diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H
index 3133376e1b4..cff8ef93d66 100644
--- a/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H
+++ b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H
@@ -539,6 +539,8 @@ fapi_try_exit:
 
     return fapi2::current_err;
 }
+
+///
 /// @brief Helper function to perform p9a OMI FIR unmasks
 /// @param[in] i_target MC target to find targets to initialize
 /// @return fapi2:ReturnCode FAPI2_RC_SUCCESS if success, else error code
@@ -546,12 +548,126 @@ fapi_try_exit:
 inline fapi2::ReturnCode after_p9a_omi_init_omi_fir_helper(const fapi2::Target<fapi2::TARGET_TYPE_MC>& i_target)
 {
     fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS;
+    fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS;
+    fapi2::ReturnCode l_rc3 = fapi2::FAPI2_RC_SUCCESS;
     fapi2::buffer<uint64_t> l_reg_data;
 
-    mss::fir::reg<P9A_MC_REG0_OMI_FIR> l_p9a_mc_omi_fir_reg(i_target, l_rc);
+    mss::fir::reg<P9A_MC_REG0_OMI_FIR> l_mc_reg0_omi_fir_reg(i_target, l_rc);
+    mss::fir::reg<P9A_MC_REG1_OMI_FIR> l_mc_reg1_omi_fir_reg(i_target, l_rc2);
+    mss::fir::reg<P9A_MC_REG2_OMI_FIR> l_mc_reg2_omi_fir_reg(i_target, l_rc3);
+
     FAPI_TRY(l_rc, "for target %s unable to create fir::reg for 0x%016x", mss::c_str(i_target), P9A_MC_REG0_OMI_FIR);
+    FAPI_TRY(l_rc2, "for target %s unable to create fir::reg for 0x%016x", mss::c_str(i_target), P9A_MC_REG1_OMI_FIR);
+    FAPI_TRY(l_rc3, "for target %s unable to create fir::reg for 0x%016x", mss::c_str(i_target), P9A_MC_REG2_OMI_FIR);
+
+    for (const auto& l_omic : mss::find_targets<fapi2::TARGET_TYPE_OMIC>(i_target))
+    {
+        for (const auto& l_omi : mss::find_targets<fapi2::TARGET_TYPE_OMI>(l_omic))
+        {
+            // Set up MC_OMI_FIR register per Axone unmask spec
+            // Note that there are child-target-specific FIR bits in these regs, so we need to check
+            // what's configured and unmask the corresponding group of FIRs in the right reg
+            // OMIC relative pos ==> REG0/1/2
+            // OMI relative pos ==> DL0/1/2
+            const auto l_omic_pos = mss::relative_pos<fapi2::TARGET_TYPE_MC>(l_omic);
+            uint8_t l_omi_pos = 0;
+            FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_OMI_DL_GROUP_POS, l_omi, l_omi_pos) );
+
+            switch(l_omic_pos)
+            {
+                case 0:
+                    switch(l_omi_pos)
+                    {
+                        case 0:
+                            l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FLIT_CE>();
+                            break;
+
+                        case 1:
+                            l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FLIT_CE>();
+                            break;
+
+                        case 2:
+                            l_mc_reg0_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FLIT_CE>();
+                            break;
+
+                        default:
+                            FAPI_ASSERT(false,
+                                        fapi2::MSS_INVALID_OMI_POSITION().
+                                        set_POSITION(l_omi_pos).
+                                        set_OMI_TARGET(l_omi),
+                                        "Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
+                            break;
+                    }
+
+                    break;
+
+                case 1:
+                    switch(l_omi_pos)
+                    {
+                        case 0:
+                            l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FLIT_CE>();
+                            break;
+
+                        case 1:
+                            l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FLIT_CE>();
+                            break;
 
-    FAPI_TRY(l_p9a_mc_omi_fir_reg.template recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FLIT_CE>().write());
+                        case 2:
+                            l_mc_reg1_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FLIT_CE>();
+                            break;
+
+                        default:
+                            FAPI_ASSERT(false,
+                                        fapi2::MSS_INVALID_OMI_POSITION().
+                                        set_POSITION(l_omi_pos).
+                                        set_OMI_TARGET(l_omi),
+                                        "Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
+                            break;
+                    }
+
+                    break;
+
+                case 2:
+                    switch(l_omi_pos)
+                    {
+                        case 0:
+                            l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL0_FLIT_CE>();
+                            break;
+
+                        case 1:
+                            l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL1_FLIT_CE>();
+                            break;
+
+                        case 2:
+                            l_mc_reg2_omi_fir_reg.recoverable_error<P9A_MC_MC_OMI_FIR_REG_DL2_FLIT_CE>();
+                            break;
+
+                        default:
+                            FAPI_ASSERT(false,
+                                        fapi2::MSS_INVALID_OMI_POSITION().
+                                        set_POSITION(l_omi_pos).
+                                        set_OMI_TARGET(l_omi),
+                                        "Invalid OMI position (%d) for %s", l_omi_pos, mss::c_str(l_omi));
+                            break;
+                    }
+
+                    break;
+
+                default:
+                    FAPI_ASSERT(false,
+                                fapi2::MSS_INVALID_OMIC_POSITION().
+                                set_POSITION(l_omic_pos).
+                                set_OMIC_TARGET(l_omic),
+                                "Invalid OMIC position (%d) for %s", l_omic_pos, mss::c_str(l_omic));
+                    break;
+            }
+        }
+    }
+
+    // Write MC_OMI_FIR registers now that they've been set up in the loop above
+    FAPI_TRY(l_mc_reg0_omi_fir_reg.write());
+    FAPI_TRY(l_mc_reg1_omi_fir_reg.write());
+    FAPI_TRY(l_mc_reg2_omi_fir_reg.write());
 
     using MCT = mss::mcTraits<mss::proc_type::AXONE>;