From 161f826cbef4562223e6d14359137e7ce001bce9 Mon Sep 17 00:00:00 2001 From: Rahul Batra Date: Wed, 15 Mar 2017 12:21:53 -0500 Subject: [PATCH] CME Pstate Updates(Platform Interdependence) - Added dpll_pstate0 calculation in pstate parameter block code Change-Id: I0e8530ab510678e839421d88930e2156ba337f74 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37982 Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Douglas R. Gilbert Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA Reviewed-by: ASHISH A. MORE Reviewed-by: Gregory S. Still Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38045 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell --- .../chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h | 11 +++++++---- .../p9/procedures/hwp/pm/p9_pstate_parameter_block.C | 5 +++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h index 35113b73c56..2b162e4177a 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h @@ -209,16 +209,16 @@ typedef struct uint8_t droop_large_override_enable; uint8_t droop_extreme_override_enable; uint8_t overvolt_override_enable; - uint16_t fmin_override_khz_enable; - uint16_t fmax_override_khz_enable; + uint8_t fmin_override_khz_enable; + uint8_t fmax_override_khz_enable; // The respecitve *_enable above indicate which index values are valid uint8_t droop_small_override[VPD_PV_POINTS]; uint8_t droop_large_override[VPD_PV_POINTS]; uint8_t droop_extreme_override[VPD_PV_POINTS]; uint8_t overvolt_override[VPD_PV_POINTS]; - uint16_t fmin_override_khz[VPD_PV_POINTS]; - uint16_t fmax_override_khz[VPD_PV_POINTS]; + uint8_t fmin_override_khz[VPD_PV_POINTS]; + uint8_t fmax_override_khz[VPD_PV_POINTS]; /// Pad structure to 8-byte alignment /// @todo pad once fully structure is complete. @@ -327,6 +327,9 @@ typedef struct /// VDM Data VDMParmBlock vdm; + /// DPLL pstate 0 value + uint32_t dpll_pstate0_value; + } LocalPstateParmBlock; #ifdef __cplusplus diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C index 6291e5550de..54f4406516e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C @@ -311,6 +311,8 @@ p9_pstate_parameter_block( const fapi2::Target& i_ // Compute VPD points p9_pstate_compute_vpd_pts(l_operating_points, &l_globalppb); + memcpy(l_globalppb.operating_points_set, l_operating_points, sizeof(l_operating_points)); + // Calculate pre-calculated slopes p9_pstate_compute_PsV_slopes(l_operating_points, &l_globalppb); @@ -339,6 +341,9 @@ p9_pstate_parameter_block( const fapi2::Target& i_ // Resonant Clock Grid Management Setup l_localppb.resclk = l_resclk_setup; + l_localppb.dpll_pstate0_value = revle32((revle32(l_localppb.operating_points[ULTRA].frequency_mhz) * 1000 / revle32( + l_globalppb.frequency_step_khz))); + // ----------------------------------------------- // OCC parameter block // -----------------------------------------------