From 29ca2d7cfcef6235f18787a942d7828f0b99e985 Mon Sep 17 00:00:00 2001 From: Devon Baughen Date: Tue, 5 May 2020 12:42:01 -0400 Subject: [PATCH] extend bootconfig0 polling to account for longer sequence CQ: SW491266 Change-Id: Iae2d757ef0141b1911de6877c25416c391e2abdd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/96367 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Daniel M Crowell Reviewed-by: Louis Stermole Dev-Ready: Louis Stermole Reviewed-by: Thi N Tran Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/96507 Reviewed-by: Jenkins Server Tested-by: Daniel M Crowell --- .../chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C index fb5fb5ebc9b..971c8c67e4b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C @@ -79,7 +79,9 @@ extern "C" FAPI_TRY(mss::exp::i2c::boot_config(i_target, l_boot_config_data)); // Check FW status for success - l_rc = mss::exp::i2c::fw_status(i_target, mss::DELAY_1MS, 100); + // Note: Extended polling count from 100 to 1000 to account for longer Boot_config_0 sequence + // in Explorer FW CL-384401. + l_rc = mss::exp::i2c::fw_status(i_target, mss::DELAY_1MS, 1000); // Note: It's still under discussion whether FIRs will be lit if BOOT_CONFIG_0 fails, and if // the registers will be clocked so we can read them. Disabling FIR checking until this