From 2e7f87d72580caac7cfb3e96e80764a94b430df5 Mon Sep 17 00:00:00 2001 From: Jacob Harvey Date: Thu, 9 Feb 2017 14:02:43 -0600 Subject: [PATCH] Disable memory throttle change_after_sync Disabled change_after_sync that sets MCAs' throttles after a sync command has been sent. The change was needed due to a hardware defect that won't be fixed Change-Id: I81e061f07a35e14c641e92a28f0a3a43ccc18289 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36231 Reviewed-by: Michael D. Pardeik Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Brian R. Silver Reviewed-by: STEPHEN GLANCY Reviewed-by: Matt K. Light Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36822 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI --- .../p9/procedures/hwp/memory/lib/mc/mc.C | 95 ++++++++++++++----- .../p9/procedures/hwp/memory/lib/mc/mc.H | 32 ++++++- .../hwp/memory/p9_mss_draminit_mc.C | 2 +- .../hwp/memory/p9_mss_throttle_mem.C | 9 +- .../attribute_info/memory_mrw_attributes.xml | 7 +- .../xml/error_info/p9_memory_mss_draminit.xml | 3 +- 6 files changed, 112 insertions(+), 36 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index 8650ad4abe0..d45b88a07e0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -63,11 +63,14 @@ enum throttle_enums NM_RAS_WEIGHT = 0b000, NM_CAS_WEIGHT = 0b001, - CHANGE_AFTER_SYNC = 0b1, + CHANGE_AFTER_SYNC_ON = 0b1, + CHANGE_AFTER_SYNC_OFF = 0b0, MAXALL_MINALL = 0b000, + //wait 16 refresh intervals of idle before powering down all ranks MIN_DOMAIN_REDUCTION_TIME = 0x10, + //wait 64 refresh intervals of idle before going into STR on all ranks ENTER_STR_TIME = 0x40 }; @@ -80,21 +83,37 @@ enum throttle_enums /// fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target& i_target) { + typedef mss::mcTraits TT; uint8_t l_pwr_cntrl = 0; fapi2::buffer l_data; FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl)); FAPI_TRY(mss::getScom(i_target, MCA_MBARPC0Q, l_data)); - l_data.insertFromRight(MAXALL_MINALL); + l_data.insertFromRight(MAXALL_MINALL); //Write data if PWR_CNTRL_REQUESTED includes power down - l_data.writeBit - ((l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR) || - (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN)); + switch (l_pwr_cntrl) + { + case PD_AND_STR: + case POWER_DOWN: + case PD_AND_STR_CLK_STOP: + l_data.setBit(); + break; + + case PD_AND_STR_OFF: + l_data.clearBit(); + break; + + default: + // Chief system engineer would reaally have to mess up here since _OFF is 0 + FAPI_ERR("ATTR_MSS_MRW_POWER_CONTROL_REQUESTED not set correctly in MRW"); + fapi2::Assert(false); + break; + } //Set the MIN_DOMAIN_REDUCTION time - l_data.insertFromRight + l_data.insertFromRight (MIN_DOMAIN_REDUCTION_TIME); FAPI_TRY(mss::putScom(i_target, MCA_MBARPC0Q, l_data) ); @@ -113,6 +132,7 @@ fapi_try_exit: /// fapi2::ReturnCode set_str_reg(const fapi2::Target& i_target) { + typedef mss::mcTraits TT; uint8_t l_str_enable = 0; fapi2::buffer l_data; @@ -120,11 +140,29 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target& i_tar FAPI_TRY(mss::getScom(i_target, MCA_MBASTR0Q, l_data)); //Write bit if STR should be enabled - l_data.writeBit - ((l_str_enable == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_STR) || - (l_str_enable == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR)); - - l_data.insertFromRight(ENTER_STR_TIME); + switch (l_str_enable) + { + case PD_AND_STR: + case PD_AND_STR_CLK_STOP: + l_data.setBit(); + break; + + case POWER_DOWN: + case PD_AND_STR_OFF: + l_data.clearBit(); + break; + + default: + // System engineer would reaally have to mess up here since _OFF is 0 + FAPI_ERR("ATTR_MSS_MRW_POWER_CONTROL_REQUESTED not set correctly in MRW"); + fapi2::Assert(false); + break; + } + + // MCA_MBASTR0Q_CFG_DIS_CLK_IN_STR: Set to 1 for PD_AND_STR_CLK_STOP, otherwise clear the bit + l_data.writeBit(l_str_enable == PD_AND_STR_CLK_STOP); + + l_data.insertFromRight(ENTER_STR_TIME); FAPI_TRY(mss::putScom(i_target, MCA_MBASTR0Q, l_data) ); @@ -140,8 +178,11 @@ fapi_try_exit: /// @return fapi2::fapi2_rc_success if ok /// @note sets MCA_MBA_FARB3Q /// + fapi2::ReturnCode set_nm_support (const fapi2::Target& i_target) { + typedef mss::mcTraits TT; + uint16_t l_run_slot = 0; uint16_t l_run_port = 0; uint32_t l_throttle_denominator = 0; @@ -159,12 +200,15 @@ fapi2::ReturnCode set_nm_support (const fapi2::Target& i l_throttle_denominator); FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data)); - l_data.insertFromRight(l_run_slot); - l_data.insertFromRight(l_run_port); - l_data.insertFromRight(l_throttle_denominator); - l_data.insertFromRight(NM_RAS_WEIGHT); - l_data.insertFromRight(NM_CAS_WEIGHT); - l_data.writeBit(CHANGE_AFTER_SYNC); + l_data.insertFromRight(l_run_slot); + l_data.insertFromRight(l_run_port); + l_data.insertFromRight(l_throttle_denominator); + l_data.insertFromRight(NM_RAS_WEIGHT); + l_data.insertFromRight(NM_CAS_WEIGHT); + + // If set, changes to cfg_nm_n_per_slot, cfg_nm_n_per_port, cfg_nm_m, min_max_domains will only be applied after a pc_sync command is seen + // Set to disable permanently due to hardware design bug (HW403028) that won't be changed + l_data.writeBit(CHANGE_AFTER_SYNC_OFF); FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); @@ -179,9 +223,12 @@ fapi_try_exit: /// @param[in] i_target the mca target /// @return fapi2::fapi2_rc_success if ok /// @note sets MCA_MBA_FARB4Q +/// @note used to set throttle window (N throttles / M clocks) /// fapi2::ReturnCode set_safemode_throttles(const fapi2::Target& i_target) { + typedef mss::mcTraits TT; + fapi2::buffer l_data; uint16_t l_throttle_per_slot = 0; uint32_t l_throttle_denominator = 0; @@ -190,8 +237,8 @@ fapi2::ReturnCode set_safemode_throttles(const fapi2::Target(l_throttle_denominator); - l_data.insertFromRight(l_throttle_per_slot); + l_data.insertFromRight(l_throttle_denominator); + l_data.insertFromRight(l_throttle_per_slot); FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB4Q, l_data) ); return fapi2::FAPI2_RC_SUCCESS; @@ -210,6 +257,8 @@ fapi_try_exit: /// fapi2::ReturnCode set_runtime_throttles_to_safe(const fapi2::Target& i_target) { + typedef mss::mcTraits TT; + fapi2::buffer l_data; uint16_t l_throttle_per_port = 0; uint32_t l_throttle_denominator = 0; @@ -219,9 +268,9 @@ fapi2::ReturnCode set_runtime_throttles_to_safe(const fapi2::Target(l_throttle_per_port); - l_data.insertFromRight(l_throttle_per_port); - l_data.insertFromRight(l_throttle_denominator); + l_data.insertFromRight(l_throttle_per_port); + l_data.insertFromRight(l_throttle_per_port); + l_data.insertFromRight(l_throttle_denominator); FAPI_TRY(mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H index 890eb2343f4..5ec586f8cca 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -106,6 +106,32 @@ class mcTraits BANK_GROUP0_BIT_MAP_LEN = MCS_PORT02_MCP0XLT2_BANK_GROUP0_BIT_MAP_LEN, BANK_GROUP1_BIT_MAP = MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP, BANK_GROUP1_BIT_MAP_LEN = MCS_PORT02_MCP0XLT2_BANK_GROUP1_BIT_MAP_LEN, + RUNTIME_N_SLOT = MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT, + RUNTIME_N_SLOT_LEN = MCA_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN, + RUNTIME_N_PORT = MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT, + RUNTIME_N_PORT_LEN = MCA_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN, + RUNTIME_M = MCA_MBA_FARB3Q_CFG_NM_M, + RUNTIME_M_LEN = MCA_MBA_FARB3Q_CFG_NM_M_LEN, + EMERGENCY_N = MCA_MBA_FARB4Q_EMERGENCY_N, + EMERGENCY_N_LEN = MCA_MBA_FARB4Q_EMERGENCY_N_LEN, + EMERGENCY_M = MCA_MBA_FARB4Q_EMERGENCY_M, + EMERGENCY_M_LEN = MCA_MBA_FARB4Q_EMERGENCY_M_LEN, + CFG_STR_ENABLE = MCA_MBASTR0Q_CFG_STR_ENABLE, + + MIN_DOMAIN_REDUCTION_ENABLE = MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE, + MIN_MAX_DOMAINS_ENABLE = MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE, + MIN_DOMAIN_REDUCTION_TIME = MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME, + MIN_DOMAIN_REDUCTION_TIME_LEN = MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN, + ENTER_STR_TIME_POS = MCA_MBASTR0Q_CFG_ENTER_STR_TIME, + ENTER_STR_TIME_LEN = MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN, + RAS_WEIGHT_LEN = MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN, + RAS_WEIGHT_POS = MCA_MBA_FARB3Q_CFG_NM_RAS_WEIGHT, + CAS_WEIGHT_LEN = MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN, + CAS_WEIGHT_POS = MCA_MBA_FARB3Q_CFG_NM_CAS_WEIGHT, + NM_CHANGE_AFTER_SYNC = MCA_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC, + CFG_MIN_MAX_DOMAINS = MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, + CFG_MIN_MAX_DOMAINS_LEN = MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN, + }; }; @@ -148,6 +174,10 @@ enum BANK_GROUP_0_BIT_INDEX = 29, BANK_GROUP_1_BIT_INDEX = 30, MAX_TRANSLATIONS = 31, + PD_AND_STR = fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR, + PD_AND_STR_CLK_STOP = fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP, + POWER_DOWN = fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN, + PD_AND_STR_OFF = fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_OFF, }; namespace mc diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index a3aa5d35d80..030106e537d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -97,7 +97,7 @@ extern "C" const bool is_pwr_cntrl = ((l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_POWER_CONTROL_REQUESTED_POWER_DOWN) || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR) - || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_STR)); + || (l_pwr_cntrl == fapi2::ENUM_ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED_PD_AND_STR_CLK_STOP)); l_data.writeBit(is_pwr_cntrl); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_throttle_mem.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_throttle_mem.C index 15783f48786..1c15dd7656e 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_throttle_mem.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_throttle_mem.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,6 +36,7 @@ #include #include #include +#include using fapi2::TARGET_TYPE_MCS; extern "C" @@ -49,6 +50,7 @@ extern "C" /// fapi2::ReturnCode p9_mss_throttle_mem( const fapi2::Target& i_target ) { + typedef mss::mcTraits TT; FAPI_INF("Start throttle mem"); for (const auto& l_mca : mss::find_targets (i_target)) @@ -64,11 +66,10 @@ extern "C" fapi2::buffer l_data; FAPI_TRY(mss::getScom(l_mca, MCA_MBA_FARB3Q, l_data)); - l_data.insertFromRight(l_runtime_slot); - l_data.insertFromRight(l_runtime_port); + l_data.insertFromRight(l_runtime_slot); + l_data.insertFromRight(l_runtime_port); FAPI_TRY( mss::putScom(l_mca, MCA_MBA_FARB3Q, l_data) ); - } FAPI_INF("End throttle mem"); diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 10098fe835f..02556a10aac 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -250,7 +250,7 @@ Used by OCC when exiting idle power-save mode uint8 - OFF = 0x00, POWER_DOWN = 0x01, STR = 0x02, PD_AND_STR = 0x03 + OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 OFF @@ -265,11 +265,10 @@ Used by OCC when entering idle power-save mode uint8 - OFF = 0x00, POWER_DOWN = 0x01, STR = 0x02, PD_AND_STR = 0x03 + OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 OFF - mrw_idle_power_control_requested @@ -285,7 +284,6 @@ - mrw_vmem_regulator_power_limit_per_dimm_adj_enable @@ -302,7 +300,6 @@ cW - mrw_vmem_regulator_power_limit_per_dimm_ddr3 diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml index cb76ed4cf57..ec856731524 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml @@ -5,7 +5,7 @@ - + @@ -76,5 +76,4 @@ -