From 53b580bab27316840520a61c73a036c647b60ac3 Mon Sep 17 00:00:00 2001 From: Jacob Harvey Date: Wed, 29 Jun 2016 11:12:59 -0500 Subject: [PATCH] Implementing thermal_init Change-Id: I4fb1fb024d690cc2e5c60fb3bc29036e12f70acb Original-Change-Id: I0fc6f6ab6f209f7399d0f5369b03a4504838a026 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26739 Tested-by: Jenkins Server Reviewed-by: Brian R. Silver Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: JACOB L. HARVEY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82426 Reviewed-by: Daniel M Crowell Tested-by: Daniel M Crowell --- .../p9/procedures/hwp/memory/lib/mc/mc.C | 144 +++++------------- 1 file changed, 38 insertions(+), 106 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index 19308668da0..42dd1255e01 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -28,17 +28,15 @@ /// @brief Subroutines to manipulate the memory controller /// // *HWP HWP Owner: Brian Silver -// *HWP HWP Backup: Andre Marin +// *HWP HWP Backup: Jacob Harvey // *HWP Team: Memory // *HWP Level: 2 // *HWP Consumed by: FSP:HB #include -#include - #include -#include #include +#include using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; @@ -130,16 +128,16 @@ fapi2::ReturnCode dump_regs( const fapi2::Target& i_target ) {"MCS_MCWATCNTL", MCS_MCWATCNTL }, }; - for (auto r : l_mcs_registers) + for (const auto& r : l_mcs_registers) { fapi2::buffer l_data; FAPI_TRY( mss::getScom(i_target, r.second, l_data) ); FAPI_DBG("dump %s: 0x%016lx 0x%016lx", r.first, r.second, l_data); } - for (auto p : i_target.getChildren()) + for (const auto& p : find_targets(i_target)) { - for (auto r : l_mba_registers) + for (const auto r : l_mba_registers) { fapi2::buffer l_data; FAPI_TRY( mss::getScom(p, r.second, l_data) ); @@ -151,131 +149,65 @@ fapi_try_exit: return fapi2::current_err; } +namespace mc +{ + /// -/// @brief Perform initializations for the MC (MCA) -/// @param[in] i_target, the MCA to initialize -/// @return FAPI2_RC_SUCCESS iff ok +/// @brief safemode throttle values defined from MRW attributes +/// @param[in] i_target the MCA target +/// @return fapi2::FAPI2_RC_SUCCESS if ok +/// @note sets safemode values for emergency mode and regular throttling /// -template<> -fapi2::ReturnCode mc::scominit(const fapi2::Target& i_target) +fapi2::ReturnCode thermal_throttle_scominit (const fapi2::Target& i_target) { uint32_t l_throttle_denominator = 0; - FAPI_TRY( mss::runtime_mem_m_dram_clocks(i_target, l_throttle_denominator) ); - - // #Register Name Final Arb Parms - // #Mnemonic MBA_FARB0Q - // #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use - // #Description FARB command control - // #1. FARB0 bit 38: cfg_parity_after_cmd - // # - set this bit if DDR3 and (RDIMM or LDRIMM) - // - // # - clear this bit if DDR4 and (RDIMM or LDRIMM) - // #2. FARB0 bit 60: cfg_ignore_rcd_parity_err - // # - clear this bit if (RDIMM or LDRIMM) - // #3. FARB0 bit 61: cfg_enable_rcd_rw_retry - // # - set this bit if (RDIMM or LDRIMM) + FAPI_TRY( mss::mem_m_dram_clocks( i_target, l_throttle_denominator) ); - // Nimbus is always LR/RDIMM, DDR4. - // Not sure what happened to cfg_ignore_rcd_parity_err, cfg_enable_rcd_rw_retry - perhaps they're always ok since we don't - // support anything else? { fapi2::buffer l_data; + FAPI_TRY(mss::getScom(i_target, MCA_MBA_FARB3Q, l_data)); - l_data.setBit(); - FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB0Q, l_data) ); - } - - { - // FABR1Q - Chip ID bits - } - { - // FARB2Q - ODT bits - } - - // #Register Name N/M Throttling Control - // #Mnemonic MBA_FARB3Q - // #Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use - // #Description N/M throttling control (Centaur only) - // # 0:14 cfg_nm_n_per_mba MSS_MEM_THROTTLED_N_COMMANDS_PER_MBA (Centaur) - // # 15:30 cfg_nm_n_per_chip MSS_MEM_THROTTLED_N_COMMANDS_PER_CHIP (Centaur) - // # 0:14 cfg_nm_n_per_slot MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT (Nimbus) - // # 15:30 cfg_nm_n_per_port MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT (Nimbus) - // # 31:44 cfg_nm_m MSS_MEM_THROTTLED_M_DRAM_CLOCKS - // # 51 cfg_nm_per_slot_enabled 1 (not on Nimbus?) - // # 52 cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else (not on Nimbus?) - // #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT - // #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT - { - fapi2::buffer l_data; - uint32_t l_throttle_per_slot = 0; uint32_t l_throttle_per_port = 0; - uint8_t l_ras_weight = 0; - uint8_t l_cas_weight = 0; - FAPI_TRY( mss::runtime_mem_throttled_n_commands_per_slot(i_target, l_throttle_per_slot) ); - FAPI_TRY( mss::runtime_mem_throttled_n_commands_per_port(i_target, l_throttle_per_port) ); - FAPI_TRY( mss::throttle_control_ras_weight(i_target, l_ras_weight) ); - FAPI_TRY( mss::throttle_control_cas_weight(i_target, l_cas_weight) ); + FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_port( l_throttle_per_port) ); - l_data.insertFromRight(l_throttle_per_slot); + l_data.insertFromRight(l_throttle_per_port); l_data.insertFromRight(l_throttle_per_port); l_data.insertFromRight(l_throttle_denominator); - l_data.insertFromRight(l_ras_weight); - l_data.insertFromRight(l_ras_weight); + + l_data.clearBit(); FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB3Q, l_data) ); - } - // Doesn't appear to be a row-hammer-mode in Nimbus - // # -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_SLOT - // # -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLED_M_DRAM_CLOCKS + } { fapi2::buffer l_data; uint32_t l_throttle_per_slot = 0; - FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_slot(l_throttle_per_slot) ); + FAPI_TRY( mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_slot) ); + FAPI_TRY( mss::getScom(i_target, MCA_MBA_FARB4Q, l_data) ); l_data.insertFromRight(l_throttle_denominator); l_data.insertFromRight(l_throttle_per_slot); - FAPI_TRY( mss::putScom(i_target, MCA_MBA_FARB4Q, l_data) ); } - - { - // TMR0Q - DDR data bus timing parameters - } - - { - // TMR1Q - DDR bank busy parameters - } - - { - // DSM0Q - Data State Machine Configurations - } - - { - // MBAREF0Q mba01 refresh settings - } - - { - // MBAPC0Q power control settings reg 0 - // MBAPC1Q power control settings reg 1 - } - - { - // MBAREF1Q MBA01 Rank-to-primary-CKE mapping table - // Doesn't exist in Nimbus. Leaving this as a comment to note that we didn't forget it. - // CKEs are fixed to chip selects for all P9 configs - } - - { - // CAL0Q (this timer to be used for zq cal) - // CAL1Q (this timer to be used for mem cal) - // CAL3Q (this timer to be used for mem cal) - } - fapi_try_exit: return fapi2::current_err; } - +/// +/// @brief Disable emergency mode throttle for thermal_init +/// @param[in] i_target the MCS target +/// @return fapi2::FAPI2_RC_SUCCESS if ok +/// @note Clears MCMODE0_ENABLE_EMER_THROTTLE bit in MCSMODE0 +/// +fapi2::ReturnCode disable_emergency_throttle (const fapi2::Target& i_target) +{ + fapi2::buffer l_data; + FAPI_TRY( mss::getScom(i_target, MCS_MCMODE0, l_data)); + l_data.clearBit(); + FAPI_TRY( mss::putScom(i_target, MCS_MCMODE0, l_data)); +fapi_try_exit: + return fapi2::current_err; } +} // namespace mc +} //close namespace mss