diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H
index 1b10be328a7..c0f73e540e1 100644
--- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H
+++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H
@@ -3250,6 +3250,17 @@ static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R6 = 0x4065900ull;
 static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R7 = 0x4065D00ull;
 static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R8 = 0x4066100ull;
 static const uint64_t EXP_DDR4_PHY_DDR_PHY_CONTROL    = 0x6000118ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS = 0x4040390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE1_DXLCDLSTATUS = 0x4044390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE2_DXLCDLSTATUS = 0x4048390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE3_DXLCDLSTATUS = 0x404C390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE4_DXLCDLSTATUS = 0x4050390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE5_DXLCDLSTATUS = 0x4054390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE6_DXLCDLSTATUS = 0x4058390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE7_DXLCDLSTATUS = 0x405C390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE8_DXLCDLSTATUS = 0x4060390ull;
+static const uint64_t EXP_DDR4_PHY_DBYTE9_DXLCDLSTATUS = 0x4064390ull;
+static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL = 0x408038Cull;
 
 
 
diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H
index fc02d5360e2..6e4126bbe1f 100644
--- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H
+++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H
@@ -53,5 +53,11 @@ static const uint8_t EXP_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL              =
 static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_AC_SELECT                = 63 - 8;
 static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK           = 63 - 5;
 static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK_LEN       = 2;
+static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS_DXLCDLFINESNAPVAL = 63 - 9;
+static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS_DXLCDLFINESNAPVAL_LEN = 10;
+static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLTSTENABLE = 63 - 11;
+static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLFINESNAP = 63 - 10;
+static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLSTATUSSEL = 63 - 15;
+static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLSTATUSSEL_LEN = 4;
 
 #endif