From 5f5573b5b0e1eebfa7e7208e95adfb00fe895da1 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Thu, 5 Mar 2020 14:49:55 -0500 Subject: [PATCH] Adds utility to read explorer delay tap size Change-Id: Iff0a0075cfbe906a65b9724cf8f0ecf11c1215f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/92916 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: Louis Stermole Reviewed-by: ANDRE A MARIN Reviewed-by: Mark Pizzutillo Tested-by: Hostboot CI Reviewed-by: Jennifer A Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/92921 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes --- .../common/include/explorer_scom_addresses_fixes.H | 11 +++++++++++ .../include/explorer_scom_addresses_fld_fixes.H | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H index 1b10be328a7..c0f73e540e1 100644 --- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H @@ -3250,6 +3250,17 @@ static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R6 = 0x4065900ull; static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R7 = 0x4065D00ull; static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R8 = 0x4066100ull; static const uint64_t EXP_DDR4_PHY_DDR_PHY_CONTROL = 0x6000118ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS = 0x4040390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_DXLCDLSTATUS = 0x4044390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_DXLCDLSTATUS = 0x4048390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_DXLCDLSTATUS = 0x404C390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_DXLCDLSTATUS = 0x4050390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_DXLCDLSTATUS = 0x4054390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_DXLCDLSTATUS = 0x4058390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_DXLCDLSTATUS = 0x405C390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_DXLCDLSTATUS = 0x4060390ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_DXLCDLSTATUS = 0x4064390ull; +static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL = 0x408038Cull; diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H index fc02d5360e2..6e4126bbe1f 100644 --- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H @@ -53,5 +53,11 @@ static const uint8_t EXP_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL = static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_AC_SELECT = 63 - 8; static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK = 63 - 5; static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK_LEN = 2; +static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS_DXLCDLFINESNAPVAL = 63 - 9; +static const uint64_t EXP_DDR4_PHY_DBYTE0_DXLCDLSTATUS_DXLCDLFINESNAPVAL_LEN = 10; +static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLTSTENABLE = 63 - 11; +static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLFINESNAP = 63 - 10; +static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLSTATUSSEL = 63 - 15; +static const uint64_t EXP_DDR4_PHY_MASTER0_LCDLDBGCNTL_LCDLSTATUSSEL_LEN = 4; #endif