diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_mrs_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_mrs_traits.H index 2b14a8152e8..55ab88f81c5 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_mrs_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_mrs_traits.H @@ -62,15 +62,6 @@ class mrsTraits static constexpr uint64_t TCCD_S = 4; static constexpr uint64_t TMRD = 16; - /// - /// @brief Returns an error for bad mrs parameter - /// @return mrs error - /// - static fapi2::MSS_BAD_MR_PARAMETER bad_mr_parameter() - { - return fapi2::MSS_BAD_MR_PARAMETER(); - } - /// /// @brief Returns if rcd mirror mode on /// @return false, currently set to disabled @@ -84,13 +75,36 @@ class mrsTraits /// /// @brief Returns if mirror mode is enabled, currently set to disabled /// @param[in] const ref to the fapi2::Target + /// @param[in] i_rank the rank on which to operate from the port perspective /// @param[out] ref to the value uint8_t /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// static fapi2::ReturnCode mirror_mode(const fapi2::Target& i_target, + const uint64_t i_rank, uint8_t& o_value) { - return mss::attr::get_exp_dram_address_mirroring(i_target, o_value); + constexpr uint64_t SINGLE_RANK_MASK = 0x1; + + // Makes sure that we have a good rank passed in + FAPI_ASSERT(i_rank < mss::exp::MAX_MRANK_PER_PORT, + fapi2::MSS_INVALID_RANK(). + set_FUNCTION(mss::generic_ffdc_codes::MRS_MIRROR_MODE). + set_RANK(i_rank). + set_PORT_TARGET(mss::find_target(i_target)), + "%s mirror mode received invalid rank: %d", + mss::c_str(i_target), i_rank); + + FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_target, o_value)); + + { + const auto l_dimm_rank = i_rank % mss::exp::MAX_RANK_PER_DIMM; + o_value = o_value >> l_dimm_rank; + o_value &= SINGLE_RANK_MASK; + } + + return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: + return fapi2::current_err; } /// diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C index 0adefec0728..a22ecebd677 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C @@ -51,35 +51,60 @@ namespace unmask { /// -/// @brief Check if any dimms exist that have RCD enabled +/// @brief Check if any dimms exist that have RCD enabled - explorer/PORT specialization /// @param[in] i_target - the fapi2::Target we are starting from /// @param[out] o_has_rcd - true iff any DIMM with RCD detected /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode has_rcd( const fapi2::Target& i_target, +fapi2::ReturnCode has_rcd( const fapi2::Target& i_target, bool& o_has_rcd ) { // Assume RCD is not supported at beginning of check o_has_rcd = false; - // Nested for loops to determine DIMM type if DIMMs exist - for (const auto& l_port : mss::find_targets(i_target)) + // Loop over all DIMM's and determine if we have an RCD + for(const auto& l_dimm : mss::find_targets(i_target)) { - for(const auto& l_dimm : mss::find_targets(l_port)) - { - uint8_t l_dimm_type = 0; - uint8_t l_rcd_supported = 0; + uint8_t l_dimm_type = 0; + uint8_t l_rcd_supported = 0; + + FAPI_TRY(mss::attr::get_dimm_type(l_dimm, l_dimm_type)); + FAPI_TRY(mss::attr::get_supported_rcd(l_dimm, l_rcd_supported)); + + // OR with tmp_rcd to maintain running true/false if RCD on *any* DIMM + o_has_rcd |= ((l_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM) || + (l_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM)); + + o_has_rcd |= (l_rcd_supported == fapi2::ENUM_ATTR_MEM_EFF_SUPPORTED_RCD_RCD_PER_CHANNEL_1); + } - FAPI_TRY(mss::attr::get_dimm_type(l_dimm, l_dimm_type)); - FAPI_TRY(mss::attr::get_supported_rcd(l_dimm, l_rcd_supported)); + return fapi2::FAPI2_RC_SUCCESS; - // OR with tmp_rcd to maintain running true/false if RCD on *any* DIMM - o_has_rcd |= ((l_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM) || - (l_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM)); +fapi_try_exit: - o_has_rcd |= (l_rcd_supported == fapi2::ENUM_ATTR_MEM_EFF_SUPPORTED_RCD_RCD_PER_CHANNEL_1); - } + return fapi2::current_err; +} + +/// +/// @brief Check if any dimms exist that have RCD enabled - explorer/OCMB specialization +/// @param[in] i_target - the fapi2::Target we are starting from +/// @param[out] o_has_rcd - true iff any DIMM with RCD detected +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode has_rcd( const fapi2::Target& i_target, + bool& o_has_rcd ) +{ + // Assume RCD is not supported at beginning of check + o_has_rcd = false; + + // Nested for loops to determine DIMM type if DIMMs exist + for (const auto& l_port : mss::find_targets(i_target)) + { + bool l_current_port_rcd = false; + FAPI_TRY(has_rcd(l_port, l_current_port_rcd)); + o_has_rcd |= l_current_port_rcd; } return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C index 349e531ea44..99448231189 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C @@ -109,5 +109,208 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Parse the MRS data from the response to correct attributes +/// @param[in] i_target OCMB chip +/// @param[in] i_resp MRS response struct +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode parse_mrs_data_attributes(const fapi2::Target& i_target, + const user_response_mrs_msdg_t& i_resp) +{ + using TT = mss::rank::rankTraits; + + uint8_t l_temp_attr = 0; + + fapi2::buffer l_MR0(i_resp.MR0); + fapi2::buffer l_MR1(i_resp.MR1[0]); + fapi2::buffer l_MR2(i_resp.MR2[0]); + fapi2::buffer l_MR3(i_resp.MR3); + fapi2::buffer l_MR4(i_resp.MR4); + fapi2::buffer l_MR5(i_resp.MR5[0]); + fapi2::buffer l_MR6(i_resp.MR6[0][0]); + + for (const auto& l_port_target : mss::find_targets(i_target)) + { + uint8_t l_odic_arr[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM] = {0}; + uint8_t l_rtt_nom_arr[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM] = {0}; + uint8_t l_rtt_wr_arr[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM] = {0}; + uint8_t l_rtt_park_arr[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM] = {0}; + uint8_t l_vrefdq_value[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM][mss::exp::MAX_NIBBLES_PER_PORT] = {0}; + uint8_t l_vrefdq_range[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM][mss::exp::MAX_NIBBLES_PER_PORT] = {0}; + uint8_t l_vrefdq_enable[mss::exp::MAX_DIMM_PER_PORT][TT::MAX_RANKS_PER_DIMM][mss::exp::MAX_NIBBLES_PER_PORT] = {0}; + + std::vector> l_ranks; + FAPI_TRY(mss::rank::ranks_on_port(l_port_target, l_ranks)); + + // Parse MR0 Attributes + l_temp_attr = l_MR0.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_rbt(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR0.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_tm(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR0.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_dll_reset(l_port_target, l_temp_attr) ); + + l_temp_attr = 0; + l_MR0.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_dram_burst_length(l_port_target, l_temp_attr) ); + + // Parse MR1 Attributes + l_temp_attr = l_MR1.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_dll_enable(l_port_target, l_temp_attr) ); + + l_temp_attr = 0; + l_MR1.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_dram_al(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR1.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_wr_lvl_enable(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR1.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_tdqs(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR1.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_dram_output_buffer(l_port_target, l_temp_attr) ); + + // Parse MR2 Attributes + l_temp_attr = 0; + l_MR2.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_dram_lpasr(l_port_target, l_temp_attr) ); + + // Parse MR3 Attributes + l_temp_attr = 0; + l_MR3.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_mpr_page(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR3.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_mpr_mode(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR3.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_geardown_mode(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR3.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_per_dram_access(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR3.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_temp_readout(l_port_target, l_temp_attr) ); + + l_temp_attr = 0; + l_MR3.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_crc_wr_latency(l_port_target, l_temp_attr) ); + + l_temp_attr = 0; + l_MR3.extractToRight(l_temp_attr); + FAPI_TRY( mss::attr::set_exp_resp_mpr_rd_format(l_port_target, l_temp_attr) ); + + // Parse MR4 Attributes + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_max_powerdown_mode(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_internal_vref_monitor(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_self_ref_abort(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_rd_preamble_train(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_rd_preamble(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR4.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_wr_preamble(l_port_target, l_temp_attr) ); + + // Parse MR5 Attributes + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_crc_error_clear(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_ca_parity_error_status(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_odt_input_buff(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_ca_parity(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_data_mask(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_write_dbi(l_port_target, l_temp_attr) ); + + l_temp_attr = l_MR5.getBit(); + FAPI_TRY( mss::attr::set_exp_resp_read_dbi(l_port_target, l_temp_attr) ); + + // Parse rank based MRs + // Note: we're only parsing for existing ranks + // Any ranks that do not exist will have 0 values for their attributes + // That's ok, we should not use those values anyways + for(const auto& l_rank_info : l_ranks) + { + const auto l_phy_rank = l_rank_info.get_phy_rank(); + const auto l_dimm_rank = l_rank_info.get_dimm_rank(); + const auto l_dimm_index = mss::index(l_rank_info.get_dimm_target()); + + // Set Rank level MRs + fapi2::buffer l_MR1_Rank(i_resp.MR1[l_phy_rank]); + fapi2::buffer l_MR2_Rank(i_resp.MR2[l_phy_rank]); + fapi2::buffer l_MR5_Rank(i_resp.MR5[l_phy_rank]); + + l_temp_attr = 0; + l_MR1_Rank.extractToRight(l_temp_attr); + l_odic_arr[l_dimm_index][l_dimm_rank] = l_temp_attr; + + l_temp_attr = 0; + l_MR1_Rank.extractToRight(l_temp_attr); + l_rtt_nom_arr[l_dimm_index][l_dimm_rank] = l_temp_attr; + + l_temp_attr = 0; + l_MR2_Rank.extractToRight(l_temp_attr); + l_rtt_wr_arr[l_dimm_index][l_dimm_rank] = l_temp_attr; + + l_temp_attr = 0; + l_MR5_Rank.extractToRight(l_temp_attr); + l_rtt_park_arr[l_dimm_index][l_dimm_rank] = l_temp_attr; + + // Set DRAM based MRs + for (int d = 0; d < mss::exp::MAX_NIBBLES_PER_PORT; d++) + { + fapi2::buffer l_MR6_Rank(i_resp.MR6[l_phy_rank][d]); + + l_temp_attr = l_MR6.getBit(); + l_vrefdq_range[l_dimm_index][l_dimm_rank][d] = l_temp_attr; + + l_temp_attr = l_MR6.getBit(); + l_vrefdq_enable[l_dimm_index][l_dimm_rank][d] = l_temp_attr; + + l_temp_attr = 0; + l_MR6_Rank.extractToRight(l_temp_attr); + l_vrefdq_value[l_dimm_index][l_dimm_rank][d] = l_temp_attr; + + } // End of DRAM loop + + } // End rank loop + + FAPI_TRY( mss::attr::set_exp_resp_vref_dq_train_value(l_port_target, l_vrefdq_value) ); + FAPI_TRY( mss::attr::set_exp_resp_vref_dq_train_range(l_port_target, l_vrefdq_range) ); + FAPI_TRY( mss::attr::set_exp_resp_vref_dq_train_enable(l_port_target, l_vrefdq_enable) ); + FAPI_TRY( mss::attr::set_exp_resp_dram_odic(l_port_target, l_odic_arr) ); + FAPI_TRY( mss::attr::set_exp_resp_dram_rtt_nom(l_port_target, l_rtt_nom_arr) ); + FAPI_TRY( mss::attr::set_exp_resp_dram_rtt_park(l_port_target, l_rtt_park_arr) ); + FAPI_TRY( mss::attr::set_exp_resp_dram_rtt_wr(l_port_target, l_rtt_wr_arr) ); + + } // End port loop + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); + return fapi2::current_err; +} + } // ns exp } // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H index fe7aa199253..e0d18cf656c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H @@ -42,14 +42,83 @@ #include #include #include -#include -#include +#include +#include namespace mss { namespace exp { +/// +/// @brief Holds all the masks for the MR attributes in MRs data +/// @note The values here are in terms of where they will be in the cronus buffers +/// +enum mrs_bits : uint16_t +{ + // MR0 Values + MR0_EFF_DRAM_RBT = 12, + MR0_EFF_DRAM_TM = 8, + MR0_EFF_DRAM_DLL_RESET = 7, + MR0_EFF_BURST_LENGTH = 14, + MR0_EFF_BURST_LENGTH_LEN = 2, + + // MR1 Values + MR1_EFF_DRAM_DLL_ENABLE = 15, + MR1_EFF_DRAM_ODIC = 13, + MR1_EFF_DRAM_ODIC_LEN = 2, + MR1_EFF_DRAM_AL = 11, + MR1_EFF_DRAM_AL_LEN = 2, + MR1_EFF_DRAM_WR_LVL_ENABLE = 8, + MR1_EFF_DRAM_RTT_NOM = 5, + MR1_EFF_DRAM_RTT_NOM_LEN = 3, + MR1_EFF_DRAM_TDQS = 4, + MR1_EFF_DRAM_OUTPUT_BUFFER = 3, + + // MR2 Values + MR2_EFF_DRAM_LPASR = 8, + MR2_EFF_DRAM_LPASR_LEN = 2, + MR2_EFF_DRAM_RTT_WR = 4, + MR2_EFF_DRAM_RTT_WR_LEN = 3, + + // MR3 Values + MR3_EFF_MPR_MODE = 13, // Needs confirmation + MR3_EFF_MPR_PAGE = 14, + MR3_EFF_MPR_PAGE_LEN = 2, + MR3_EFF_GEARDOWN_MODE = 12, + MR3_EFF_PER_DRAM_ACCESS = 11, + MR3_EFF_TEMP_READOUT = 10, + MR3_EFF_CRC_WR_LATENCY = 5, + MR3_EFF_CRC_WR_LATENCY_LEN = 2, + MR3_EFF_MPR_RD_FORMAT = 3, + MR3_EFF_MPR_RD_FORMAT_LEN = 2, + + // MR4 Values + MR4_EFF_MAX_POWERDOWN_MODE = 14, + MR4_EFF_INTERNAL_VREF_MONITOR = 11, + MR4_EFF_SELF_REF_ABORT = 6, + MR4_EFF_RD_PREAMBLE_TRAIN = 5, + MR4_EFF_RD_PREAMBLE = 4, + MR4_EFF_WR_PREAMBLE = 3, + + // MR5 Values + MR5_EFF_CRC_ERROR_CLEAR = 12, + MR5_EFF_CA_PARITY_ERROR_STATUS = 11, + MR5_EFF_ODT_INPUT_BUFF = 10, + MR5_EFF_CA_PARITY = 6, + MR5_EFF_DATA_MASK = 5, + MR5_EFF_WRITE_DBI = 4, + MR5_EFF_READ_DBI = 3, + MR5_EFF_DRAM_RTT_PARK = 7, + MR5_EFF_DRAM_RTT_PARK_LEN = 3, + + // MR6 Values + MR6_VREFDQ_TRAINING_VALUE = 10, + MR6_VREFDQ_TRAINING_VALUE_LEN = 6, + MR6_VREFDQ_TRAINING_RANGE = 9, + MR6_VREFDQ_TRAINING_ENABLE = 8, +}; + /// /// @brief Read eye capture response data from explorer data buffer /// @@ -169,6 +238,15 @@ inline void read_eye_capture_response(const fapi2:: return; } +/// +/// @brief Parse the MRS data from the response to correct attributes +/// @param[in] i_target OCMB chip +/// @param[in] i_resp MRS response struct +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode parse_mrs_data_attributes(const fapi2::Target& i_target, + const user_response_mrs_msdg_t& i_resp); + /// /// @brief Read the common block of fields from the training response structs /// @@ -238,6 +316,9 @@ fapi2::ReturnCode read_tm_err_mrs_rc_response(const fapi2::Target exp_resp_ddr4_f1rc05 + + + ATTR_MSS_EXP_RESP_DRAM_RBT + TARGET_TYPE_MEM_PORT + + Read Burst Type from DDR4 DRAM Spec + This is for DDR4 MRS0. + From user_response_mrs_msdg_t in draminit. + + + uint8 + SEQUENTIAL = 0, INTERLEAVE = 1 + + exp_resp_dram_rbt + + + + ATTR_MSS_EXP_RESP_DRAM_TM + TARGET_TYPE_MEM_PORT + + Test Mode from DDR4 DRAM Spec + This is for DDR4 MRS0. + From user_response_mrs_msdg_t in draminit. + + + uint8 + NORMAL= 0, TEST = 1 + + exp_resp_dram_tm + + + + ATTR_MSS_EXP_RESP_DRAM_DLL_RESET + TARGET_TYPE_MEM_PORT + + DLL Reset from DDR4 DRAM Spec + This is for DDR4 MRS0. + From user_response_mrs_msdg_t in draminit. + + + uint8 + NO = 0, YES = 1 + + exp_resp_dram_dll_reset + + + + ATTR_MSS_EXP_RESP_DRAM_BURST_LENGTH + TARGET_TYPE_MEM_PORT + + DLL Reset from DDR4 DRAM Spec + This is for DDR4 MRS0. + From user_response_mrs_msdg_t in draminit. + + + uint8 + FIXED8 = 0, ON_THE_FLY = 1, BC4 = 2, RESERVED = 3 + + exp_resp_dram_burst_length + + + + ATTR_MSS_EXP_RESP_DRAM_DLL_ENABLE + TARGET_TYPE_MEM_PORT + + DLL Enable from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + ENABLE = 1, DISABLE = 0 + + exp_resp_dram_dll_enable + + + + ATTR_MSS_EXP_RESP_DRAM_ODIC + TARGET_TYPE_MEM_PORT + + DRAM output driver impedance control from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + RZQ5 = 1, RZQ7 = 0 + + 2 4 + exp_resp_dram_odic + + + + ATTR_MSS_EXP_RESP_DRAM_AL + TARGET_TYPE_MEM_PORT + + Additive Latency from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, CL_MINUS_1 = 1, CL_MINUS_2 = 2 + + exp_resp_dram_al + + + + ATTR_MSS_EXP_RESP_DRAM_WR_LVL_ENABLE + TARGET_TYPE_MEM_PORT + + Write Level Enable from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_dram_wr_lvl_enable + + + + ATTR_MSS_EXP_RESP_DRAM_RTT_NOM + TARGET_TYPE_MEM_PORT + + RTT_NOM value read to be programmed from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + + 2 4 + exp_resp_dram_rtt_nom + + + + ATTR_MSS_EXP_RESP_DRAM_RTT_PARK + TARGET_TYPE_MEM_PORT + + RTT_PARK value read to be programmed from DDR4 DRAM Spec + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + + 2 4 + exp_resp_dram_rtt_park + + + + ATTR_MSS_EXP_RESP_DRAM_TDQS + TARGET_TYPE_MEM_PORT + + TDQS from DDR4 DRAM Spec + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_dram_tdqs + + + + ATTR_MSS_EXP_RESP_DRAM_OUTPUT_BUFFER + TARGET_TYPE_MEM_PORT + + DRAM Qoff from DDR4 DRAM Spec + Enables or disables DRAM output. + This is for DDR4 MRS1. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 1, ENABLE = 0 + + exp_resp_dram_output_buffer + + + + ATTR_MSS_EXP_RESP_DRAM_LPASR + TARGET_TYPE_MEM_PORT + + Low Power Auto Self-Refresh from DDR4 DRAM Spec + This is for DDR4 MRS2. + From user_response_mrs_msdg_t in draminit. + + + uint8 + MANUAL_NORMAL =0, MANUAL_REDUCED = 1, MANUAL_EXTENDED = 2, ASR = 3 + + exp_resp_dram_lpasr + + + + ATTR_MSS_EXP_RESP_DRAM_RTT_WR + TARGET_TYPE_MEM_PORT + + RTT_WR value from DDR4 DRAM Spec + This is for DDR4 MRS2. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DYNAMIC_ODT_OFF = 0, RZQ2 = 1, RZQ1 = 2, HIZ = 3, RZQ3 = 4 + 2 4 + + exp_resp_dram_rtt_wr + + + + ATTR_MSS_EXP_RESP_MPR_PAGE + TARGET_TYPE_MEM_PORT + + MPR Page Selection from DDR4 DRAM Spec. + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + PG0 = 0, PG1 = 1, PG2 = 2, PG3 = 3 + + exp_resp_mpr_page + + + + ATTR_MSS_EXP_RESP_MPR_MODE + TARGET_TYPE_MEM_PORT + + Multi Purpose Register Mode from DDR4 DRAM Spec + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_mpr_mode + + + + ATTR_MSS_EXP_RESP_GEARDOWN_MODE + TARGET_TYPE_MEM_PORT + + Gear Down Mode from DDR4 DRAM Spec. + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + HALF =0, QUARTER=1 + + exp_resp_geardown_mode + + + + ATTR_MSS_EXP_RESP_PER_DRAM_ACCESS + TARGET_TYPE_MEM_PORT + + Per DRAM accessibility from DDR4 DRAM Spec + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_per_dram_access + + + + ATTR_MSS_EXP_RESP_TEMP_READOUT + TARGET_TYPE_MEM_PORT + + Temperature sensor readout from DDR4 DRAM Spec. + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_temp_readout + + + + ATTR_MSS_EXP_RESP_CRC_WR_LATENCY + TARGET_TYPE_MEM_PORT + + Write latency for CRC and DM from DDR4 DRAM Spec. + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + 4NCK = 4, 5NCK = 5, 6NCK = 6 + + exp_resp_crc_wr_latency + + + + ATTR_MSS_EXP_RESP_MPR_RD_FORMAT + TARGET_TYPE_MEM_PORT + + MPR READ FORMAT from DDR4 DRAM Spec. + This is for DDR4 MRS3. + From user_response_mrs_msdg_t in draminit. + + + uint8 + SERIAL = 0, PARALLEL = 1, STAGGERED = 2 + + exp_resp_mpr_rd_format + + + + ATTR_MSS_EXP_RESP_MAX_POWERDOWN_MODE + TARGET_TYPE_MEM_PORT + + Max Power down mode from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_max_powerdown_mode + + + + ATTR_MSS_EXP_RESP_INTERNAL_VREF_MONITOR + TARGET_TYPE_MEM_PORT + + Internal Vref Monitor from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_internal_vref_monitor + + + + ATTR_MSS_EXP_RESP_SELF_REF_ABORT + TARGET_TYPE_MEM_PORT + + Self Refresh Abort from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_self_ref_abort + + + + ATTR_MSS_EXP_RESP_RD_PREAMBLE_TRAIN + TARGET_TYPE_MEM_PORT + + Read Pre amble Training Mode from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_rd_preamble_train + + + + ATTR_MSS_EXP_RESP_RD_PREAMBLE + TARGET_TYPE_MEM_PORT + + Read Pre amble Mode from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + 1NCLK = 0, 2NCLK = 1 + + exp_resp_rd_preamble + + + + ATTR_MSS_EXP_RESP_WR_PREAMBLE + TARGET_TYPE_MEM_PORT + + Write Pre amble Mode from DDR4 DRAM Spec. + This is for DDR4 MRS4. + From user_response_mrs_msdg_t in draminit. + + + uint8 + 1NCLK = 0, 2NCLK = 1 + + exp_resp_wr_preamble + + + + ATTR_MSS_EXP_RESP_CRC_ERROR_CLEAR + TARGET_TYPE_MEM_PORT + + CRC Error Clear from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + CLEAR = 0, ERROR = 1 + + exp_resp_crc_error_clear + + + + ATTR_MSS_EXP_RESP_CA_PARITY_ERROR_STATUS + TARGET_TYPE_MEM_PORT + + C/A Parity Error Status from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + CLEAR = 0, ERROR = 1 + + exp_resp_ca_parity_error_status + + + + ATTR_MSS_EXP_RESP_ODT_INPUT_BUFF + TARGET_TYPE_MEM_PORT + + ODT Input Buffer during power down from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + ACTIVATED = 0, DEACTIVATED = 1 + + exp_resp_odt_input_buff + + + + ATTR_MSS_EXP_RESP_CA_PARITY + TARGET_TYPE_MEM_PORT + + CA Parity Persistance Error from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_ca_parity + + + + ATTR_MSS_EXP_RESP_DATA_MASK + TARGET_TYPE_MEM_PORT + + Data Mask from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_data_mask + + + + ATTR_MSS_EXP_RESP_WRITE_DBI + TARGET_TYPE_MEM_PORT + + Write DBI from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_write_dbi + + + + ATTR_MSS_EXP_RESP_READ_DBI + TARGET_TYPE_MEM_PORT + + Read DBI from DDR4 DRAM Spec. + This is for DDR4 MRS5. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + exp_resp_read_dbi + + + + ATTR_MSS_EXP_RESP_VREF_DQ_TRAIN_VALUE + TARGET_TYPE_MEM_PORT + + VrefDQ Training Value from DDR4 DRAM Spec. + This is for DDR4 MRS6. + From user_response_mrs_msdg_t in draminit. + + + uint8 + + 2 4 20 + exp_resp_vref_dq_train_value + + + + ATTR_MSS_EXP_RESP_VREF_DQ_TRAIN_RANGE + TARGET_TYPE_MEM_PORT + + VrefDQ Training Range from DDR4 DRAM Spec. + This is for DDR4 MRS6. + From user_response_mrs_msdg_t in draminit. + + + uint8 + RANGE1 = 0, RANGE2 = 1 + + 2 4 20 + exp_resp_vref_dq_train_range + + + + ATTR_MSS_EXP_RESP_VREF_DQ_TRAIN_ENABLE + TARGET_TYPE_MEM_PORT + + VrefDQ Training Value from DDR4 DRAM Spec. + This is for DDR4 MRS6. + From user_response_mrs_msdg_t in draminit. + + + uint8 + DISABLE = 0, ENABLE = 1 + + 2 4 20 + exp_resp_vref_dq_train_enable + + diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index a1d5340aa40..327ab581840 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -64,7 +64,7 @@ namespace ddr4 /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target& i_target, - const mrs06_data& i_mrs06, + const mrs06_data& i_mrs06, const uint64_t i_rank, std::vector< ccs::instruction_t >& io_inst) { @@ -180,7 +180,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target& io_inst) { // Check to make sure our ctor worked ok - mrs06_data l_mrs06( i_target, fapi2::current_err ); + mrs06_data l_mrs06( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS06 data from attributes", mss::c_str(i_target)); // Setup training range if the value is not the default diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index 759757fc0c5..04227d20416 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -67,7 +67,7 @@ enum wr_vref_override : uint8_t /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target& i_target, - const mrs06_data& i_mrs06, + const mrs06_data& i_mrs06, const uint64_t i_rank, std::vector< ccs::instruction_t >& io_inst); @@ -90,7 +90,7 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target& io_mrs06) { // Sets up the MR information for(uint64_t i = 0; i < MAX_RANK_PER_DIMM; ++i) @@ -103,7 +103,7 @@ inline void enable_vref_train_enable(mrs06_data& io_mrs06) /// @brief disables VREF train enable in an MRS06 class /// @param[in,out] io_mrs06 /// -inline void disable_vref_train_enable(mrs06_data& io_mrs06) +inline void disable_vref_train_enable(mrs06_data& io_mrs06) { // Sets up the MR information for(uint64_t i = 0; i < MAX_RANK_PER_DIMM; ++i) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00_nimbus.C index c4f8a33f5f0..5c26a023382 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00_nimbus.C @@ -24,10 +24,10 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs00.C +/// @file mrs00_nimbus.C /// @brief Run and manage the DDR4 MRS00 loading /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -39,14 +39,11 @@ #include #include #include -#include #include -#include - +#include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -62,7 +59,9 @@ namespace ddr4 /// @note Burst Length will always be set to fixed x8 (0) /// @note Burst Chop (x4) is not supported /// -mrs00_data::mrs00_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs00_data::mrs00_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_burst_length(0), iv_read_burst_type(fapi2::ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL), iv_dll_reset(fapi2::ENUM_ATTR_EFF_DRAM_DLL_RESET_NO), @@ -89,196 +88,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs00 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs00(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs00_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS00 data from attributes", mss::c_str(i_target) ); - FAPI_TRY( mrs00(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs00, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs00_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs00(const fapi2::Target& i_target, - const mrs00_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - // Map from Write Recovery attribute value to bits in the MRS. - // Bit 4 is A13, bits 5:7 are A11:A9 - constexpr uint64_t LOWEST_WR = 10; - constexpr uint64_t WR_COUNT = 17; - constexpr uint8_t wr_map[WR_COUNT] = - { - // 10 12 14 16 18 20 22 24 26 - 0b0000, 0, 0b0001, 0, 0b0010, 0, 0b0011, 0, 0b0100, 0, 0b0101, 0, 0b0111, 0, 0b0110, 0, 0b1000 - }; - - // Map from the CAS Latency attribute to the bits in the MRS - constexpr uint64_t LOWEST_CL = 9; - constexpr uint64_t CL_COUNT = 25; - constexpr uint8_t cl_map[CL_COUNT] = - { - // 9 10 11 12 13 14 15 16 - 0b00000, 0b00001, 0b00010, 0b00011, 0b00100, 0b00101, 0b00110, 0b00111, - // 17, 18 19 20 21 22 23 24 - 0b01101, 0b01000, 0b01110, 0b01001, 0b01111, 0b01010, 0b01100, 0b01011, - // 25 26 27 28 29 30 31 32 33 - 0b10000, 0b10001, 0b10010, 0b10011, 0b10100, 0b10101, 0b10110, 0b10111, 0b11000 - }; - - fapi2::buffer l_cl; - fapi2::buffer l_wr; - - FAPI_ASSERT((i_data.iv_write_recovery >= LOWEST_WR) && (i_data.iv_write_recovery < (LOWEST_WR + WR_COUNT)), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(0) - .set_PARAMETER(WRITE_RECOVERY) - .set_PARAMETER_VALUE(i_data.iv_write_recovery) - .set_DIMM_IN_ERROR(i_target), - "Bad value for Write Recovery: %d (%s)", - i_data.iv_write_recovery, - mss::c_str(i_target)); - - FAPI_ASSERT((i_data.iv_cas_latency >= LOWEST_CL) && (i_data.iv_cas_latency < (LOWEST_CL + CL_COUNT)), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(0) - .set_PARAMETER(CAS_LATENCY) - .set_PARAMETER_VALUE(i_data.iv_cas_latency) - .set_DIMM_IN_ERROR(i_target), - "Bad value for CAS Latency: %d (%s)", - i_data.iv_cas_latency, - mss::c_str(i_target)); - - io_inst.arr0.insertFromRight(i_data.iv_burst_length); - io_inst.arr0.writeBit(i_data.iv_read_burst_type); - io_inst.arr0.writeBit(i_data.iv_test_mode); - io_inst.arr0.writeBit(i_data.iv_dll_reset); - - // CAS Latency takes a little effort - the bits aren't contiguous - l_cl = cl_map[i_data.iv_cas_latency - LOWEST_CL]; - io_inst.arr0.writeBit(l_cl.getBit<3>()); - io_inst.arr0.writeBit(l_cl.getBit<4>()); - io_inst.arr0.writeBit(l_cl.getBit<5>()); - io_inst.arr0.writeBit(l_cl.getBit<6>()); - io_inst.arr0.writeBit(l_cl.getBit<7>()); - - // Write Recovery/Read to Precharge is not contiguous either. - l_wr = wr_map[i_data.iv_write_recovery - LOWEST_WR]; - io_inst.arr0.writeBit(l_wr.getBit<4>()); - io_inst.arr0.writeBit(l_wr.getBit<5>()); - io_inst.arr0.writeBit(l_wr.getBit<6>()); - io_inst.arr0.writeBit(l_wr.getBit<7>()); - - FAPI_INF("%s MR0: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs00_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @param[out] o_burst_length the burst length -/// @param[out] o_read_burst_type the burst type -/// @param[out] o_dll_reset the dll reset bit -/// @param[out] o_test_mode the test mode bit -/// @param[out] o_wr_index the write index -/// @param[out] o_cas_latency the cas latency -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_burst_length, - uint8_t& o_read_burst_type, - uint8_t& o_dll_reset, - uint8_t& o_test_mode, - fapi2::buffer& o_wr_index, - fapi2::buffer& o_cas_latency) -{ - using TT = ccsTraits; - - static const uint8_t wr_map[9] = { 10, 12, 14, 16, 18, 20, 24, 22, 26 }; - - o_wr_index = 0; - o_cas_latency = 0; - - i_inst.arr0.extractToRight(o_burst_length); - o_read_burst_type = i_inst.arr0.getBit(); - o_test_mode = i_inst.arr0.getBit(); - o_dll_reset = i_inst.arr0.getBit(); - - // CAS Latency takes a little effort - the bits aren't contiguous - o_cas_latency.writeBit<3>(i_inst.arr0.getBit()); - o_cas_latency.writeBit<4>(i_inst.arr0.getBit()); - o_cas_latency.writeBit<5>(i_inst.arr0.getBit()); - o_cas_latency.writeBit<6>(i_inst.arr0.getBit()); - o_cas_latency.writeBit<7>(i_inst.arr0.getBit()); - - // Write Recovery/Read to Precharge is not contiguous either. - o_wr_index.writeBit<4>(i_inst.arr0.getBit()); - o_wr_index.writeBit<5>(i_inst.arr0.getBit()); - o_wr_index.writeBit<6>(i_inst.arr0.getBit()); - o_wr_index.writeBit<7>(i_inst.arr0.getBit()); - - FAPI_INF("MR0 Decode BL: 0x%x, RBT: 0x%x, CL: 0x%x, TM: 0x%x, DLL_RESET: 0x%x, WR: (0x%x)0x%x", - o_burst_length, o_read_burst_type, uint8_t(o_cas_latency), o_test_mode, o_dll_reset, - wr_map[uint8_t(o_wr_index)], uint8_t(o_wr_index)); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS0, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - uint8_t l_burst_length = 0; - uint8_t l_read_burst_type = 0; - uint8_t l_dll_reset = 0; - uint8_t l_test_mode = 0; - fapi2::buffer l_wr_index; - fapi2::buffer l_cas_latency; - - return mrs00_decode_helper(i_inst, i_rank, l_burst_length, l_read_burst_type, l_dll_reset, l_test_mode, - l_wr_index, l_cas_latency); -} - -fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs00_data& i_data, +template<> +fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs00_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs00; -fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs00_decode; +template<> +fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs00_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01_nimbus.C index 94f51cce72b..ffff42b23f9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01_nimbus.C @@ -24,29 +24,26 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs01.C +/// @file mrs01_nimbus.C /// @brief Run and manage the DDR4 MRS01 loading /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#include - #include #include #include #include -#include +#include #include -#include - +#include +#include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -56,127 +53,37 @@ namespace ddr4 { /// -/// @brief mrs01_data ctor -/// @param[in] a fapi2::TARGET_TYPE_DIMM target -/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -mrs01_data::mrs01_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): - iv_dll_enable(fapi2::ENUM_ATTR_EFF_DRAM_DLL_ENABLE_YES), - iv_additive_latency(0), - iv_wl_enable(0), - iv_tdqs(0), - iv_qoff(0) -{ - FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_odic(i_target, &(iv_odic[0])), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_tdqs(i_target, iv_tdqs), "Error in mrs01_data()" ); - FAPI_TRY( mss::eff_dram_output_buffer(i_target, iv_qoff), "Error in mrs01_data()" ); - - o_rc = fapi2::FAPI2_RC_SUCCESS; - return; - -fapi_try_exit: - o_rc = fapi2::current_err; - FAPI_ERR("%s unable to get attributes for mrs01"); - return; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs01 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs01(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs01_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS01 data from attributes", mss::c_str(i_target) ); - FAPI_TRY( mrs01(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs01, data object as input +/// @brief Helper function to decode ODIC to the MRS value - nimbus specialization /// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs01_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question +/// @param[in] i_odic_value the value to be decoded for ODIC +/// @param[out] o_odic_decode the MRS decoded value for ODIC /// @return FAPI2_RC_SUCCESS iff OK /// -fapi2::ReturnCode mrs01(const fapi2::Target& i_target, - const mrs01_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) +template<> +fapi2::ReturnCode odic_helper(const fapi2::Target& i_target, + const uint8_t i_odic_value, + fapi2::buffer& o_odic_decode) { - using TT = ccsTraits; - // Little table to map Output Driver Imepdance Control. 34Ohm is index 0, // 48Ohm is index 1 // Left bit is A2, right bit is A1 constexpr uint8_t odic_map[] = { 0b00, 0b01 }; - constexpr uint64_t ODIC_LENGTH = 2; - constexpr uint64_t ODIC_START_BIT = 7; - constexpr uint64_t ADDITIVE_LATENCE_LENGTH = 2; - constexpr uint64_t ADDITIVE_LATENCE_START_BIT = 7; - constexpr uint64_t RTT_NOM_LENGTH = 3; - constexpr uint64_t RTT_NOM_START_BIT = 7; - - - fapi2::buffer l_additive_latency; - fapi2::buffer l_odic_buffer; - fapi2::buffer l_rtt_nom_buffer; - - //check here to make sure the rank indexes correctly into the attribute array - //It's equivalent to mss::index(i_rank) < l_rtt_nom.size() if C arrays had a .size() method - fapi2::Assert( mss::index(i_rank) < MAX_RANK_PER_DIMM); - - FAPI_ASSERT( ((i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) || - (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM48)), + FAPI_ASSERT( ((i_odic_value == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) || + (i_odic_value == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM48)), fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(1) .set_PARAMETER(OUTPUT_IMPEDANCE) - .set_PARAMETER_VALUE(i_data.iv_odic[mss::index(i_rank)]) + .set_PARAMETER_VALUE(i_odic_value) .set_DIMM_IN_ERROR(i_target), "Bad value for output driver impedance: %d (%s)", - i_data.iv_odic[mss::index(i_rank)], + i_odic_value, mss::c_str(i_target)); // Map from impedance to bits in MRS1 - l_odic_buffer = (i_data.iv_odic[mss::index(i_rank)] == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ? + o_odic_decode = (i_odic_value == fapi2::ENUM_ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS_OHM34) ? odic_map[0] : odic_map[1]; - // Map from RTT_NOM array to the value in the map - l_rtt_nom_buffer = i_data.iv_rtt_nom[mss::index(i_rank)]; - - // Print this here as opposed to the MRS01 ctor as we want to see the specific rtt now information - FAPI_INF("%s MR1 rank %d attributes: DLL_ENABLE: 0x%x, ODIC: 0x%x(0x%x), AL: 0x%x, WLE: 0x%x, " - "RTT_NOM:0x%x, TDQS: 0x%x, QOFF: 0x%x", - mss::c_str(i_target), i_rank, i_data.iv_dll_enable, - i_data.iv_odic[mss::index(i_rank)], uint8_t(l_odic_buffer), - uint8_t(l_additive_latency), i_data.iv_wl_enable, - uint8_t(l_rtt_nom_buffer), i_data.iv_tdqs, i_data.iv_qoff); - - io_inst.arr0.writeBit(i_data.iv_dll_enable); - mss::swizzle(l_odic_buffer, io_inst.arr0); - mss::swizzle(fapi2::buffer - (i_data.iv_additive_latency), io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_wl_enable); - mss::swizzle(l_rtt_nom_buffer, io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_tdqs); - io_inst.arr0.writeBit(i_data.iv_qoff); - - FAPI_INF("%s MR1: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: @@ -184,80 +91,46 @@ fapi_try_exit: } /// -/// @brief Helper function for mrs01_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @param[out] o_dll_enable the dll enable bit -/// @param[out] o_wrl_enable the write leveling enable bit -/// @param[out] o_tdqs the tdqs enable bit -/// @param[out] o_qoff the qoff bit -/// @param[out] o_odic the output driver impedance control setting -/// @param[out] o_additive_latency the additive latency setting -/// @param[out] o_rtt_nom the rtt_nom setting -/// @return FAPI2_RC_SUCCESS iff ok +/// @brief mrs01_data ctor +/// @param[in] a fapi2::TARGET_TYPE_DIMM target +/// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_dll_enable, - uint8_t& o_wrl_enable, - uint8_t& o_tdqs, - uint8_t& o_qoff, - fapi2::buffer& o_odic, - fapi2::buffer& o_additive_latency, - fapi2::buffer& o_rtt_nom) +template<> +mrs01_data::mrs01_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): + iv_dll_enable(fapi2::ENUM_ATTR_EFF_DRAM_DLL_ENABLE_YES), + iv_additive_latency(0), + iv_wl_enable(0), + iv_tdqs(0), + iv_qoff(0) { - using TT = ccsTraits; - - o_odic = 0; - o_additive_latency = 0; - o_rtt_nom = 0; - - o_dll_enable = i_inst.arr0.getBit(); - o_wrl_enable = i_inst.arr0.getBit(); - o_tdqs = i_inst.arr0.getBit(); - o_qoff = i_inst.arr0.getBit(); - - mss::swizzle<6, 2, TT::A2>(i_inst.arr0, o_odic); - mss::swizzle<6, 2, TT::A4>(i_inst.arr0, o_additive_latency); - mss::swizzle<5, 3, TT::A10>(i_inst.arr0, o_rtt_nom); - - FAPI_INF("MR1 rank %d decode: DLL_ENABLE: 0x%x, ODIC: 0x%x, AL: 0x%x, WLE: 0x%x, " - "RTT_NOM: 0x%x, TDQS: 0x%x, QOFF: 0x%x", - i_rank, o_dll_enable, uint8_t(o_odic), uint8_t(o_additive_latency), - o_wrl_enable, uint8_t(o_rtt_nom), o_tdqs, o_qoff); - - return FAPI2_RC_SUCCESS; -} + FAPI_TRY( mss::eff_dram_dll_enable(i_target, iv_dll_enable), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_odic(i_target, &(iv_odic[0])), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_al(i_target, iv_additive_latency), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_wr_lvl_enable(i_target, iv_wl_enable), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_rtt_nom(i_target, &(iv_rtt_nom[0])), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_tdqs(i_target, iv_tdqs), "Error in mrs01_data()" ); + FAPI_TRY( mss::eff_dram_output_buffer(i_target, iv_qoff), "Error in mrs01_data()" ); -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS1, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - uint8_t l_dll_enable = 0; - uint8_t l_wrl_enable = 0; - uint8_t l_tdqs = 0; - uint8_t l_qoff = 0; - fapi2::buffer l_odic; - fapi2::buffer l_additive_latency; - fapi2::buffer l_rtt_nom; + o_rc = fapi2::FAPI2_RC_SUCCESS; + return; - return mrs01_decode_helper(i_inst, i_rank, l_dll_enable, l_wrl_enable, l_tdqs, l_qoff, l_odic, - l_additive_latency, l_rtt_nom); +fapi_try_exit: + o_rc = fapi2::current_err; + FAPI_ERR("%s unable to get attributes for mrs01"); + return; } -fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs01_data& i_data, +template<> +fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs01_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs01; -fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs01_decode; +template<> +fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs01_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02_nimbus.C index 36491e63808..b0b056b48ec 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02_nimbus.C @@ -24,10 +24,10 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs02.C +/// @file mrs02_nimbus.C /// @brief Run and manage the DDR4 MRS02 loading /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -38,11 +38,12 @@ #include #include #include +#include +#include #include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -56,7 +57,9 @@ namespace ddr4 /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -mrs02_data::mrs02_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs02_data::mrs02_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_lpasr(0), iv_cwl(0), iv_write_crc(0) @@ -75,154 +78,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs02 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs02(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs02_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, - "%s Unable to construct MRS02 data from attributes", - mss::c_str(i_target) ); - FAPI_TRY( mrs02(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs02, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs02_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs02(const fapi2::Target& i_target, - const mrs02_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - constexpr uint64_t CWL_LENGTH = 3; - constexpr uint64_t CWL_START = 7; - constexpr uint64_t LPASR_LENGTH = 2; - constexpr uint64_t LPASR_START = 7; - constexpr uint64_t RTT_WR_LENGTH = 3; - constexpr uint64_t RTT_WR_START = 7; - - // Index this by subtracting 9 from the CWL attribute value. The table maps CWL attribute value - // (in clks) to the bit setting in MR2. See the table in the JEDEC spec for the mapping. - constexpr uint64_t LOWEST_CWL = 9; - constexpr uint64_t CWL_COUNT = 12; - // 9 10 11 12 14 16 18 20 - constexpr uint8_t cwl_map[CWL_COUNT] = { 0b000, 0b001, 0b010, 0b011, 0, 0b100, 0, 0b101, 0, 0b110, 0, 0b111 }; - - fapi2::buffer l_cwl_buffer; - - fapi2::Assert(mss::index(i_rank) < MAX_RANK_PER_DIMM); - - fapi2::buffer l_rtt_wr_buffer = i_data.iv_dram_rtt_wr[mss::index(i_rank)]; - - FAPI_ASSERT((i_data.iv_cwl >= LOWEST_CWL) && (i_data.iv_cwl < (LOWEST_CWL + CWL_COUNT)), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(0) - .set_PARAMETER(CAS_WRITE_LATENCY) - .set_PARAMETER_VALUE(i_data.iv_cwl) - .set_DIMM_IN_ERROR(i_target), - "Bad value for CWL: %d (%s)", i_data.iv_cwl, mss::c_str(i_target)); - - l_cwl_buffer = cwl_map[i_data.iv_cwl - LOWEST_CWL]; - - - // Printed here as opposed to the ctor as it uses the rank information - FAPI_INF("%s MR2 rank %d attributes: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x(0x%x), WRITE_CRC: 0x%x", - mss::c_str(i_target), i_rank, uint8_t(i_data.iv_lpasr), i_data.iv_cwl, - uint8_t(l_cwl_buffer), uint8_t(l_rtt_wr_buffer), i_data.iv_write_crc); - - mss::swizzle(l_cwl_buffer, io_inst.arr0); - - mss::swizzle(fapi2::buffer(i_data.iv_lpasr), io_inst.arr0); - - mss::swizzle(l_rtt_wr_buffer, io_inst.arr0); - - io_inst.arr0.writeBit(i_data.iv_write_crc); - - FAPI_INF("MR2: 0x%016llx", uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs02_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_write_crc the write crc bit -/// @param[out] o_lpasr the low power array self refresh setting -/// @param[out] o_cwl the cas write latency setting -/// @param[out] o_rtt_wr the rtt_wr setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_write_crc, - fapi2::buffer& o_lpasr, - fapi2::buffer& o_cwl, - fapi2::buffer& o_rtt_wr) -{ - using TT = ccsTraits; - - o_lpasr = 0; - o_cwl = 0; - o_rtt_wr = 0; - - o_write_crc = i_inst.arr0.getBit(); - mss::swizzle<5, 3, TT::A5>(i_inst.arr0, o_cwl); - mss::swizzle<6, 2, TT::A7>(i_inst.arr0, o_lpasr); - mss::swizzle<5, 3, TT::A11>(i_inst.arr0, o_rtt_wr); - - FAPI_INF("MR2 rank %d deocode: LPASR: 0x%x, CWL: 0x%x, RTT_WR: 0x%x, WRITE_CRC: 0x%x", - i_rank, uint8_t(o_lpasr), uint8_t(o_cwl), uint8_t(o_rtt_wr), o_write_crc); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS2, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - uint8_t l_write_crc = 0; - fapi2::buffer l_lpasr; - fapi2::buffer l_cwl; - fapi2::buffer l_rtt_wr; - - return mrs02_decode_helper(i_inst, i_rank, l_write_crc, l_lpasr, l_cwl, l_rtt_wr); -} - -fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs02_data& i_data, +template<> +fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs02_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs02; -fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs02_decode; +template<> +fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs02_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03_nimbus.C index 26a28dc27fb..91db853409b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03_nimbus.C @@ -24,10 +24,10 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs03.C +/// @file mrs03_nimbus.C /// @brief Run and manage mrs03 /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Mattew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -38,11 +38,12 @@ #include #include #include +#include +#include #include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -50,24 +51,53 @@ namespace mss namespace ddr4 { -enum swizzle : uint64_t + +/// +/// @brief Helper function to decode CRC WR latency to the MRS value - nimbus specialization +/// @param[in] i_target a fapi2::Target +/// @param[in] i_value the value to be decoded +/// @param[out] o_decode the MRS decoded value +/// @return FAPI2_RC_SUCCESS iff OK +/// +template<> +fapi2::ReturnCode crc_wr_latency_helper(const fapi2::Target& i_target, + const uint8_t i_value, + fapi2::buffer& o_decode) { - MPR_PAGE_LENGTH = 2, - MPR_PAGE_START = 7, - FINE_REFRESH_LENGTH = 3, - FINE_REFRESH_START = 7, - CRC_WR_LATENCY_LENGTH = 2, - CRC_WR_LATENCY_START = 7, - READ_FORMAT_LENGTH = 2, - READ_FORMAT_START = 7, -}; + constexpr uint64_t WL_COUNT = 3; + constexpr uint64_t LOWEST_WL = 4; + // 4 5 6 + constexpr uint8_t crc_wr_latency_map[WL_COUNT] = { 0, 1, 2 }; + + fapi2::buffer l_crc_wr_latency_buffer; + + FAPI_ASSERT((i_value >= LOWEST_WL) && + (i_value < (LOWEST_WL + WL_COUNT)), + fapi2::MSS_BAD_MR_PARAMETER() + .set_MR_NUMBER(3) + .set_PARAMETER(WRITE_CMD_LATENCY) + .set_PARAMETER_VALUE(i_value) + .set_DIMM_IN_ERROR(i_target), + "Bad value for Write CMD Latency: %d (%s)", + i_value, + mss::c_str(i_target)); + + o_decode = crc_wr_latency_map[i_value - LOWEST_WL]; + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief mrs03_data ctor /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -mrs03_data::mrs03_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs03_data::mrs03_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_mpr_mode(fapi2::ENUM_ATTR_EFF_MPR_MODE_DISABLE), iv_mpr_page(fapi2::ENUM_ATTR_EFF_MPR_PAGE_PG0), iv_geardown(0), @@ -100,164 +130,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs03 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs03(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs03_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, - "%s Unable to construct MRS03 data from attributes", - mss::c_str(i_target) ); - FAPI_TRY( mrs03(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs03, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs00_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs03(const fapi2::Target& i_target, - const mrs03_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - //Some consts for the swizzle action - constexpr uint64_t LOWEST_WL = 4; - constexpr uint64_t WL_COUNT = 3; - // 4 5 6 - constexpr uint8_t crc_wr_latency_map[WL_COUNT] = { 0, 1, 2 }; - - fapi2::buffer l_crc_wr_latency_buffer; - - FAPI_ASSERT((i_data.iv_crc_wr_latency >= LOWEST_WL) && - (i_data.iv_crc_wr_latency < (LOWEST_WL + WL_COUNT)), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(3) - .set_PARAMETER(WRITE_CMD_LATENCY) - .set_PARAMETER_VALUE(i_data.iv_crc_wr_latency) - .set_DIMM_IN_ERROR(i_target), - "Bad value for Write CMD Latency: %d (%s)", - i_data.iv_crc_wr_latency, - mss::c_str(i_target)); - - l_crc_wr_latency_buffer = crc_wr_latency_map[i_data.iv_crc_wr_latency - LOWEST_WL]; - - mss::swizzle(fapi2::buffer(i_data.iv_mpr_page), io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_mpr_mode); - io_inst.arr0.writeBit(i_data.iv_geardown); - io_inst.arr0.writeBit(i_data.iv_pda); - io_inst.arr0.writeBit(i_data.iv_temp_readout); - - mss::swizzle(fapi2::buffer(i_data.iv_fine_refresh), - io_inst.arr0); - mss::swizzle(l_crc_wr_latency_buffer, io_inst.arr0); - mss::swizzle(fapi2::buffer(i_data.iv_read_format), - io_inst.arr0); - - FAPI_INF("%s MR3: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs03_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_mpr_mode the mpr operation setting -/// @param[out] o_geardown the geardown mode setting -/// @param[out] o_pda the per dram addressability setting -/// @param[out] o_temp_readout the temperature sensor readout setting -/// @param[out] o_mpr_page the mpr page selection -/// @param[out] o_fine_refresh the fine granularity refresh mode setting -/// @param[out] o_crc_wr_latency_buffer the write cmd latency when crc and dm are enabled -/// @param[out] o_read_fromat the mpr read format setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_mpr_mode, - uint8_t& o_geardown, - uint8_t& o_pda, - uint8_t& o_temp_readout, - fapi2::buffer& o_mpr_page, - fapi2::buffer& o_fine_refresh, - fapi2::buffer& o_crc_wr_latency_buffer, - fapi2::buffer& o_read_format) -{ - using TT = ccsTraits; - - o_mpr_page = 0; - o_fine_refresh = 0; - o_crc_wr_latency_buffer = 0; - o_read_format = 0; - - o_mpr_mode = i_inst.arr0.getBit(); - o_geardown = i_inst.arr0.getBit(); - o_pda = i_inst.arr0.getBit(); - o_temp_readout = i_inst.arr0.getBit(); - - mss::swizzle<6, 2, TT::A1>(i_inst.arr0, o_mpr_page); - mss::swizzle<5, 3, TT::A8>(i_inst.arr0, o_fine_refresh); - mss::swizzle<6, 2, TT::A10>(i_inst.arr0, o_crc_wr_latency_buffer); - mss::swizzle<6, 2, TT::A12>(i_inst.arr0, o_read_format); - - FAPI_INF("MR3 rank %d decode: MPR_MODE: 0x%x, MPR_PAGE: 0x%x, GD: 0x%x, PDA: 0x%x, " - "TEMP: 0x%x FR: 0x%x, CRC_WL: 0x%x, RF: 0x%x", i_rank, - uint8_t(o_mpr_mode), o_mpr_page, o_geardown, o_pda, uint8_t(o_temp_readout), - uint8_t(o_fine_refresh), uint8_t(o_crc_wr_latency_buffer), uint8_t(o_read_format)); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS3, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - uint8_t l_mpr_mode = 0; - uint8_t l_geardown = 0; - uint8_t l_pda = 0; - uint8_t l_temp_readout = 0; - fapi2::buffer l_mpr_page; - fapi2::buffer l_fine_refresh; - fapi2::buffer l_crc_wr_latency_buffer; - fapi2::buffer l_read_format; - - return mrs03_decode_helper(i_inst, i_rank, l_mpr_mode, l_geardown, l_pda, l_temp_readout, - l_mpr_page, l_fine_refresh, l_crc_wr_latency_buffer, l_read_format); -} - -fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs03_data& i_data, +template<> +fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs03_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs03; -fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs03_decode; +template<> +fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs03_decode; } // ns ddr4 } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04_nimbus.C index cc8cf4e5b9c..f0e122a4cac 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04_nimbus.C @@ -24,10 +24,10 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs04.C +/// @file mrs04_nimbus.C /// @brief Run and manage the DDR4 MRS04 loading /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -38,11 +38,14 @@ #include #include #include +#include +#include +#include +#include #include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -56,7 +59,9 @@ namespace ddr4 /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -mrs04_data::mrs04_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs04_data::mrs04_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_max_pd_mode(fapi2::ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE), iv_temp_refresh_range(fapi2::ENUM_ATTR_MSS_MRW_TEMP_REFRESH_RANGE_NORMAL), iv_temp_ref_mode(fapi2::ENUM_ATTR_MSS_MRW_TEMP_REFRESH_MODE_DISABLE), @@ -99,173 +104,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs04 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank thes rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs04(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs04_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS04 data from attributes", mss::c_str(i_target) ); - FAPI_TRY( mrs04(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs04, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs04_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs04(const fapi2::Target& i_target, - const mrs04_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - constexpr uint64_t CS_CMD_LATENCY_LENGTH = 3; - constexpr uint64_t CS_CMD_LATENCY_START = 7; - - constexpr uint64_t CS_CMD_COUNT = 9; - // 0 3 4 5 6 8 - constexpr uint8_t cs_cmd_latency_map[CS_CMD_COUNT] = { 0b000, 0, 0, 0b001, 0b010, 0b011, 0b100, 0, 0b101 }; - - fapi2::buffer l_cs_cmd_latency_buffer; - - FAPI_ASSERT( (i_data.iv_cs_cmd_latency < CS_CMD_COUNT), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(4) - .set_PARAMETER(CS_CMD_LATENCY) - .set_PARAMETER_VALUE(i_data.iv_cs_cmd_latency) - .set_DIMM_IN_ERROR(i_target), - "Bad value for CS to CMD/ADDR Latency: %d (%s)", i_data.iv_cs_cmd_latency, mss::c_str(i_target)); - - l_cs_cmd_latency_buffer = cs_cmd_latency_map[i_data.iv_cs_cmd_latency]; - - io_inst.arr0.writeBit(i_data.iv_max_pd_mode); - io_inst.arr0.writeBit(i_data.iv_temp_refresh_range); - io_inst.arr0.writeBit(i_data.iv_temp_ref_mode); - io_inst.arr0.writeBit(i_data.iv_vref_mon); - io_inst.arr0.writeBit(i_data.iv_soft_ppr); - - mss::swizzle(l_cs_cmd_latency_buffer, io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_ref_abort); - io_inst.arr0.writeBit(i_data.iv_rd_pre_train_mode); - io_inst.arr0.writeBit(i_data.iv_rd_preamble); - io_inst.arr0.writeBit(i_data.iv_wr_preamble); - io_inst.arr0.writeBit(i_data.iv_ppr); - - FAPI_INF("%s MR4: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs04_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_max_pd_mode the maximum power down mode setting -/// @param[out] o_temp_refresh_range the temperature controlled refresh range setting -/// @param[out] o_temp_ref_mode the temperature controlled refresh mode setting -/// @param[out] o_vref_mon the internal vref monitor setting -/// @param[out] o_ref_abort the self refresh abort setting -/// @param[out] o_rd_pre_train_mode the read preamble training mode setting -/// @param[out] o_rd_preamble the read preamble setting -/// @param[out] o_wr_preamble the write preamble setting -/// @param[out] o_ppr the ppr setting -/// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_max_pd_mode, - uint8_t& o_temp_refresh_range, - uint8_t& o_temp_ref_mode, - uint8_t& o_vref_mon, - uint8_t& o_ref_abort, - uint8_t& o_rd_pre_train_mode, - uint8_t& o_rd_preamble, - uint8_t& o_wr_preamble, - uint8_t& o_ppr, - uint8_t& o_soft_ppr, - fapi2::buffer& o_cs_cmd_latency_buffer) -{ - using TT = ccsTraits; - - o_max_pd_mode = i_inst.arr0.getBit(); - o_temp_refresh_range = i_inst.arr0.getBit(); - o_temp_ref_mode = i_inst.arr0.getBit(); - o_vref_mon = i_inst.arr0.getBit(); - o_soft_ppr = i_inst.arr0.getBit(); - - o_cs_cmd_latency_buffer = 0; - mss::swizzle<5, 3, TT::A8>(i_inst.arr0, o_cs_cmd_latency_buffer); - - o_ref_abort = i_inst.arr0.getBit(); - o_rd_pre_train_mode = i_inst.arr0.getBit(); - o_rd_preamble = i_inst.arr0.getBit(); - o_wr_preamble = i_inst.arr0.getBit(); - o_ppr = i_inst.arr0.getBit(); - - FAPI_INF("MR4 rank %d decode: MAX_PD: 0x%x, TEMP_REFRESH_RANGE: 0x%x, TEMP_REF_MODE: 0x%x " - "VREF_MON: 0x%x, CSL: 0x%x, REF_ABORT: 0x%x, RD_PTM: 0x%x, RD_PRE: 0x%x, " - "WR_PRE: 0x%x, PPR: 0x%x", - i_rank, o_max_pd_mode, o_temp_refresh_range, o_temp_ref_mode, - o_vref_mon, uint8_t(o_cs_cmd_latency_buffer), o_ref_abort, - o_rd_pre_train_mode, o_rd_preamble, o_wr_preamble, o_ppr); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS4, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - uint8_t l_max_pd_mode = 0; - uint8_t l_temp_refresh_range = 0; - uint8_t l_temp_ref_mode = 0; - uint8_t l_vref_mon = 0; - uint8_t l_ref_abort = 0; - uint8_t l_rd_pre_train_mode = 0; - uint8_t l_rd_preamble = 0; - uint8_t l_wr_preamble = 0; - uint8_t l_ppr = 0; - uint8_t l_soft_ppr = 0; - - fapi2::buffer l_cs_cmd_latency_buffer; - - return mrs04_decode_helper(i_inst, i_rank, l_max_pd_mode, l_temp_refresh_range, l_temp_ref_mode, - l_vref_mon, l_ref_abort, l_rd_pre_train_mode, l_rd_preamble, - l_wr_preamble, l_ppr, l_soft_ppr, l_cs_cmd_latency_buffer); -} - -fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs04_data& i_data, +template<> +fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs04_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs04; -fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs04_decode; +template<> +fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs04_decode; } // ns ddr4 } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05_nimbus.C index df632e3be07..c8d78f48dce 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05_nimbus.C @@ -24,10 +24,10 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mrs05.C +/// @file mrs05_nimbus.C /// @brief Run and manage the DDR4 MRS05 loading /// -// *HWP HWP Owner: Jacob Harvey +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -38,11 +38,12 @@ #include #include #include +#include +#include #include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -56,7 +57,9 @@ namespace ddr4 /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -mrs05_data::mrs05_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs05_data::mrs05_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_ca_parity_latency(fapi2::ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE), iv_crc_error_clear(fapi2::ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR), iv_ca_parity_error_status(fapi2::ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR), @@ -68,7 +71,8 @@ mrs05_data::mrs05_data( const fapi2::Target& i_target, { FAPI_TRY( mss::eff_ca_parity_latency(i_target, iv_ca_parity_latency), "Error in mrs05_data()" ); FAPI_TRY( mss::eff_crc_error_clear(i_target, iv_crc_error_clear), "Error in mrs05_data()" ); - FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status), "Error in mrs05_data()" ); + FAPI_TRY( mss::eff_ca_parity_error_status(i_target, iv_ca_parity_error_status), + "Error in mrs05_data()" ); FAPI_TRY( mss::eff_odt_input_buff(i_target, iv_odt_input_buffer), "Error in mrs05_data()" ); FAPI_TRY( mss::eff_dram_rtt_park(i_target, &(iv_rtt_park[0])), "Error in mrs05_data()" ); FAPI_TRY( mss::eff_ca_parity(i_target, iv_ca_parity), "Error in mrs05_data()" ); @@ -85,184 +89,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs05 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs05(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs05_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS05 data from attributes", mss::c_str(i_target) ); - FAPI_TRY( mrs05(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs05, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs05_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs05(const fapi2::Target& i_target, - const mrs05_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - constexpr uint64_t CA_PARITY_LATENCY_LENGTH = 3; - constexpr uint64_t CA_PARITY_LATENCY_START = 7; - constexpr uint64_t RTT_PARK_LENGTH = 3; - constexpr uint64_t RTT_PARK_START = 7; - - constexpr uint64_t CA_PARITY_COUNT = 9; - // 0 4 5 6 8 - constexpr uint8_t ca_parity_latency_map[CA_PARITY_COUNT] = { 0b000, 0, 0, 0, 0b001, 0b010, 0b011, 0, 0b100 }; - - fapi2::buffer l_ca_parity_latency_buffer; - - fapi2::buffer l_rtt_park_buffer = i_data.iv_rtt_park[mss::index(i_rank)]; - - //check here to make sure the rank indexes correctly into the attribute array - FAPI_ASSERT( (mss::index(i_rank) < MAX_RANK_PER_DIMM), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(5) - .set_PARAMETER(RANK) - .set_PARAMETER_VALUE(i_rank) - .set_DIMM_IN_ERROR(i_target), - "Bad value for RTT park: %d (%s)", i_rank, mss::c_str(i_target)); - - FAPI_ASSERT( (i_data.iv_ca_parity_latency < CA_PARITY_COUNT), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(5) - .set_PARAMETER(CA_PARITY_LATENCY) - .set_PARAMETER_VALUE(i_data.iv_ca_parity_latency) - .set_DIMM_IN_ERROR(i_target), - "Bad value for CA parity latency: %d (%s)", i_data.iv_ca_parity_latency, mss::c_str(i_target)); - - l_ca_parity_latency_buffer = ca_parity_latency_map[i_data.iv_ca_parity_latency]; - - FAPI_INF("%s MR5 rank %d attributes: CAPL: 0x%x(0x%x), CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x " - "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", - mss::c_str(i_target), i_rank, i_data.iv_ca_parity_latency, uint8_t(l_ca_parity_latency_buffer), - i_data.iv_crc_error_clear, i_data.iv_ca_parity_error_status, i_data.iv_odt_input_buffer, - uint8_t(l_rtt_park_buffer), i_data.iv_ca_parity, - i_data.iv_data_mask, i_data.iv_write_dbi, i_data.iv_read_dbi); - - mss::swizzle(l_ca_parity_latency_buffer, io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_crc_error_clear); - io_inst.arr0.writeBit(i_data.iv_ca_parity_error_status); - io_inst.arr0.writeBit(i_data.iv_odt_input_buffer); - mss::swizzle(l_rtt_park_buffer, io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_ca_parity); - io_inst.arr0.writeBit(i_data.iv_data_mask); - io_inst.arr0.writeBit(i_data.iv_write_dbi); - io_inst.arr0.writeBit(i_data.iv_read_dbi); - - FAPI_INF("%s MR5: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs05_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_crc_error_clear the crc error clear setting -/// @param[out] o_ca_parity_error_status the c/a parity error status -/// @param[out] o_odt_input_buffer the odt input buffer during power down mode setting -/// @param[out] o_ca_parity the c/a parity persistent error setting -/// @param[out] o_data_mask the data mask setting -/// @param[out] o_write_dbi the write dbi setting -/// @param[out] o_read_dbi the read dbi setting -/// @param[out] o_ca_parity_latency_buffer the c/a parity latency mode setting -/// @param[out] o_rtt_park_buffer the rtt_park setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_crc_error_clear, - uint8_t& o_ca_parity_error_status, - uint8_t& o_odt_input_buffer, - uint8_t& o_ca_parity, - uint8_t& o_data_mask, - uint8_t& o_write_dbi, - uint8_t& o_read_dbi, - fapi2::buffer& o_ca_parity_latency_buffer, - fapi2::buffer& o_rtt_park_buffer) -{ - using TT = ccsTraits; - - o_ca_parity_latency_buffer = 0; - o_rtt_park_buffer = 0; - - mss::swizzle<5, 3, TT::A2>(i_inst.arr0, o_ca_parity_latency_buffer); - mss::swizzle<5, 3, TT::A8>(i_inst.arr0, o_rtt_park_buffer); - - o_crc_error_clear = i_inst.arr0.getBit(); - o_ca_parity_error_status = i_inst.arr0.getBit(); - o_odt_input_buffer = i_inst.arr0.getBit(); - - o_ca_parity = i_inst.arr0.getBit(); - o_data_mask = i_inst.arr0.getBit(); - o_write_dbi = i_inst.arr0.getBit(); - o_read_dbi = i_inst.arr0.getBit(); - - FAPI_INF("MR5 rank %d decode: CAPL: 0x%x, CRC_EC: 0x%x, CA_PES: 0x%x, ODT_IB: 0x%x " - "RTT_PARK: 0x%x, CAP: 0x%x, DM: 0x%x, WDBI: 0x%x, RDBI: 0x%x", - i_rank, uint8_t(o_ca_parity_latency_buffer), o_crc_error_clear, o_ca_parity_error_status, - o_odt_input_buffer, uint8_t(o_rtt_park_buffer), o_ca_parity, o_data_mask, - o_write_dbi, o_read_dbi); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS5, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - fapi2::buffer l_ca_parity_latency_buffer; - fapi2::buffer l_rtt_park_buffer; - - uint8_t l_crc_error_clear = 0; - uint8_t l_ca_parity_error_status = 0; - uint8_t l_odt_input_buffer = 0; - uint8_t l_ca_parity = 0; - uint8_t l_data_mask = 0; - uint8_t l_write_dbi = 0; - uint8_t l_read_dbi = 0; - - return mrs05_decode_helper(i_inst, i_rank, l_crc_error_clear, l_ca_parity_error_status, - l_odt_input_buffer, l_ca_parity, l_data_mask, l_write_dbi, - l_read_dbi, l_ca_parity_latency_buffer, l_rtt_park_buffer); -} - -fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs05_data& i_data, +template<> +fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs05_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs05; -fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs05_decode; +template<> +fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs05_decode; } // ns ddr4 } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06_nimbus.C index 51f1db30116..0871909e65f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06_nimbus.C @@ -27,7 +27,7 @@ /// @file mrs06_nimbus.C /// @brief Run and manage the DDR4 MRS06 loading /// -// *HWP HWP Owner: Stephen Glancy +// *HWP HWP Owner: Matthew Hickman // *HWP HWP Backup: Andre Marin // *HWP Team: Memory // *HWP Level: 3 @@ -38,11 +38,12 @@ #include #include #include +#include +#include #include +#include -using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; - using fapi2::FAPI2_RC_SUCCESS; namespace mss @@ -56,7 +57,9 @@ namespace ddr4 /// @param[in] a fapi2::TARGET_TYPE_DIMM target /// @param[out] fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok /// -mrs06_data::mrs06_data( const fapi2::Target& i_target, fapi2::ReturnCode& o_rc ): +template<> +mrs06_data::mrs06_data( const fapi2::Target& i_target, + fapi2::ReturnCode& o_rc ): iv_tccd_l(0) { FAPI_TRY( mss::eff_vref_dq_train_value(i_target, &(iv_vrefdq_train_value[0])), "Error in mrs06_data()" ); @@ -73,145 +76,16 @@ fapi_try_exit: return; } -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs06 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs06(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - // Check to make sure our ctor worked ok - mrs06_data l_data( i_target, fapi2::current_err ); - FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS06 data from attributes", mss::c_str(i_target) ); - FAPI_TRY( mrs06(i_target, l_data, io_inst, i_rank) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure the ARR0 of the CCS instruction for mrs06, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs06_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs06(const fapi2::Target& i_target, - const mrs06_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank) -{ - using TT = ccsTraits; - - constexpr uint64_t VREFDQ_TRAIN_LENGTH = 6; - constexpr uint64_t VREFDQ_TRAIN_START = 7; - constexpr uint64_t TCCD_L_LENGTH = 3; - constexpr uint64_t TCCD_L_START = 7; - - constexpr uint64_t LOWEST_TCCD = 4; - constexpr uint64_t TCCD_COUNT = 5; - // 4 5 6 7 8 - constexpr uint8_t tccd_l_map[TCCD_COUNT] = { 0b000, 0b001, 0b010, 0b011, 0b100 }; - - fapi2::buffer l_tccd_l_buffer; - fapi2::buffer l_vrefdq_train_value_buffer; - - FAPI_ASSERT((i_data.iv_tccd_l >= LOWEST_TCCD) && (i_data.iv_tccd_l < (LOWEST_TCCD + TCCD_COUNT)), - fapi2::MSS_BAD_MR_PARAMETER() - .set_MR_NUMBER(6) - .set_PARAMETER(TCCD) - .set_PARAMETER_VALUE(i_data.iv_tccd_l) - .set_DIMM_IN_ERROR(i_target), - "Bad value for TCCD: %d (%s)", - i_data.iv_tccd_l, - mss::c_str(i_target)); - - l_tccd_l_buffer = tccd_l_map[i_data.iv_tccd_l - LOWEST_TCCD]; - l_vrefdq_train_value_buffer = i_data.iv_vrefdq_train_value[mss::index(i_rank)]; - - FAPI_INF("%s MR6 rank %d attributes: TRAIN_V: 0x%x(0x%x), TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x(0x%x)", - mss::c_str(i_target), i_rank, i_data.iv_vrefdq_train_value[mss::index(i_rank)], - uint8_t(l_vrefdq_train_value_buffer), i_data.iv_vrefdq_train_range[mss::index(i_rank)], - i_data.iv_vrefdq_train_enable[mss::index(i_rank)], i_data.iv_tccd_l, uint8_t(l_tccd_l_buffer)); - - mss::swizzle(l_vrefdq_train_value_buffer, io_inst.arr0); - io_inst.arr0.writeBit(i_data.iv_vrefdq_train_range[mss::index(i_rank)]); - io_inst.arr0.writeBit(i_data.iv_vrefdq_train_enable[mss::index(i_rank)]); - mss::swizzle(l_tccd_l_buffer, io_inst.arr0); - - FAPI_INF("%s MR6: 0x%016llx", mss::c_str(i_target), uint64_t(io_inst.arr0)); - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function for mrs06_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_vrefdq_train_range the vrefdq training range setting -/// @param[out] o_vrefdq_train_enable the vrefdq training enable setting -/// @param[out] o_tccd_l_buffer the tccd_l setting -/// @param[out] o_vrefdq_train_value_buffer the vrefdq training value -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_vrefdq_train_range, - uint8_t& o_vrefdq_train_enable, - fapi2::buffer& o_tccd_l_buffer, - fapi2::buffer& o_vrefdq_train_value_buffer) -{ - using TT = ccsTraits; - - o_tccd_l_buffer = 0; - o_vrefdq_train_value_buffer = 0; - - mss::swizzle<2, 6, TT::A5>(i_inst.arr0, o_vrefdq_train_value_buffer); - o_vrefdq_train_range = i_inst.arr0.getBit(); - o_vrefdq_train_enable = i_inst.arr0.getBit(); - mss::swizzle<5, 3, TT::A12>(i_inst.arr0, o_tccd_l_buffer); - - FAPI_INF("MR6 rank %d decode: TRAIN_V: 0x%x, TRAIN_R: 0x%x, TRAIN_E: 0x%x, TCCD_L: 0x%x", - i_rank, uint8_t(o_vrefdq_train_value_buffer), o_vrefdq_train_range, - o_vrefdq_train_enable, uint8_t(o_tccd_l_buffer)); - - return FAPI2_RC_SUCCESS; -} - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS6, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank) -{ - fapi2::buffer l_tccd_l_buffer; - fapi2::buffer l_vrefdq_train_value_buffer; - uint8_t l_vrefdq_train_range = 0; - uint8_t l_vrefdq_train_enable = 0; - - return mrs06_decode_helper(i_inst, i_rank, l_vrefdq_train_range, l_vrefdq_train_enable, - l_tccd_l_buffer, l_vrefdq_train_value_buffer); -} - -fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const fapi2::Target& i_target, - const mrs06_data& i_data, +template<> +fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const + fapi2::Target& i_target, + const mrs06_data& i_data, ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs06; -fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t& i_inst, - const uint64_t i_rank) = &mrs06_decode; +template<> +fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t& i_inst, + const uint64_t i_rank) = &mrs06_decode; } // ns ddr4 } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.C index e97eebba0d9..6b3d10b109a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.C @@ -43,6 +43,14 @@ #include #include +#include +#include +#include +#include +#include +#include +#include + using fapi2::TARGET_TYPE_DIMM; using fapi2::FAPI2_RC_SUCCESS; @@ -77,8 +85,8 @@ fapi_try_exit: /// @note Based off of Table 2.8 Proposed DDR4 Full spec update(79-4B) page 28 /// template<> -fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_target, - bool& o_is_needed) +fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_target, + bool& o_is_needed) { uint8_t l_dram_density = 0; uint8_t l_dram_width = 0; @@ -103,8 +111,8 @@ fapi_try_exit: /// @note Based off of Table 2.8 Proposed DDR4 Full spec update(79-4B) page 28 /// template<> -fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_target, - bool& o_is_needed) +fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_target, + bool& o_is_needed) { // Set this to good in case no dimms and we're running unit tests fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -118,7 +126,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_t // Default to not used // Using temp because we want to OR the two results together. Don't want the false to overwrite bool l_temp = false; - FAPI_TRY( is_a17_needed( l_dimm, l_temp), "%s Failed to get a17 boolean", mss::c_str(l_dimm) ); + FAPI_TRY( is_a17_needed( l_dimm, l_temp), "%s Failed to get a17 boolean", mss::c_str(l_dimm) ); o_is_needed = o_is_needed | l_temp; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.H index 962831ce8f8..2a20eacbe49 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4_nimbus.H @@ -47,418 +47,6 @@ namespace mss namespace ddr4 { -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs00 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs00(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs01 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs01(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs02 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs02(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs03 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs03(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs04 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs04(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs05 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs05(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs06 -/// @param[in] i_target a fapi2::Target -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs06(const fapi2::Target& i_target, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// }@ - -/// -/// @defgroup setup-ccs-overloads -/// @addtogroyp setup-ccs-overloads -/// API which setup CCS instructions, but take an MRS data object as input -/// @{ - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs00, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs00_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs00(const fapi2::Target& i_target, - const mrs00_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs01, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs01_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs01(const fapi2::Target& i_target, - const mrs01_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs02, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs02_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs02(const fapi2::Target& i_target, - const mrs02_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs03, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs00_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs03(const fapi2::Target& i_target, - const mrs03_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs04, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs04_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs04(const fapi2::Target& i_target, - const mrs04_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs05, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs05_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs05(const fapi2::Target& i_target, - const mrs05_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// -/// @brief Configure the ARR0 of the CCS isntruction for mrs06, data object as input -/// @param[in] i_target a fapi2::Target -/// @param[in] i_data an mrs06_data object, filled in -/// @param[in,out] io_inst the instruction to fixup -/// @param[in] i_rank ths rank in question -/// @return FAPI2_RC_SUCCESS iff OK -/// -fapi2::ReturnCode mrs06(const fapi2::Target& i_target, - const mrs06_data& i_data, - ccs::instruction_t& io_inst, - const uint64_t i_rank); - -/// }@ - -/// -/// @defgroup ccs-decode -/// @addtogroyccs-decode -/// API which decode CCS instructions. -/// @{ - -/// -/// @brief Helper function for mrs00_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_burst_length the burst length -/// @param[out] o_read_burst_type the burst type -/// @param[out] o_dll_reset the dll reset bit -/// @param[out] o_test_mode the test mode bit -/// @param[out] o_wr_index the write index -/// @param[out] o_cas_latency the cas latency -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_burst_length, - uint8_t& o_read_burst_type, - uint8_t& o_dll_reset, - uint8_t& o_test_mode, - fapi2::buffer& o_wr_index, - fapi2::buffer& o_cas_latency); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS00, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs01_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_dll_enable the dll enable bit -/// @param[out] o_wrl_enable the write leveling enable bit -/// @param[out] o_tdqs the tdqs enable bit -/// @param[out] o_qoff the qoff bit -/// @param[out] o_odic the output driver impedance control setting -/// @param[out] o_additive_latency the additive latency setting -/// @param[out] o_rtt_nom the rtt_nom setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_dll_enable, - uint8_t& o_wrl_enable, - uint8_t& o_tdqs, - uint8_t& o_qoff, - fapi2::buffer& o_odic, - fapi2::buffer& o_additive_latency, - fapi2::buffer& o_rtt_nom); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS01, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs02_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_write_crc the write crc bit -/// @param[out] o_lpasr the low power array self refresh setting -/// @param[out] o_cwl the cas write latency setting -/// @param[out] o_rtt_wr the rtt_wr setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_write_crc, - fapi2::buffer& o_lpasr, - fapi2::buffer& o_cwl, - fapi2::buffer& o_rtt_wr); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS02, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs03_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_mpr_mode the mpr operation setting -/// @param[out] o_geardown the geardown mode setting -/// @param[out] o_pda the per dram addressability setting -/// @param[out] o_temp_readout the temperature sensor readout setting -/// @param[out] o_mpr_page the mpr page selection -/// @param[out] o_fine_refresh the fine granularity refresh mode setting -/// @param[out] o_crc_wr_latency_buffer the write cmd latency when crc and dm are enabled -/// @param[out] o_read_fromat the mpr read format setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_mpr_mode, - uint8_t& o_geardown, - uint8_t& o_pda, - uint8_t& o_temp_readout, - fapi2::buffer& o_mpr_page, - fapi2::buffer& o_fine_refresh, - fapi2::buffer& o_crc_wr_latency_buffer, - fapi2::buffer& o_read_format); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS03, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs04_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_max_pd_mode the maximum power down mode setting -/// @param[out] o_temp_refresh_range the temperature controlled refresh range setting -/// @param[out] o_temp_ref_mode the temperature controlled refresh mode setting -/// @param[out] o_vref_mon the internal vref monitor setting -/// @param[out] o_ref_abort the self refresh abort setting -/// @param[out] o_rd_pre_train_mode the read preamble training mode setting -/// @param[out] o_rd_preamble the read preamble setting -/// @param[out] o_wr_preamble the write preamble setting -/// @param[out] o_ppr the ppr setting -/// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_max_pd_mode, - uint8_t& o_temp_refresh_range, - uint8_t& o_temp_ref_mode, - uint8_t& o_vref_mon, - uint8_t& o_ref_abort, - uint8_t& o_rd_pre_train_mode, - uint8_t& o_rd_preamble, - uint8_t& o_wr_preamble, - uint8_t& o_ppr, - uint8_t& o_soft_ppr, - fapi2::buffer& o_cs_cmd_latency_buffer); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS04, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs05_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_crc_error_clear the crc error clear setting -/// @param[out] o_ca_parity_error_status the c/a parity error status -/// @param[out] o_odt_input_buffer the odt input buffer during power down mode setting -/// @param[out] o_ca_parity the c/a parity persistent error setting -/// @param[out] o_data_mask the data mask setting -/// @param[out] o_write_dbi the write dbi setting -/// @param[out] o_read_dbi the read dbi setting -/// @param[out] o_ca_parity_latency_buffer the c/a parity latency mode setting -/// @param[out] o_rtt_park_buffer the rtt_park setting -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_crc_error_clear, - uint8_t& o_ca_parity_error_status, - uint8_t& o_odt_input_buffer, - uint8_t& o_ca_parity, - uint8_t& o_data_mask, - uint8_t& o_write_dbi, - uint8_t& o_read_dbi, - fapi2::buffer& o_ca_parity_latency_buffer, - fapi2::buffer& o_rtt_park_buffer); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS05, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// -/// @brief Helper function for mrs06_decode -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @param[out] o_vrefdq_train_range the vrefdq training range setting -/// @param[out] o_vrefdq_train_enable the vrefdq training enable setting -/// @param[out] o_tccd_l_buffer the tccd_l setting -/// @param[out] o_vrefdq_train_value_buffer the vrefdq training value -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, - const uint64_t i_rank, - uint8_t& o_vrefdq_train_range, - uint8_t& o_vrefdq_train_enable, - fapi2::buffer& o_tccd_l_buffer, - fapi2::buffer& o_vrefdq_train_value_buffer); - -/// -/// @brief Given a CCS instruction which contains address bits with an encoded MRS06, -/// decode and trace the contents -/// @param[in] i_inst the CCS instruction -/// @param[in] i_rank the rank in question -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, - const uint64_t i_rank); - -/// @} - /// /// @brief Perform the mrs_load DDR4 operations - TARGET_TYPE_DIMM specialization /// @param[in] i_target a fapi2::Target diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.C index df84c2a4909..afb326dd3fa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda_nimbus.C @@ -236,7 +236,7 @@ fapi2::ReturnCode add_enable( const fapi2::Target& i_ta const uint64_t i_rank, std::vector< ccs::instruction_t >& io_inst ) { - mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); + mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); // Overrides the PDA value to be enabled @@ -288,7 +288,7 @@ fapi2::ReturnCode add_disable( const fapi2::Target& i_t const uint64_t i_rank, std::vector< ccs::instruction_t >& io_inst ) { - mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); + mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); // Overrides the PDA value to be disabled @@ -348,9 +348,10 @@ fapi_try_exit: /// @note A PDA latch of WR VREF settings is the most common PDA operations /// This function adds a bit of fanciness (compression) to speed up the overall runtime /// -fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target& i_target, +template<> +fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target& i_target, const uint64_t i_rank, - const mss::ddr4::mrs06_data& i_mrs, + const mss::ddr4::mrs06_data& i_mrs, const std::vector& i_drams ) { const auto& l_mca = mss::find_target(i_target); @@ -400,7 +401,9 @@ fapi_try_exit: /// @note A PDA latch of WR VREF settings is the most common PDA operations /// This function adds a bit of fanciness (compression) to speed up the overall runtime /// -fapi2::ReturnCode execute_wr_vref_latch( const commands& i_commands ) +template<> +fapi2::ReturnCode execute_wr_vref_latch( const + commands>& i_commands ) { // If the commands passed in are empty, simply exit FAPI_ASSERT((!i_commands.empty()), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 3cefd2fa20e..1a1fa0e688b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -1551,7 +1551,7 @@ fapi2::ReturnCode eff_dimm::dimm_rc02() fapi2::buffer l_temp; bool is_a17 = false; - FAPI_TRY( is_a17_needed( iv_dimm, is_a17), "%s Failed to get a17 boolean", mss::c_str(iv_dimm) ); + FAPI_TRY( is_a17_needed( iv_dimm, is_a17), "%s Failed to get a17 boolean", mss::c_str(iv_dimm) ); l_temp.writeBit(is_a17 ? rc02_encode::A17_ENABLE : rc02_encode::A17_DISABLE); FAPI_TRY( eff_dimm_ddr4_rc02(iv_mcs, &l_attrs_dimm_rc02[0][0]) ); @@ -1914,7 +1914,8 @@ fapi2::ReturnCode eff_dimm::dimm_rc08() { bool l_is_a17 = false; - FAPI_TRY( is_a17_needed( iv_dimm, l_is_a17), "%s Failed to get a17 boolean", mss::c_str(iv_dimm) ); + FAPI_TRY( is_a17_needed( iv_dimm, l_is_a17), "%s Failed to get a17 boolean", + mss::c_str(iv_dimm) ); l_buffer.writeBit(l_is_a17 ? DA17_QA17_ENABLE : DA17_QA17_DISABLE); FAPI_INF("%s Turning %s DA17", mss::c_str(iv_dimm), (l_is_a17 ? "on" : "off")); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_traits_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_traits_nimbus.H index 0a62b373549..b7d4c745252 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_traits_nimbus.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_traits_nimbus.H @@ -59,15 +59,6 @@ class mrsTraits static constexpr uint64_t TCCD_S = 4; static constexpr uint64_t TMRD = 8; - /// - /// @brief Returns an error for bad mrs parameter - /// @return mrs error - /// - static fapi2::MSS_BAD_MR_PARAMETER bad_mr_parameter() - { - return fapi2::MSS_BAD_MR_PARAMETER(); - } - /// /// @brief Returns the attribute rcd mirror mode on /// @return rcd mirror mode on @@ -80,10 +71,12 @@ class mrsTraits /// /// @brief Returns the ATTR_EFF_DIMM_RCD_MIRROR_MODE getter /// @param[in] const ref to the fapi2::Target + /// @param[in] i_rank the rank on which to operate /// @param[out] ref to the value uint8_t /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// static fapi2::ReturnCode mirror_mode(const fapi2::Target& i_target, + const uint64_t i_rank, uint8_t& o_value) { return mss::eff_dimm_rcd_mirror_mode(i_target, o_value); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 5bf986ac061..d1e265da759 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -695,7 +695,7 @@ fapi2::ReturnCode write_ctr::post_workaround( const fapi2::Target l_container; + mss::ddr4::pda::commands> l_container; // Loops through and sets up all the data needed the workaround for(const auto& l_pair : l_bad_drams ) @@ -705,7 +705,7 @@ fapi2::ReturnCode write_ctr::post_workaround( const fapi2::Target l_mrs(l_dimm, l_rc); FAPI_TRY(l_rc, "%s failed to create MRS06 data class", mss::c_str(l_dimm)); // Updates the MRS06 settings to have the proper VREF settings diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H index 53050bcf39a..bc01edcb491 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/seq.H @@ -546,7 +546,7 @@ fapi2::ReturnCode reset_config0( const fapi2::Target& i_target ) // Let's figure out if the A17 bit is on/ needed for parity calculations bool l_a17 = false; - FAPI_TRY( is_a17_needed( i_target, l_a17) ); + FAPI_TRY( is_a17_needed( i_target, l_a17) ); { const auto l_encoding = l_a17 ? TT::A17_IS_USED : TT::A17_IS_NOT_USED; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C index cab9f308598..1bf5ab3b2b0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C @@ -485,7 +485,7 @@ namespace wr_lvl /// @param[in,out] io_mrs - the MRS to update /// @param[in] i_state - the state for the qoff in the MRS /// -void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state) +void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state) { io_mrs.iv_qoff = i_state; io_mrs.iv_wl_enable = i_state; @@ -513,7 +513,7 @@ fapi2::ReturnCode add_mrs(const fapi2::Target& i_target, { // Get the MRS data fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; - mss::ddr4::mrs01_data l_mrs(l_dimm, l_rc); + mss::ddr4::mrs01_data l_mrs(l_dimm, l_rc); FAPI_TRY( l_rc, "%s failed to create MRS for rank %lu", mss::c_str(l_dimm), i_rank); // Update the MRS data for qoff diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H index 616905c7f6e..3dfee11325a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H @@ -216,7 +216,7 @@ namespace wr_lvl /// @param[in,out] io_mrs - the MRS to update /// @param[in] i_state - the state for the qoff in the MRS /// -void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state); +void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state); /// /// @brief Adds in an MRS on a per-rank basis based upon qoff diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C index 9253096dcc2..072f42815ab 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C @@ -1965,7 +1965,7 @@ fapi_try_exit: /// @note The differing values can cause WR VREF fail, so the bit(s) that differ are disabled temporarily /// fapi2::ReturnCode modify_mrs_vref_to_vpd( const fapi2::Target& i_target, - mss::ddr4::mrs06_data& io_mrs06 ) + mss::ddr4::mrs06_data& io_mrs06 ) { // Gets the VPD JEDEC WR VREF information uint8_t l_train_value = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H index 77cff02c59a..f40fd1dbbf5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H @@ -796,7 +796,7 @@ fapi2::ReturnCode configure_skip_bits( const fapi2::Target& i_target, - mss::ddr4::mrs06_data& io_mrs06 ); + mss::ddr4::mrs06_data& io_mrs06 ); /// /// @brief Resets the WR DQ delays for a given DRAM to be a quarter clock before the DQS diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H index 43d16947e77..d5d8b355a55 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H @@ -47,6 +47,14 @@ #include #include +#include +#include +#include +#include +#include +#include +#include + namespace mss { @@ -154,7 +162,7 @@ class shadow_regs_traits<0> uint64_t l_freq = 0; // Check to make sure our ctor worked ok - mss::ddr4::mrs00_data l_data( i_target, fapi2::current_err ); + mss::ddr4::mrs00_data l_data( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS00 data from attributes", mss::c_str(i_target) ); FAPI_TRY( mss::eff_dimm_type(i_target, l_dimm_type)); FAPI_TRY( mss::freq(mss::find_target(i_target), l_freq)); diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml index f8177810ce4..69688abfdc8 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit.xml @@ -5,7 +5,7 @@ - + @@ -60,32 +60,4 @@ - - - RC_MSS_BAD_MR_PARAMETER - - A bad parameter was passed to MR processing - This is probably due to a bad value received from the SPD (e.g. unsupported cas latency) - Could be a code error - - MR_NUMBER - PARAMETER - PARAMETER_VALUE - - MEMORY_PLUGGING_ERROR - HIGH - - - CODE - MEDIUM - - - DIMM_IN_ERROR - LOW - - - DIMM_IN_ERROR - - - diff --git a/src/import/generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H index adc5e64f180..920b9fa04b7 100644 --- a/src/import/generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/generic/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -107,7 +107,7 @@ fapi2::ReturnCode address_mirror(const fapi2::Target& i { // We only mirror if the mirroring attribute is set. uint8_t l_mirror = 0; - FAPI_TRY( TT::mirror_mode(i_target, l_mirror), + FAPI_TRY( TT::mirror_mode(i_target, i_rank, l_mirror), "Failed to invoke rcd_mirror_mode accesor on %s", mss::c_str(i_target) ); // We only mirror odd ranks. @@ -208,13 +208,14 @@ fapi_try_exit: /// /// @brief Helper function to determine whether the A17 is needed -/// @tparam T fapi2::TargetType DIMM or MCA +/// @tparam mc_type MC +/// @tparam T fapi2::TargetType DIMM or port type /// @param[in] i_target the target to check /// @param[out] o_is_needed boolean whether A17 should be turned on or off /// @return fapi2::FAPI2_RC_SUCCESS if okay /// @note Based off of Table 2.8 Proposed DDR4 Full spec update(79-4B) page 28 /// -template< fapi2::TargetType T> +template< mss::mc_type MC, fapi2::TargetType T> fapi2::ReturnCode is_a17_needed(const fapi2::Target& i_target, bool& o_is_needed); @@ -254,7 +255,7 @@ fapi2::ReturnCode mrs_engine( const fapi2::Target& i_ta i_data.iv_mrs, i_rank, mss::c_str(i_target) ); // So we need to see if the A17 bit is enabled. If it is we need to invert it for the CCS parity - FAPI_TRY( is_a17_needed( i_target, l_is_a17) ); + FAPI_TRY( is_a17_needed( i_target, l_is_a17) ); l_inst_b_side = mss::address_invert(i_target, l_inst_a_side, l_is_a17); // Not sure if we can get tricky here and only delay after the b-side MR. The question is whether the delay @@ -302,13 +303,26 @@ namespace ddr4 { // Forward declarations -class mrs00_data; -class mrs01_data; -class mrs02_data; -class mrs03_data; -class mrs04_data; -class mrs05_data; -class mrs06_data; +template< mss::mc_type MC > +struct mrs00_data; + +template< mss::mc_type MC > +struct mrs01_data; + +template< mss::mc_type MC > +struct mrs02_data; + +template< mss::mc_type MC > +struct mrs03_data; + +template< mss::mc_type MC > +struct mrs04_data; + +template< mss::mc_type MC > +struct mrs05_data; + +template< mss::mc_type MC > +struct mrs06_data; /// /// @defgroup mrs-structs @@ -319,7 +333,9 @@ class mrs06_data; /// /// @brief Data structure for MRS0 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs00_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -355,7 +371,7 @@ struct mrs00_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs00_data& i_rhs) const + bool operator<(const mss::ddr4::mrs00_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // write recover/RTP @@ -398,7 +414,7 @@ struct mrs00_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs00_data& i_rhs) const + bool operator==(const mss::ddr4::mrs00_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -413,7 +429,9 @@ struct mrs00_data /// /// @brief Data structure for MRS1 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs01_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -446,7 +464,7 @@ struct mrs01_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs01_data& i_rhs) const + bool operator<(const mss::ddr4::mrs01_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // Qoff @@ -499,7 +517,7 @@ struct mrs01_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs01_data& i_rhs) const + bool operator==(const mss::ddr4::mrs01_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -515,7 +533,9 @@ struct mrs01_data /// /// @brief Data structure for MRS2 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs02_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -548,7 +568,7 @@ struct mrs02_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs02_data& i_rhs) const + bool operator<(const mss::ddr4::mrs02_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // write crc @@ -581,7 +601,7 @@ struct mrs02_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs02_data& i_rhs) const + bool operator==(const mss::ddr4::mrs02_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -595,7 +615,9 @@ struct mrs02_data /// /// @brief Data structure for MRS3 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs03_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -628,7 +650,7 @@ struct mrs03_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs03_data& i_rhs) const + bool operator<(const mss::ddr4::mrs03_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // MPR read format @@ -683,7 +705,7 @@ struct mrs03_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs03_data& i_rhs) const + bool operator==(const mss::ddr4::mrs03_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -700,7 +722,9 @@ struct mrs03_data /// /// @brief Data structure for MRS4 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs04_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -733,7 +757,7 @@ struct mrs04_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs04_data& i_rhs) const + bool operator<(const mss::ddr4::mrs04_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // PPR @@ -806,7 +830,7 @@ struct mrs04_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs04_data& i_rhs) const + bool operator==(const mss::ddr4::mrs04_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -826,7 +850,9 @@ struct mrs04_data /// /// @brief Data structure for MRS5 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs05_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -859,7 +885,7 @@ struct mrs05_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs05_data& i_rhs) const + bool operator<(const mss::ddr4::mrs05_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // Read DBI @@ -922,7 +948,7 @@ struct mrs05_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs05_data& i_rhs) const + bool operator==(const mss::ddr4::mrs05_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -940,7 +966,9 @@ struct mrs05_data /// /// @brief Data structure for MRS6 data +/// @tparam MC mss::mc_type memory controller type /// +template< mss::mc_type MC > struct mrs06_data { // Needed as we need to know what MR for the CCS instruction created by the lab tooling @@ -973,7 +1001,7 @@ struct mrs06_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is less than i_rhs /// - bool operator<(const mss::ddr4::mrs06_data& i_rhs) const + bool operator<(const mss::ddr4::mrs06_data& i_rhs) const { // MSB to LSB - 2015 JEDEC spec // TCCD_L @@ -1009,7 +1037,7 @@ struct mrs06_data /// @param[in] i_rhs right hand comparison operator /// @bool true if this object is equal to i_rhs /// - bool operator==(const mss::ddr4::mrs06_data& i_rhs) const + bool operator==(const mss::ddr4::mrs06_data& i_rhs) const { return !((*this < i_rhs) || (i_rhs < *this)); } @@ -1034,12 +1062,12 @@ struct mrs06_data template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_wr_lvl_mode(const fapi2::Target& i_target, const mss::states i_mode, - mrs01_data& io_data) + mrs01_data& io_data) { constexpr uint64_t MAX_WR_LVL_MODE = 0b1; FAPI_ASSERT( i_mode <= MAX_WR_LVL_MODE, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(WR_LVL) .set_PARAMETER_VALUE(i_mode) @@ -1071,12 +1099,12 @@ fapi_try_exit: template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_dram_mpr_mode(const fapi2::Target& i_target, const uint8_t i_mode, - mrs03_data& io_data) + mrs03_data& io_data) { constexpr uint64_t MAX_MPR_MODE = 0b1; FAPI_ASSERT( i_mode <= MAX_MPR_MODE, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(MPR_MODE) .set_PARAMETER_VALUE(i_mode) @@ -1104,14 +1132,14 @@ fapi_try_exit: template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_dram_rtt_nom(const fapi2::Target& i_target, const uint8_t i_value[MAX_RANK_PER_DIMM], - mrs01_data& io_data) + mrs01_data& io_data) { constexpr uint64_t MAX_RTT_NOM = RTT_NOM_RZQ_OVER_7; for (size_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) { FAPI_ASSERT( i_value[l_rank] <= MAX_RTT_NOM, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(RTT_NOM) .set_PARAMETER_VALUE(i_value[l_rank]) @@ -1142,14 +1170,14 @@ fapi_try_exit: template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_dram_rtt_wr(const fapi2::Target& i_target, const uint8_t i_value[MAX_RANK_PER_DIMM], - mrs02_data& io_data) + mrs02_data& io_data) { constexpr uint64_t MAX_RTT_WR = RTT_WR_RZQ_OVER_3; for (size_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) { FAPI_ASSERT( i_value[l_rank] <= MAX_RTT_WR, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(RTT_WR) .set_PARAMETER_VALUE(i_value[l_rank]) @@ -1180,12 +1208,12 @@ fapi_try_exit: template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_dram_mpr_rd_format(const fapi2::Target& i_target, const uint8_t i_format, - mrs03_data& io_data) + mrs03_data& io_data) { constexpr uint64_t MAX_READ_FORMAT = 0b10; FAPI_ASSERT( i_format <= MAX_READ_FORMAT, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(MPR_READ_FORMAT) .set_PARAMETER_VALUE(i_format) @@ -1215,12 +1243,12 @@ fapi_try_exit: template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > fapi2::ReturnCode set_dram_mpr_page(const fapi2::Target& i_target, const uint8_t i_page, - mrs03_data& io_data) + mrs03_data& io_data) { constexpr uint64_t MAX_PAGE = 0b11; FAPI_ASSERT( i_page <= MAX_PAGE, - TT::bad_mr_parameter() + fapi2::MSS_BAD_MR_PARAMETER() .set_MR_NUMBER(MRS_LOAD) .set_PARAMETER(MPR_PAGE) .set_PARAMETER_VALUE(i_page) @@ -1246,17 +1274,16 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -inline fapi2::ReturnCode wr_lvl(const fapi2::Target& i_target, - const mss::states i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t >& io_inst ) +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > +fapi2::ReturnCode wr_lvl(const fapi2::Target& i_target, + const mss::states i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - using TT = mrsTraits; - // Spec states we need to use tmod for our delay, so we do const uint64_t l_delay = TT::mrs_tmod(i_target); - mrs01_data l_data(i_target, fapi2::current_err); + mrs01_data l_data(i_target, fapi2::current_err); FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs01_data for set_wr_lvl_mode", mss::c_str(i_target) ); FAPI_TRY( set_wr_lvl_mode(i_target, i_mode, l_data), @@ -1280,18 +1307,17 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -inline fapi2::ReturnCode mpr_load(const fapi2::Target& i_target, - const uint8_t i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t >& io_inst ) +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > +fapi2::ReturnCode mpr_load(const fapi2::Target& i_target, + const uint8_t i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - using TT = mrsTraits; - // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode const uint64_t l_delay = std::max( TT::mrs_tmod(i_target), TT::TMRD ); - mrs03_data l_data(i_target, fapi2::current_err); + mrs03_data l_data(i_target, fapi2::current_err); FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs03_data for mpr_load", mss::c_str(i_target) ); FAPI_TRY( set_dram_mpr_mode(i_target, i_mode, l_data), @@ -1316,19 +1342,18 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -inline fapi2::ReturnCode mpr_load(const fapi2::Target& i_target, - const uint8_t i_mode, - const uint8_t i_rd_format, - const uint64_t i_rank, - std::vector< ccs::instruction_t >& io_inst ) +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > +fapi2::ReturnCode mpr_load(const fapi2::Target& i_target, + const uint8_t i_mode, + const uint8_t i_rd_format, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - using TT = mrsTraits; - // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode const uint64_t l_delay = std::max( TT::mrs_tmod(i_target), TT::TMRD ); - mrs03_data l_data(i_target, fapi2::current_err); + mrs03_data l_data(i_target, fapi2::current_err); FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs03_data for mpr_load", mss::c_str(i_target) ); FAPI_TRY( set_dram_mpr_mode(i_target, i_mode, l_data), @@ -1356,17 +1381,16 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -inline fapi2::ReturnCode rtt_nom_load(const fapi2::Target& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t >& io_inst ) +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > +fapi2::ReturnCode rtt_nom_load(const fapi2::Target& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - using TT = mrsTraits; - // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = TT::TMRD; - mrs01_data l_data(i_target, fapi2::current_err); + mrs01_data l_data(i_target, fapi2::current_err); FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs01_data for rtt_nom_load", mss::c_str(i_target) ); FAPI_TRY( set_dram_rtt_nom(i_target, i_value, l_data), @@ -1390,17 +1414,16 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -inline fapi2::ReturnCode rtt_wr_load(const fapi2::Target& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t >& io_inst ) +template< mss::mc_type MC = DEFAULT_MC_TYPE, typename TT = mrsTraits > +fapi2::ReturnCode rtt_wr_load(const fapi2::Target& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - using TT = mrsTraits; - // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = TT::TMRD; - mrs02_data l_data(i_target, fapi2::current_err); + mrs02_data l_data(i_target, fapi2::current_err); FAPI_TRY(fapi2::current_err, "%s. Failed to initialize mrs02_data for rtt_wr_load", mss::c_str(i_target) ); FAPI_TRY( set_dram_rtt_wr(i_target, i_value, l_data), diff --git a/src/import/generic/memory/lib/dimm/ddr4/pda.H b/src/import/generic/memory/lib/dimm/ddr4/pda.H index 5dd10a4f13e..9070753343e 100644 --- a/src/import/generic/memory/lib/dimm/ddr4/pda.H +++ b/src/import/generic/memory/lib/dimm/ddr4/pda.H @@ -312,6 +312,7 @@ class commands /// /// @brief Performs a PDA WR VREF latch +/// @tparam MC mss::mc_type memory controller type /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_rank the rank to send to /// @param[in] i_mrs the MRS data to update @@ -320,19 +321,22 @@ class commands /// @note A PDA latch of WR VREF settings is the most common PDA operations /// This function adds a bit of fanciness (compression) to speed up the overall runtime /// +template< mss::mc_type MC = DEFAULT_MC_TYPE > fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target& i_target, const uint64_t i_rank, - const mss::ddr4::mrs06_data& i_mrs, + const mss::ddr4::mrs06_data& i_mrs, const std::vector& i_drams ); /// /// @brief Performs a PDA WR VREF latch +/// @tparam MC mss::mc_type memory controller type /// @param[in] i_commands the PDA commands to issue and DRAM /// @return FAPI2_RC_SUCCESS if and only if ok /// @note A PDA latch of WR VREF settings is the most common PDA operations /// This function adds a bit of fanciness (compression) to speed up the overall runtime /// -fapi2::ReturnCode execute_wr_vref_latch( const commands& i_commands ); +template< mss::mc_type MC = DEFAULT_MC_TYPE > +fapi2::ReturnCode execute_wr_vref_latch( const commands>& i_commands ); } // ns pda diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 9462529b75f..b84cb530f11 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -273,6 +273,10 @@ enum generic_ffdc_codes SET_RCD_MFG_ID = 0x109B, SET_DRAM_MODULE_HEIGHT = 0x109C, SET_SPD_REVISION = 0x109D, + + MRS_MIRROR_MODE = 0x109E, + MRS01_GEN = 0x109F, + MRS02_GEN = 0x10A0, }; /// diff --git a/src/import/generic/procedures/xml/error_info/generic_error.xml b/src/import/generic/procedures/xml/error_info/generic_error.xml index 43440ce2ee9..9a6200c9680 100644 --- a/src/import/generic/procedures/xml/error_info/generic_error.xml +++ b/src/import/generic/procedures/xml/error_info/generic_error.xml @@ -37,6 +37,33 @@ + + RC_MSS_BAD_MR_PARAMETER + + A bad parameter was passed to MR processing + This is probably due to a bad value received from the SPD (e.g. unsupported cas latency) + Could be a code error + + MR_NUMBER + PARAMETER + PARAMETER_VALUE + + MEMORY_PLUGGING_ERROR + HIGH + + + CODE + MEDIUM + + + DIMM_IN_ERROR + LOW + + + DIMM_IN_ERROR + + + RC_MSS_DIVIDE_BY_ZERO