diff --git a/src/include/usr/isteps/istep06list.H b/src/include/usr/isteps/istep06list.H index 170837c02bb..f80a814c333 100644 --- a/src/include/usr/isteps/istep06list.H +++ b/src/include/usr/isteps/istep06list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* Contributors Listed Below - COPYRIGHT 2012,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -235,6 +235,7 @@ const DepModInfo g_istep06Dependancies = { DEP_LIB(libimageprocs.so), DEP_LIB(libp9_cpuWkup.so), DEP_LIB(libisteps_nest.so), + DEP_LIB(libruntime.so), NULL } }; diff --git a/src/include/usr/targeting/common/hbrt_target.H b/src/include/usr/targeting/common/hbrt_target.H index 1a6989bf4ba..0ea42e8137a 100644 --- a/src/include/usr/targeting/common/hbrt_target.H +++ b/src/include/usr/targeting/common/hbrt_target.H @@ -25,20 +25,49 @@ #ifndef __HBRT_TARGET_H #define __HBRT_TARGET_H -#include +#include namespace TARGETING { typedef uint64_t rtChipId_t; + + struct ocmbMmioAddressRange_t { + rtChipId_t hbrtId; // Keep hbrtId as the first member of this struct + // there is some tricky casting that depends on this + uint64_t mmioBaseAddr; + uint64_t mmioEndAddr; + uint8_t accessSize; + + ocmbMmioAddressRange_t() : + hbrtId(0), mmioBaseAddr(0), mmioEndAddr(0), accessSize(4) + {} + + ocmbMmioAddressRange_t(uint64_t id, uint64_t start_addr, uint64_t end_addr, uint8_t io_size) : + hbrtId(id), mmioBaseAddr(start_addr), mmioEndAddr(end_addr), accessSize(io_size) + {} + } __attribute__((packed)); + /** * @brief Convert a TARGETING::Target to an unit ID that can be used * in calls to the runtime host * @param[in] The HB TARGETING::Target - * @param[out] Sapphire target id + * @param[out] Hypervisor target id * @return an error handle on error */ errlHndl_t getRtTarget(const TARGETING::Target* i_target, - rtChipId_t &o_targetId); + rtChipId_t &o_targetId); + + /** + * @brief Takes a TARGETING::Target and passes back a vector of ocmbMmioAddressRange_t + * structs, one for each memory mapped i/o space associated with a given memory + * target. + * @param[in] The HB Memory TARGETING::Target + * @param[out] Vector of structs representing the mmio spaces associated with + * the given memory target + * @return an error handle on error + */ + errlHndl_t getMemTargetMmioInfo ( TARGETING::Target * i_memTarget, + std::vector& o_ocmbMmioSpaces); } diff --git a/src/usr/isteps/istep06/host_discover_targets.C b/src/usr/isteps/istep06/host_discover_targets.C index 7884056c149..a63eaed8f16 100644 --- a/src/usr/isteps/istep06/host_discover_targets.C +++ b/src/usr/isteps/istep06/host_discover_targets.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -55,6 +55,7 @@ #endif #include #include +#include //SBE interfacing #include @@ -681,6 +682,19 @@ void* host_discover_targets( void *io_pArgs ) errlCommit( l_err, ISTEP_COMP_ID ); } + // Now that we have all of the targets set up we can assign HBRT ids + // to all of the targets. These are the IDs the Hypervisors use to ID + // a given target. We set them up now because we want to make sure the + // attribute is set long before HDAT code consumes them. + l_err = RUNTIME::configureHbrtHypIds(TARGETING::is_phyp_load()); + if(l_err) + { + // Create IStep error log and cross reference occurred error + l_stepError.addErrorDetails( l_err ); + // Commit Error + errlCommit (l_err, ISTEP_COMP_ID); + } + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "host_discover_targets exit" ); diff --git a/src/usr/mmio/mmio.C b/src/usr/mmio/mmio.C index ff7eec6613b..1ba123a0ccf 100644 --- a/src/usr/mmio/mmio.C +++ b/src/usr/mmio/mmio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -105,7 +105,7 @@ errlHndl_t mmioSetup() l_mcTarget->getAttr(); // Get the base BAR address for OpenCapi Memory Interfaces (OMIs) of this Memory Controller (MC) - auto l_omiBaseAddr = + auto l_mcBaseOffset = l_mcTarget->getAttr(); // Build up the full address with group/chip address considerations @@ -115,21 +115,21 @@ errlHndl_t mmioSetup() l_parentChip->getAttr(); uint8_t l_chipId = l_parentChip->getAttr(); - uint64_t l_realAddr = computeMemoryMapOffset( MMIO_BASE, + uint64_t l_physMcAddr = computeMemoryMapOffset( MMIO_BASE, l_groupId, l_chipId ); // Apply the MMIO base offset so we get the final address - l_realAddr += l_omiBaseAddr; + l_physMcAddr += l_mcBaseOffset; // Map the device with a kernel call, each device, the MC, is 32 GB - uint64_t l_virtAddr = reinterpret_cast - (mmio_dev_map(reinterpret_cast(l_realAddr), + uint64_t l_virtMcAddr = reinterpret_cast + (mmio_dev_map(reinterpret_cast(l_physMcAddr), THIRTYTWO_GB)); TRACFCOMP ( g_trac_mmio, "MC%.02X (0x%.08X) MMIO BAR PHYSICAL ADDR = 0x%lX VIRTUAL ADDR = 0x%lX" , l_mcChipUnit ? 0x23 : 0x01, get_huid(l_mcTarget), - l_realAddr, l_virtAddr); + l_physMcAddr, l_virtMcAddr); // set VM_ADDR on each OCMB TargetHandleList l_omiTargetList; @@ -160,22 +160,23 @@ errlHndl_t mmioSetup() // +-----+--------------------+------+-----------------------------------------+------+------- // Calculate CNFG space BAR to write to OCMB attribute - uint64_t l_currentOmiOffset = (( l_omiPosRelativeToMc / 2) * 8 * GIGABYTE) + + uint64_t l_omiOffsetRelativeToMc = (( l_omiPosRelativeToMc / 2) * 8 * GIGABYTE) + (( l_omiPosRelativeToMc % 2) * 2 * GIGABYTE); - // Calculated real address for this OMI is (BAR from MC attribute) + (currentOmiOffset) - uint64_t l_calulatedRealAddr = l_omiBaseAddr + l_currentOmiOffset; + // Calculate the MC mmio offset + the current OMI offset and this should match + // the ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET value set on the OMI target + uint64_t l_totalMmioOffset = l_mcBaseOffset + l_omiOffsetRelativeToMc; // Grab bar value from attribute to verify it matches // our calculations - auto l_omiBarAttrVal = l_omiTarget-> + auto l_omiOffsetAttrVal = l_omiTarget-> getAttr(); - if(l_omiBarAttrVal != l_calulatedRealAddr) + if(l_omiOffsetAttrVal != l_totalMmioOffset) { TRACFCOMP(g_trac_mmio, "Discrepancy found between calculated OMI MMIO bar offset and what we found in ATTR_OMI_INBAND_BAR_BASE_ADDR_OFFSET"); - TRACFCOMP(g_trac_mmio, "Calculated Offset: 0x%lX, Attribute Value : 0x%lX", l_calulatedRealAddr, l_omiBarAttrVal); + TRACFCOMP(g_trac_mmio, "Calculated Offset: 0x%lX, Attribute Value : 0x%lX", l_totalMmioOffset, l_omiOffsetAttrVal); /*@ * @errortype ERRORLOG::ERRL_SEV_UNRECOVERABLE @@ -191,8 +192,8 @@ errlHndl_t mmioSetup() ERRORLOG::ERRL_SEV_UNRECOVERABLE, MMIO::MOD_MMIO_SETUP, MMIO::RC_BAR_OFFSET_MISMATCH, - l_calulatedRealAddr, - l_omiBarAttrVal, + l_totalMmioOffset, + l_omiOffsetAttrVal, ERRORLOG::ErrlEntry::ADD_SW_CALLOUT); l_err->collectTrace( MMIO_COMP_NAME); ERRORLOG::ErrlUserDetailsTarget(l_omiTarget).addToLog(l_err); @@ -201,9 +202,9 @@ errlHndl_t mmioSetup() } - uint64_t l_currentOmiVirtAddr = l_virtAddr + l_currentOmiOffset; + uint64_t l_currentOmiVirtAddr = l_virtMcAddr + l_omiOffsetRelativeToMc; - // set VM_ADDR the associated OCMB + // set ATTR_MMIO_VM_ADDR and ATTR_MMIO_PHYS_ADDR the associated OCMB TargetHandleList l_ocmbTargetList; getChildAffinityTargets(l_ocmbTargetList, l_omiTarget, CLASS_CHIP, TYPE_OCMB_CHIP); @@ -215,10 +216,12 @@ errlHndl_t mmioSetup() " address is 0x%lX", get_huid(l_ocmbTargetList[0]), l_currentOmiVirtAddr, - l_calulatedRealAddr | MMIO_BASE ); + l_physMcAddr + l_omiOffsetRelativeToMc ); l_ocmbTargetList[0]-> setAttr(l_currentOmiVirtAddr); + l_ocmbTargetList[0]-> + setAttr(l_physMcAddr + l_omiOffsetRelativeToMc); } } } while(0); diff --git a/src/usr/runtime/populate_hbruntime.C b/src/usr/runtime/populate_hbruntime.C index 5ead63b3eef..bc1a60e5679 100644 --- a/src/usr/runtime/populate_hbruntime.C +++ b/src/usr/runtime/populate_hbruntime.C @@ -1107,21 +1107,6 @@ errlHndl_t populate_HbRsvMem(uint64_t i_nodeId, bool i_master_node) assert(l_sys != nullptr, "populate_HbRsvMem: top level target nullptr" ); - // Configure the ATTR_HBRT_HYP_ID attributes so that runtime code and - // whichever hypervisor is loaded can reference equivalent targets - // When populating hbRuntimeData, we make IPC calls if we are running - // on a multi-node configuration. The message handler for that IPC call, - // calls populateHbRsvMem. We want to setup hbrt target types for all - // the nodes. That's why, we moved this call here instead of directly - // calling it from istep21. - l_elog = RUNTIME::configureHbrtHypIds(TARGETING::is_phyp_load()); - if (l_elog) - { - TRACFCOMP(g_trac_runtime, ERR_MRK"populate_HbRsvMem> i_nodeId=%d" - " configureHbrtHypIds failed"); - break; - } - // Wipe out our cache of the NACA/SPIRA pointers RUNTIME::rediscover_hdat(); @@ -3483,19 +3468,6 @@ errlHndl_t populate_hbRuntimeData( void ) } else { - //When PAYLOAD_KIND = NONE (aka simics) - //Configure the ATTR_HBRT_HYP_ID attributes - //When PAYLOAD_KIND is set, we call this function from - //populate_HbRsvMem as that function is also executed on slave - //nodes in a multi-node config. But, moving it there removes - //this call in simics case. Therefore, adding it here. - l_elog = RUNTIME::configureHbrtHypIds(TARGETING::is_phyp_load()); - if (l_elog) - { - TRACFCOMP(g_trac_runtime, ERR_MRK"populate_HbRsvMem> i_nodeId=%d" - " configureHbrtHypIds failed"); - break; - } // still fill in HB DATA for testing uint64_t l_startAddr = cpu_spr_value(CPU_SPR_HRMOR) + VMM_HB_DATA_TOC_START_OFFSET; diff --git a/src/usr/targeting/common/hbrt_target.C b/src/usr/targeting/common/hbrt_target.C index b9197992211..801cacdd91e 100644 --- a/src/usr/targeting/common/hbrt_target.C +++ b/src/usr/targeting/common/hbrt_target.C @@ -22,6 +22,8 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +#include #include #include #include @@ -60,11 +62,10 @@ errlHndl_t getRtTarget( auto huid = get_huid(i_pTarget); auto targetingTargetType = i_pTarget->getAttr(); - TRACFCOMP(g_trac_targeting, ERR_MRK - "Targeting target type of 0x%08X not supported. " - "HUID: 0x%08X", - targetingTargetType, - huid); + TARG_ERR("getRtTarget: Targeting target type of 0x%08X not supported. " + "HUID: 0x%08X", + targetingTargetType, + huid); /*@ * @errortype * @moduleid TARG_RT_GET_RT_TARGET @@ -98,4 +99,57 @@ errlHndl_t getRtTarget( return pError; } +errlHndl_t getMemTargetMmioInfo ( TARGETING::Target * i_memTarget, + std::vector& o_ocmbMmioSpaces) +{ + errlHndl_t l_err; + + do{ + TARGETING::ocmbMmioAddressRange_t l_tmpRange; + TARGETING::ATTR_TYPE_type l_targetType = i_memTarget->getAttr(); + + assert(l_targetType == TARGETING::TYPE_OCMB_CHIP, + "Target type % passed to getMemTargetMmioInfo." + " Currently this function only supports TYPE_OCMB_CHIP", + l_targetType); + + // We need to store in a local variable initially because we cannot + // pass a ptr to the getRtTarget member of the packed ocmbMmioAddressRange_t struct + rtChipId_t l_hbrtId; + l_err = TARGETING::getRtTarget(i_memTarget, l_hbrtId); + if(l_err) + { + break; + } + l_tmpRange.hbrtId = l_hbrtId; + + TARGETING::ATTR_MMIO_PHYS_ADDR_type l_ocmbBaseMmioPhysAddr = + i_memTarget->getAttr(); + + assert(l_ocmbBaseMmioPhysAddr != 0, + "0 returned for physical address of OCMB's MMIO space. MMIO map probably isn't set up yet."); + + // CONFIG space ( 2 GB ) + l_tmpRange.mmioBaseAddr = l_ocmbBaseMmioPhysAddr; + l_tmpRange.mmioEndAddr = l_tmpRange.mmioBaseAddr + (2 * GIGABYTE) - 1; + l_tmpRange.accessSize = 4; + o_ocmbMmioSpaces.push_back(l_tmpRange); + + // Microchip Scom Access Space ( 128 MB ) + l_tmpRange.mmioBaseAddr = l_ocmbBaseMmioPhysAddr + (4 * GIGABYTE); + l_tmpRange.mmioEndAddr = l_tmpRange.mmioBaseAddr + (128 * MEGABYTE) - 1; + l_tmpRange.accessSize = 4; + o_ocmbMmioSpaces.push_back(l_tmpRange); + + // IBM Scom Access Space ( 16 MB ) + l_tmpRange.mmioBaseAddr = l_ocmbBaseMmioPhysAddr + (4 * GIGABYTE) + (128 * MEGABYTE); + l_tmpRange.mmioEndAddr = l_tmpRange.mmioBaseAddr + (16 * MEGABYTE) - 1; + l_tmpRange.accessSize = 8; + o_ocmbMmioSpaces.push_back(l_tmpRange); + + }while(0); + + return l_err; +} + } \ No newline at end of file diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml index 7d9af590421..0eb449bedf9 100755 --- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml @@ -935,6 +935,21 @@ + + MMIO_PHYS_ADDR + + Physical memory address this device has been mapped to. + + + + 0 + + + volatile-zeroed + + + + MMIO_VM_ADDR diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml index e2be5b6f851..d9bfb23688e 100644 --- a/src/usr/targeting/common/xmltohb/target_types_hb.xml +++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml @@ -92,6 +92,10 @@ IBSCOM_MUTEX + + 0 + MMIO_PHYS_ADDR + 0 MMIO_VM_ADDR diff --git a/src/usr/targeting/test/makefile b/src/usr/targeting/test/makefile index fa6fd0584e0..410bd3c1efd 100644 --- a/src/usr/targeting/test/makefile +++ b/src/usr/targeting/test/makefile @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2011,2019 +# Contributors Listed Below - COPYRIGHT 2011,2020 # [+] International Business Machines Corp. # # @@ -55,7 +55,10 @@ HWPF_REL_PATH = ${ROOTPATH}/src/include/usr/hwpf EXTRAINCDIR += \ $(addprefix ${HWPF_REL_PATH}/, ${HWPF_INC_DIRS}) \ ${ROOTPATH}/src/include/usr/ecmddatabuffer \ - ../ + ../ \ + ${ROOTPATH}/obj/genfiles/ \ + ${ROOTPATH}/src/import/hwpf/fapi2/include/ \ + ${ROOTPATH}/src/include/usr/fapi2/ # Generate the test suite diff --git a/src/usr/targeting/test/testtargeting.H b/src/usr/targeting/test/testtargeting.H index 5f49781df1e..db1c081404b 100644 --- a/src/usr/targeting/test/testtargeting.H +++ b/src/usr/targeting/test/testtargeting.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2019 */ +/* Contributors Listed Below - COPYRIGHT 2012,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,28 +39,35 @@ // STD #include #include +#include // CXXTEST #include +// System #include +#include #include #include #include +#include +#include // This component #include #include #include +#include #include #include #include #include #include #include -#include #include -#include + +// Generated +#include /** * @brief Struct to hold pointers to a mutex / protected value @@ -815,6 +822,395 @@ class TargetingTestSuite : public CxxTest::TestSuite TS_TRACE(EXIT_MRK "testI2cMux"); } + void testGetMemTargetMmioInfo(void) + { + uint32_t l_tests = 0; + uint32_t l_fails = 0; + TS_TRACE(ENTER_MRK "testGetMemTargetMmioInfo" ); + do + { + errlHndl_t l_errl = nullptr; + + // Get a reference to the target service + TARGETING::TargetService& l_targetService = TARGETING::targetService(); + + // Get the system target + TARGETING::Target* l_pSys = nullptr; + (void) l_targetService.getTopLevelTarget(l_pSys); + if (l_pSys == nullptr) + { + TS_FAIL("Top level target handle is NULL"); + break; + } + // Read the fabric mode (Chip is group OR Chip is node) + TARGETING::ATTR_PROC_FABRIC_PUMP_MODE_type l_fbcMode = + l_pSys->getAttr(); + + uint64_t l_procOffset = 0; + + if(l_fbcMode == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP) + { + l_procOffset = MMIO_OFFSET_PER_GROUP; + } + else + { + l_procOffset = MMIO_OFFSET_PER_CHIP; + } + + TARGETING::TargetHandleList l_ocmbTargetList; + TARGETING::getAllChips(l_ocmbTargetList, TARGETING::TYPE_OCMB_CHIP); + + // proc 0's ocmbs + const uint64_t OCMB0_RT_ID = 0x80000000; + const uint64_t OCMB0_MMIO_BAR = 0x30400000000 | MMIO_BASE; + const uint64_t OCMB8_RT_ID = 0x80000008; + const uint64_t OCMB8_MMIO_BAR = 0x30C00000000 | MMIO_BASE; + // proc 1's ocmbs + const uint64_t OCMB16_RT_ID = 0x80000010; + const uint64_t OCMB16_MMIO_BAR = 0x30400000000 | MMIO_BASE | l_procOffset; + const uint64_t OCMB24_RT_ID = 0x80000018; + const uint64_t OCMB24_MMIO_BAR = 0x30C00000000 | MMIO_BASE | l_procOffset; + + const uint64_t CONFIG_SPACE_SIZE = 2 * GIGABYTE; + const uint64_t SM_MMIO_SPACE_OFFSET = 4 * GIGABYTE; + const uint64_t SM_MMIO_SPACE_SIZE = 128 * MEGABYTE; + const uint64_t IBM_MMIO_SPACE_OFFSET = SM_MMIO_SPACE_OFFSET + SM_MMIO_SPACE_SIZE; + const uint64_t IBM_MMIO_SPACE_SIZE = 16 * MEGABYTE; + const uint8_t SUPPORTS_8_BYTE = 8; + const uint8_t SUPPORTS_4_BYTE = 4; + + const TARGETING::ocmbMmioAddressRange_t EXPECTED_VALUES[4][3] { + // OCMB 0 info + { + // Config Space + TARGETING::ocmbMmioAddressRange_t(OCMB0_RT_ID, + OCMB0_MMIO_BAR, + CONFIG_SPACE_SIZE + OCMB0_MMIO_BAR - 1, + SUPPORTS_4_BYTE), + // Super Micro MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB0_RT_ID, + OCMB0_MMIO_BAR + SM_MMIO_SPACE_OFFSET, + SM_MMIO_SPACE_SIZE + OCMB0_MMIO_BAR + SM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_4_BYTE), + // IBM MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB0_RT_ID, + OCMB0_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, + IBM_MMIO_SPACE_SIZE + OCMB0_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_8_BYTE) + }, + // OCMB 8 info + { + // Config Space + TARGETING::ocmbMmioAddressRange_t(OCMB8_RT_ID, + OCMB8_MMIO_BAR, + CONFIG_SPACE_SIZE + OCMB8_MMIO_BAR - 1, + SUPPORTS_4_BYTE), + // Super Micro MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB8_RT_ID, + OCMB8_MMIO_BAR + SM_MMIO_SPACE_OFFSET, + SM_MMIO_SPACE_SIZE + OCMB8_MMIO_BAR + SM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_4_BYTE), + // IBM MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB8_RT_ID, + OCMB8_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, + IBM_MMIO_SPACE_SIZE + OCMB8_MMIO_BAR + IBM_MMIO_SPACE_OFFSET -1, + SUPPORTS_8_BYTE) + }, + // OCMB 16 info + { + // Config Space + TARGETING::ocmbMmioAddressRange_t(OCMB16_RT_ID, + OCMB16_MMIO_BAR, + CONFIG_SPACE_SIZE + OCMB16_MMIO_BAR - 1, + SUPPORTS_4_BYTE), + // Super Micro MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB16_RT_ID, + OCMB16_MMIO_BAR + SM_MMIO_SPACE_OFFSET, + SM_MMIO_SPACE_SIZE + OCMB16_MMIO_BAR + SM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_4_BYTE), + // IBM MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB16_RT_ID, + OCMB16_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, + IBM_MMIO_SPACE_SIZE + OCMB16_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_8_BYTE) + }, + // OCMB 24 info + { + // Config Space + TARGETING::ocmbMmioAddressRange_t(OCMB24_RT_ID, + OCMB24_MMIO_BAR, + CONFIG_SPACE_SIZE + OCMB24_MMIO_BAR - 1, + SUPPORTS_4_BYTE), + // Super Micro MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB24_RT_ID, + OCMB24_MMIO_BAR + SM_MMIO_SPACE_OFFSET, + SM_MMIO_SPACE_SIZE + OCMB24_MMIO_BAR + SM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_4_BYTE), + // IBM MMIO Space + TARGETING::ocmbMmioAddressRange_t(OCMB24_RT_ID, + OCMB24_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, + IBM_MMIO_SPACE_SIZE + OCMB24_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + SUPPORTS_8_BYTE) + } + }; + + for (const auto & l_ocmb_target : l_ocmbTargetList) + { + TARGETING::ATTR_POSITION_type l_pos = l_ocmb_target->getAttr(); + // Only check first and last functional dimm for each proc + if( l_pos != 0 && l_pos != 8 && l_pos != 16 && l_pos != 24 ) + { + continue; + } + std::vector l_ranges; + l_errl = TARGETING::getMemTargetMmioInfo(l_ocmb_target, l_ranges); + + l_tests++; + if(l_errl) + { + TS_FAIL("testGetMemTargetMmioInfo an error occured while attempted to read mmio infor from target 0x%.08x", + TARGETING::get_huid(l_ocmb_target)); + delete l_errl; + l_errl = nullptr; + l_fails++; + // Skip this target + continue; + } + + l_tests++; + if(l_ranges.size() != 3) + { + TS_FAIL("testGetMemTargetMmioInfo OCMB with huid %.08X returned %d mmio ranges when 3 were expected", + TARGETING::get_huid(l_ocmb_target), l_ranges.size()); + l_fails++; + // Skip this target + continue; + } + + switch (l_pos) + { + case 0: + l_tests++; + if ( memcmp( &l_ranges[0], &EXPECTED_VALUES[0][0], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB0's CNFG space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[0][0].hbrtId, + EXPECTED_VALUES[0][0].mmioBaseAddr, + EXPECTED_VALUES[0][0].mmioEndAddr, + EXPECTED_VALUES[0][0].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[0].hbrtId, + l_ranges[0].mmioBaseAddr, + l_ranges[0].mmioEndAddr, + l_ranges[0].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[1], &EXPECTED_VALUES[0][1], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB0's Super Micro MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[0][1].hbrtId, + EXPECTED_VALUES[0][1].mmioBaseAddr, + EXPECTED_VALUES[0][1].mmioEndAddr, + EXPECTED_VALUES[0][1].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[1].hbrtId, + l_ranges[1].mmioBaseAddr, + l_ranges[1].mmioEndAddr, + l_ranges[1].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[2], &EXPECTED_VALUES[0][2], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB0's IBM MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[0][2].hbrtId, + EXPECTED_VALUES[0][2].mmioBaseAddr, + EXPECTED_VALUES[0][2].mmioEndAddr, + EXPECTED_VALUES[0][2].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[2].hbrtId, + l_ranges[2].mmioBaseAddr, + l_ranges[2].mmioEndAddr, + l_ranges[2].accessSize == 8 ? "true" : "false"); + } + break; + case 8: + l_tests++; + if ( memcmp( &l_ranges[0], &EXPECTED_VALUES[1][0], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB8's CNFG space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[1][0].hbrtId, + EXPECTED_VALUES[1][0].mmioBaseAddr, + EXPECTED_VALUES[1][0].mmioEndAddr, + EXPECTED_VALUES[1][0].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[0].hbrtId, + l_ranges[0].mmioBaseAddr, + l_ranges[0].mmioEndAddr, + l_ranges[0].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[1], &EXPECTED_VALUES[1][1], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB8's Super Micro MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[1][1].hbrtId, + EXPECTED_VALUES[1][1].mmioBaseAddr, + EXPECTED_VALUES[1][1].mmioEndAddr, + EXPECTED_VALUES[1][1].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[1].hbrtId, + l_ranges[1].mmioBaseAddr, + l_ranges[1].mmioEndAddr, + l_ranges[1].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[2], &EXPECTED_VALUES[1][2], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB8's IBM MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[1][2].hbrtId, + EXPECTED_VALUES[1][2].mmioBaseAddr, + EXPECTED_VALUES[1][2].mmioEndAddr, + EXPECTED_VALUES[1][2].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[2].hbrtId, + l_ranges[2].mmioBaseAddr, + l_ranges[2].mmioEndAddr, + l_ranges[2].accessSize == 8 ? "true" : "false"); + } + break; + case 16: + l_tests++; + if ( memcmp( &l_ranges[0], &EXPECTED_VALUES[2][0], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB16's CNFG space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[2][0].hbrtId, + EXPECTED_VALUES[2][0].mmioBaseAddr, + EXPECTED_VALUES[2][0].mmioEndAddr, + EXPECTED_VALUES[2][0].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[0].hbrtId, + l_ranges[0].mmioBaseAddr, + l_ranges[0].mmioEndAddr, + l_ranges[0].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[1], &EXPECTED_VALUES[2][1], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB16's Super Micro MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[2][1].hbrtId, + EXPECTED_VALUES[2][1].mmioBaseAddr, + EXPECTED_VALUES[2][1].mmioEndAddr, + EXPECTED_VALUES[2][1].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[1].hbrtId, + l_ranges[1].mmioBaseAddr, + l_ranges[1].mmioEndAddr, + l_ranges[1].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[2], &EXPECTED_VALUES[2][2], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB16's IBM MMIO space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[2][2].hbrtId, + EXPECTED_VALUES[2][2].mmioBaseAddr, + EXPECTED_VALUES[2][2].mmioEndAddr, + EXPECTED_VALUES[2][2].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[2].hbrtId, + l_ranges[2].mmioBaseAddr, + l_ranges[2].mmioEndAddr, + l_ranges[2].accessSize == 8 ? "true" : "false"); + } + break; + case 24: + l_tests++; + if ( memcmp( &l_ranges[0], &EXPECTED_VALUES[3][0], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB24's CNFG space info did not match what was expected"); + l_fails++; + TS_INFO("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[3][0].hbrtId, + EXPECTED_VALUES[3][0].mmioBaseAddr, + EXPECTED_VALUES[3][0].mmioEndAddr, + EXPECTED_VALUES[3][0].accessSize == 8 ? "true" : "false"); + TS_INFO("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[0].hbrtId, + l_ranges[0].mmioBaseAddr, + l_ranges[0].mmioEndAddr, + l_ranges[0].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[1], &EXPECTED_VALUES[3][1], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB24's Super Micro MMIO space info did not match what was expected"); + l_fails++; + TS_TRACE("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[3][1].hbrtId, + EXPECTED_VALUES[3][1].mmioBaseAddr, + EXPECTED_VALUES[3][1].mmioEndAddr, + EXPECTED_VALUES[3][1].accessSize == 8 ? "true" : "false"); + TS_TRACE("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[1].hbrtId, + l_ranges[1].mmioBaseAddr, + l_ranges[1].mmioEndAddr, + l_ranges[1].accessSize == 8 ? "true" : "false"); + } + l_tests++; + if ( memcmp( &l_ranges[2], &EXPECTED_VALUES[3][2], sizeof(TARGETING::ocmbMmioAddressRange_t )) != 0) + { + TS_FAIL("testGetMemTargetMmioInfo::" + "OCMB24's IBM MMIO space info did not match what was expected"); + l_fails++; + TS_TRACE("EXPECTED: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + EXPECTED_VALUES[3][2].hbrtId, + EXPECTED_VALUES[3][2].mmioBaseAddr, + EXPECTED_VALUES[3][2].mmioEndAddr, + EXPECTED_VALUES[3][2].accessSize == 8 ? "true" : "false"); + TS_TRACE("ACTUAL: id:0x%lx addr:0x%lx size:0x%lx 8byteAccess:%s ", + l_ranges[2].hbrtId, + l_ranges[2].mmioBaseAddr, + l_ranges[2].mmioEndAddr, + l_ranges[2].accessSize == 8 ? "true" : "false"); + } + break; + default: + TS_FAIL("testGetMemTargetMmioInfo::" + "We are processing a position we shouldn't be, investigation required."); + break; + } + } + }while(0); + TS_TRACE(EXIT_MRK "testGetMemTargetMmioInfo tests: %d fails: %d", l_tests, l_fails ); + } + }; #endif // End __TARGETING_TESTTARGETING_H