diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 37240256de3..b9585643519 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -27,9 +27,9 @@ /// @brief Establish safe settings for Core and Quad. /// // *HWP HWP Owner: Greg Still -// *HWP FW Owner: Sangeetha T S -// *HWP Team: PM -// *HWP Level: 2 +// *HWP FW Owner: Prasad BG Ranganath +// *HWP Team: PM +// *HWP Level: 3 // *HWP Consumed by: HS /// @verbatim @@ -44,11 +44,12 @@ /// loop over all valid chiplets (EX, EQ and Core) /// { /// Clear the Doorbells to remove latent values -/// Setup static Core PM mode register bits -/// Setup static Quad PM mode register bits +/// Set or clear static Core PM mode register bits +/// Set or clear static Quad PM mode register bits /// Setup CME SCRAM scrub index -/// Clear CME flags and scratch registers -/// Restore CME FIR mask value from HWP attribute +/// Clear CME flags and scratch registers as these will be setup +/// via CME booting during SGPE boot +/// Clear PPM Errors /// Restore PPM Error mask value from HWP attribute /// } /// } @@ -56,15 +57,23 @@ /// { /// loop over all valid chiplets (EX, EQ and Core) /// { -/// Save the CME FIR mask value to HWP attribute and clear the register -/// Save the PPM Error mask value to HWP attribute and clear the register -/// Stop the CME 0 & 1 +/// Save the QPPM Error mask value to HWP attribute and set mask per parm /// Disable OCC Heartbeat -/// Allow access to the PPM +/// Clear Quad PPM InterPPM Enablement to allow FFDC collection +/// If Quad GPMMR RESET_STATE_INDICATOR = 0 (which means the CME was +/// previously started) and CME is halted, flag cme_error_halt and log +/// it +/// for each good EX in Quad +/// Stop the CME 0 & 1 +/// Collect CME state (registers, global vars and PK trace) to PM HOMER +/// FFDC +/// if cme_error_halt, mark collected state as such +/// Collect CME LFIR to PM HOMER FFDC +/// for each core in EX +/// Save the CPPM Error mask value to HWP attribute and set mask per parm +/// Allow access to the CPPM /// Disable resonant clocks /// Disable IVRM -/// Clear PPM Errors -/// Clear CME FIRs /// } /// } /// @@ -75,6 +84,11 @@ // ----------------------------------------------------------------------------- #include #include +#include +#include +#include +#include +#include // ----------------------------------------------------------------------------- // Constant definitions @@ -126,6 +140,19 @@ fapi2::ReturnCode pm_corequad_init( // Function definitions // ---------------------------------------------------------------------- +/** + * @brief Returns the fully qualified address for a CME register + * @param[in] i_cmeid position of a CME + * @param[in] i_baseaddr base address for a CME register + * @return return the fully qualified address of a CME register + */ +uint64_t getCmeAddr(uint8_t i_cmeid, uint64_t i_baseaddr) +{ + return ( i_baseaddr | + ((i_cmeid / 2 ) << 24) | + ((i_cmeid % 2 ) << 10) ); +} + fapi2::ReturnCode p9_pm_corequad_init( const fapi2::Target& i_target, const p9pm::PM_FLOW_MODE i_mode, @@ -133,7 +160,7 @@ fapi2::ReturnCode p9_pm_corequad_init( const uint32_t i_cppmErrMask, const uint32_t i_qppmErrMask) { - FAPI_IMP("Entering p9_pm_corequad_init..."); + FAPI_DBG("> p9_pm_corequad_init..."); if (i_mode == p9pm::PM_INIT) { @@ -142,29 +169,32 @@ fapi2::ReturnCode p9_pm_corequad_init( } else if (i_mode == p9pm::PM_RESET) { - FAPI_TRY(pm_corequad_reset(i_target, i_cmeFirMask, i_cppmErrMask, + FAPI_TRY(pm_corequad_reset(i_target, + i_cmeFirMask, + i_cppmErrMask, i_qppmErrMask), "ERROR: Failed to reset core quad"); } else { FAPI_ASSERT(false, - fapi2::PM_COREQUAD_BAD_MODE().set_BADMODE(i_mode), + fapi2::PM_COREQUAD_BAD_MODE() + .set_BADMODE(i_mode), "Unknown mode 0x%X passed to p9_pm_corequad_init", i_mode); } fapi_try_exit: - FAPI_IMP("Exiting p9_pm_corequad_init..."); + FAPI_DBG("< p9_pm_corequad_init..."); return fapi2::current_err; } fapi2::ReturnCode pm_corequad_init( const fapi2::Target& i_target) { - FAPI_IMP("Entering pm_corequad_init..."); + FAPI_DBG(">> pm_corequad_init..."); fapi2::buffer l_data64; - uint8_t l_chpltNumber = 0; + uint64_t l_address = 0; uint32_t l_errMask = 0; @@ -178,9 +208,11 @@ fapi2::ReturnCode pm_corequad_init( { // Fetch the position of the EQ target - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_quad_chplt, + fapi2::ATTR_CHIP_UNIT_POS_Type l_chpltNumber = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_quad_chplt, l_chpltNumber), - "ERROR: Failed to get the position of the Quad:0x%08X", + "ERROR: Failed to get the position of the Quad 0x%08X", l_quad_chplt); FAPI_DBG("Quad number = %d", l_chpltNumber); @@ -193,19 +225,43 @@ fapi2::ReturnCode pm_corequad_init( // 14 : Enable PFETs upon iVRMs dropout // 18 - 19 : PCB interrupt // 20,22,24,26: InterPPM Ivrm/Aclk/Vdata/Dpll enable - FAPI_INF("Setup Quad PPM Mode register"); - l_data64.flush<0>().setBit<0, 15>().setBit<18, 3>(). - setBit<22>().setBit<24>().setBit<26>(); + FAPI_INF("Clear Quad PPM Mode register"); + + // *INDENT-OFF* + l_data64.flush<0>() + .setBit() + .setBit() + .setBit() + .setBit() + .setBit< EQ_QPPM_QPMMR_ENABLE_PFETS_UPON_IVRM_DROPOUT>() + .setBit< EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS>() + .setBit< EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT>() + .setBit< EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_LARGE_DROOP>() + .setBit< EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_EXTREME_DROOP>() + // @todo RTC 179958 IVRM enablement - only based on ATTR_SYSTEM_IVRM_DISABLE + // .setBit() + .setBit() + .setBit() + .setBit(); + // *INDENT-ON* + l_address = EQ_QPPM_QPMMR_CLEAR; FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to setup Quad PMM register"); + // Clear Quad PPM Errors + FAPI_INF("Clear QUAD PPM ERROR Register"); + l_data64.flush<0>(); + l_address = EQ_QPPM_ERR; + FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), + "ERROR: Failed to clear QUAD PPM ERROR"); + // Restore Quad PPM Error Mask - FAPI_INF("Restore QUAD PPM Error Mask"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_QUAD_PPM_ERRMASK, l_quad_chplt, l_errMask), "ERROR: Failed to get CORE PPM error Mask"); l_data64.flush<0>().insertFromRight<0, 32>(l_errMask); + FAPI_INF("Restore QUAD PPM Error Mask to 0%08X", l_errMask); l_address = EQ_QPPM_ERRMSK; FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to restore the QUAD PPM Error Mask"); @@ -218,9 +274,10 @@ fapi2::ReturnCode pm_corequad_init( for (auto l_core_chplt : l_coreChiplets) { // Fetch the position of the Core target - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_core_chplt, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_core_chplt, l_chpltNumber), - "ERROR: Failed to get the position of the CORE:0x%08X", + "ERROR: Failed to get the position of the Core 0x%08X", l_core_chplt); FAPI_DBG("CORE number = %d", l_chpltNumber); @@ -242,23 +299,41 @@ fapi2::ReturnCode pm_corequad_init( // 12 : PPM response for CME error // 14 : enable pece // 15 : cme spwu done dis - // Bits Init or Reset in STOP Hcode: + + // Other bits are Init or Reset by STOP Hcode and, thus, not touched + // here // 0 : PPM Write control // 9 : FUSED_CORE_MODE // 10 : STOP_EXIT_TYPE_SEL // 13 : WKUP_NOTIFY_SELECT - FAPI_INF("Setup Core PPM Mode register"); - l_data64.flush<0>().setBit<1>().setBit<11, 2>().setBit<14, 2>(); + + FAPI_INF("Clearing Core PPM Mode register ..."); + // *INDENT-OFF* + l_data64.flush<0>() + .setBit() + .setBit() + .setBit() + .setBit() + .setBit(); + // *INDENT-ON* l_address = C_CPPM_CPMMR_CLEAR; FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to setup Core PMM register"); + // Clear Core PPM Errors + l_data64.flush<0>(); + FAPI_INF("Clear CORE PPM ERROR Register"); + l_address = C_CPPM_ERR; + FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), + "ERROR: Failed to clear CORE PPM ERROR"); + // Restore CORE PPM Error Mask - FAPI_INF("Restore CORE PPM Error Mask"); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CORE_PPM_ERRMASK, l_core_chplt, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CORE_PPM_ERRMASK, + l_core_chplt, l_errMask), - "ERROR: Failed to get CORE PPM error Mask"); + "ERROR: Failed to get CORE P l_address = EX_PPE_XIXCR;PM error Mask"); l_data64.flush<0>().insertFromRight<0, 32>(l_errMask); + FAPI_INF("Restore CORE PPM Error Mask to 0%08X", l_errMask); l_address = C_CPPM_ERRMSK; FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to restore the CORE PPM Error Mask"); @@ -266,6 +341,7 @@ fapi2::ReturnCode pm_corequad_init( } fapi_try_exit: + FAPI_DBG("<< pm_corequad_init..."); return fapi2::current_err; } @@ -275,14 +351,14 @@ fapi2::ReturnCode pm_corequad_reset( const uint32_t i_cppmErrMask, const uint32_t i_qppmErrMask) { - FAPI_IMP("Entering pm_corequad_reset..."); + FAPI_DBG(">> pm_corequad_reset..."); fapi2::buffer l_data64; fapi2::ReturnCode l_rc; uint8_t l_chpltNumber = 0; uint64_t l_address = 0; uint32_t l_errMask = 0; - uint32_t l_pollCount = 20; + bool l_l2_is_scanable = false; bool l_l3_is_scanable = false; bool l_l2_is_scomable = false; @@ -297,57 +373,61 @@ fapi2::ReturnCode pm_corequad_reset( for (auto l_quad_chplt : l_eqChiplets) { // Fetch the position of the EQ target - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_quad_chplt, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_quad_chplt, l_chpltNumber), - "ERROR: Failed to get the position of the Quad:0x%08X", + "ERROR: Failed to get the position of the Quad 0x%08X", l_quad_chplt); FAPI_DBG("Quad number = %d", l_chpltNumber); // Store QUAD Error Mask in an attribute - FAPI_INF("Store QUAD PPM ERROR MASK in HWP attribute"); l_address = EQ_QPPM_ERRMSK; FAPI_TRY(fapi2::getScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to fetch the QUAD PPM Error Mask"); l_data64.extractToRight(l_errMask, 0, 32); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_QUAD_PPM_ERRMASK, l_quad_chplt, + FAPI_INF("Store QUAD PPM ERROR MASK in HWP attribute: 0x%016llX", + l_data64); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_QUAD_PPM_ERRMASK, + l_quad_chplt, l_errMask), "ERROR: Failed to set QUAD PPM error Mask"); - // Write parameter provided value to Quad Error mask - FAPI_INF("Write QUAD PPM ERROR MASK"); + // Write parameter provided value to Quad Error mask. This allows for + // the caller to provide a custom mask to be present which in reset l_data64.flush<0>().insertFromRight<0, 32>(i_qppmErrMask); + FAPI_INF("Write QUAD PPM ERROR MASK: 0x%016llX", l_data64); FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to write the QUAD PPM Error Mask"); // Disable OCC Heartbeat - // Clear the bit 16 : OCC_HEARTBEAT_ENABLE - FAPI_INF("Disable OCC HeartBeat register"); + FAPI_INF("Disable OCC HeartBeat"); l_address = EQ_QPPM_OCCHB; FAPI_TRY(fapi2::getScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to fetch OCC HeartBeat register"); - l_data64.clearBit<16>(); + l_data64.clearBit(); FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to disable OCC HeartBeat register"); - // Clear Quad PPM Errors - FAPI_INF("Clear QUAD PPM ERROR Register"); - l_address = EQ_QPPM_ERR; - FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), - "ERROR: Failed to clear QUAD PPM ERROR"); - // Insert the QPMMR operations to clear the inter-PPM enablement // bit to allow for access to those functions for FFDC access. // Remember, pm_init (reset) can be run without and subsequent // pm_init(init) when left in safe mode. FAPI_INF("Clear Quad PPM InterPPM Enablement for FFDC"); - l_data64.flush<0>().setBit<20>().setBit<22>().setBit<24>().setBit<26>(); + l_data64.flush<0>() + .setBit() + .setBit() + .setBit() + .setBit(); l_address = EQ_QPPM_QPMMR_CLEAR; FAPI_TRY(fapi2::putScom(l_quad_chplt, l_address, l_data64), "ERROR: Failed to setup Quad PMM register"); - //Cannot always rely on HWAS state, during MPIPL attr are not - //accurate, must use query_cache_access state prior to scomming - //ex targets + // @todo RTC 179967 PM FFDC HWP update + // Save the Quad Stop State History Reg to PM FFDC region + + // Cannot always rely on HWAS state, during MPIPL attr are not + // accurate, must use query_cache_access state prior to scomming + // EX targetsi_target FAPI_EXEC_HWP(l_rc, p9_query_cache_access_state, l_quad_chplt, l_l2_is_scomable, l_l2_is_scanable, l_l3_is_scomable, l_l3_is_scanable); @@ -367,48 +447,43 @@ fapi2::ReturnCode pm_corequad_reset( for (auto l_ex_chplt : l_exChiplets) { // Fetch the position of the EX target - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_ex_chplt, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, + l_ex_chplt, l_chpltNumber), "ERROR: Failed to get the position of the EX:0x%08X", l_ex_chplt); FAPI_DBG("EX number = %d", l_chpltNumber); - // Program XCR to HALT CME 0 & 1 and verify by polling the XSR - // Set the value of bits as follows: - // bits (1,2,3) = 001 : halt state - // - // NOTE: This will be removed once the PPE common class that does this - // functionality is available. - // Ex, ppe cme; - // cme.hard_reset(); - FAPI_INF("Stop CME0 and CME1"); - l_data64.flush<0>().insertFromRight(p9hcd::HALT, 1, 3); - l_address = EX_PPE_XIXCR; - FAPI_TRY(fapi2::putScom(l_ex_chplt, l_address, l_data64), - "ERROR: Failed to stop the CMEs"); - - do + // @todo RTC 179967 PM FFDC HWP update + // If CME is already halted, create error log and and mark the FFDC + // dump (below) as such. + + // Halt the CME + FAPI_INF("Halt CME %d", l_chpltNumber); + uint64_t cme_address = getCmeAddr(l_chpltNumber, CME0_BASE_ADDRESS); + l_rc = ppe_halt(i_target, cme_address); + + if (l_rc != fapi2::FAPI2_RC_SUCCESS) { - FAPI_INF("Polling the CME Status"); - l_address = EX_PPE_XIRAMDBG; - FAPI_TRY(fapi2::getScom(l_ex_chplt, l_address, l_data64), - "ERROR: Failed to read CME status"); - fapi2::delay(1000, 0); // poll after a delay of 1us + std::vector l_cmeBaseAddress; + l_cmeBaseAddress.push_back(cme_address); + + FAPI_ASSERT(false, + fapi2::PM_COREQUAD_CME_HALT_ERROR() + .set_PROC_CHIP_TARGET(i_target) + .set_EX_TARGET(l_ex_chplt) + .set_EQ_TARGET(l_quad_chplt) + .set_CME_BASE_ADDRESS(l_cmeBaseAddress) + .set_CME_STATE_MODE(HALT), + "CME Halt Timeout"); } - while((l_data64.getBit() != 1) && - (--l_pollCount != 0)); - FAPI_ASSERT((l_pollCount != 0), - fapi2::PM_CME_ACTIVE_ERROR() - .set_TARGET_CHIPLET(l_ex_chplt), - "ERROR: Failed to stop the CME"); + // @todo RTC 179967 PM FFDC HWP update + // Calls to dump CME state, CME global vars and CME PK trace goes + // here. - // Clear CME LFIRs - FAPI_INF("Clear CME FIR Register"); - l_data64.flush<0>(); - l_address = EX_CME_SCOM_LFIR_AND; - FAPI_TRY(fapi2::putScom(l_ex_chplt, l_address, l_data64), - "ERROR: Failed to clear CME FIR"); + // @todo RTC 179967 PM FFDC HWP update + // Save the CME LFIR to PM FFDC region auto l_coreChiplets = l_ex_chplt.getChildren @@ -425,35 +500,36 @@ fapi2::ReturnCode pm_corequad_reset( FAPI_DBG("CORE number = %d", l_chpltNumber); // Write CPPM Error mask into attribute - FAPI_INF("Store CORE PPM ERROR MASK in HWP attribute"); + l_address = C_CPPM_ERRMSK; FAPI_TRY(fapi2::getScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to fetch the CORE PPM Error Mask"); l_data64.extractToRight(l_errMask, 0, 32); + FAPI_INF("Store CORE PPM ERROR MASK in HWP attribute: 0x%016llX", + l_data64); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CORE_PPM_ERRMASK, l_core_chplt, l_errMask), "ERROR: Failed to set CORE PPM error Mask"); // Set parameter provided value to Core PPM ERROR MASK - FAPI_INF(" Write CORE PPM ERROR MASK "); l_data64.flush<0>().insertFromRight<0, 32>(i_cppmErrMask); + FAPI_INF("Write CORE PPM ERROR MASK: 0x%016llX", l_data64); FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to write to CORE PPM Error Mask"); // Allow PCB Access - // Set bit 0 : PPM_WRITE_DISABLE + // Set bit 0 : PPM_WRITE_DISABLE FAPI_INF("Allow PCB access to PPM"); - l_data64.flush<0>().setBit<0>(); + l_data64.flush<0>() + .setBit(); l_address = C_CPPM_CPMMR_CLEAR; FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), "ERROR: Failed to allow PCB access to PPM"); - // Clear Core PPM Errors - l_data64.flush<0>(); - FAPI_INF("Clear CORE PPM ERROR Register"); - l_address = C_CPPM_ERR; - FAPI_TRY(fapi2::putScom(l_core_chplt, l_address, l_data64), - "ERROR: Failed to clear CORE PPM ERROR"); + // @todo RTC 179967 PM FFDC HWP update + // Save the CPPM Error Reg to PM FFDC region + // Save the Core Stop State History Reg to PM FFDC region + } } } @@ -462,5 +538,6 @@ fapi2::ReturnCode pm_corequad_reset( //TODO: RTC 149079: Disable IVRM fapi_try_exit: + FAPI_DBG("<< pm_corequad_reset..."); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.H index 0d65c177743..a4e3a1159af 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016 */ +/* Contributors Listed Below - COPYRIGHT 2016,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -27,21 +27,19 @@ /// @brief Establish safe settings for Core and Quad. /// // *HWP HWP Owner: Greg Still -// *HWP FW Owner: Sangeetha T S -// *HWP Team: PM -// *HWP Level: 2 +// *HWP FW Owner: Prasad BG Ranganath +// *HWP Team: PM +// *HWP Level: 3 // *HWP Consumed by: HS -#ifndef _P9_COREQ_IN_H_ -#define _P9_COREQ_IN_H_ +#ifndef _P9_COREQUAD_INIT_H_ +#define _P9_COREQUAD_INIT_H_ // ----------------------------------------------------------------------------- // Includes // ----------------------------------------------------------------------------- #include #include -#include -#include // function pointer typedef definition for HWP call support typedef fapi2::ReturnCode (*p9_pm_corequad_init_FP_t) @@ -80,4 +78,4 @@ extern "C" const uint32_t i_qppmErrMask); } // extern "C" -#endif // _P9_COREQ_IN_H_ +#endif // _P9_COREQUAD_INIT_H_ diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.mk b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.mk index 7c74f51659e..6f8e2733de7 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.mk +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2016 +# Contributors Listed Below - COPYRIGHT 2016,2017 # [+] International Business Machines Corp. # # @@ -24,4 +24,5 @@ # IBM_PROLOG_END_TAG PROCEDURE=p9_pm_corequad_init $(call ADD_MODULE_SRCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/lib) +lib$(PROCEDURE)_DEPLIBS+=p9_ppe_utils $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_pm_corequad_init_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_pm_corequad_init_errors.xml index 863209d188a..f8ca035636c 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_pm_corequad_init_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_pm_corequad_init_errors.xml @@ -5,7 +5,7 @@ - + @@ -28,17 +28,35 @@ RC_PM_COREQUAD_BAD_MODE Unknown mode passed to p9_pm_corequad_init. BADMODE + + CODE + HIGH + - RC_PM_CME_ACTIVE_ERROR - The CME was not stopped during the reset of the cores quads - + RC_PM_COREQUAD_CME_HALT_ERROR + Failed to halt CME + PROC_CHIP_TARGET + EX_TARGET + EQ_TARGET + p9_eq_clear_atomic_lock, EQ_TARGET + p9_collect_ppe_state, PROC_CHIP_TARGET, CME_STATE_MODE, CME_BASE_ADDRESS CME_FFDC_REGISTERS - TARGET_CHIPLET + EX_TARGET TARGET_TYPE_EX + + EX_TARGET + HIGH + + + EX_TARGET + + + EX_TARGET +