From 93fcaa00fbf0c31bff0edc6b221170b13b74fcb1 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Tue, 26 Feb 2019 17:16:21 -0500 Subject: [PATCH] Adds explorer post-draminit bad bits processing Change-Id: I60a76365e95eab18a24075ac20a24fb2754c6b00 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72511 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: Louis Stermole Reviewed-by: ANDRE A. MARIN Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75612 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../procedures/hwp/memory/exp_draminit.C | 5 +- .../hwp/memory/lib/phy/exp_train_handler.C | 4 +- .../hwp/memory/lib/phy/exp_train_handler.H | 108 +++++++++++++++++- .../hwp/memory/lib/shared/exp_consts.H | 1 + .../xml/error_info/mss_exp_errors.xml | 14 ++- .../generic/memory/lib/utils/mss_bad_bits.H | 4 +- .../lib/utils/shared/mss_generic_consts.H | 2 +- 7 files changed, 125 insertions(+), 13 deletions(-) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C index 685ec22e7d4..78d941db21c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C @@ -33,9 +33,10 @@ // *HWP Level: 2 // *HWP Consumed by: FSP:HB -#include #include +#include #include +#include #include #include #include @@ -91,7 +92,7 @@ extern "C" // If not, then we need to process the bad bitmap if(l_rc != fapi2::FAPI2_RC_SUCCESS) { - mss::exp::bad_bit_interface l_interface; + mss::exp::bad_bit_interface l_interface(l_train_response); // Record bad bits should only fail if we have an attributes issue - that's a major issue FAPI_TRY(mss::record_bad_bits(i_target, l_interface)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C index 976812fc0d5..0418b59d1f4 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C @@ -42,7 +42,6 @@ #include #include - namespace mss { @@ -73,9 +72,12 @@ namespace check // TK update this when FIR's are fully reviewed template<> fapi2::ReturnCode bad_fir_bits( const fapi2::Target& i_target, + fapi2::ReturnCode& io_rc, bool& o_fir_error ) + { + io_rc = fapi2::FAPI2_RC_SUCCESS; o_fir_error = false; return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H index bb6bca47a0d..41c868946c0 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H @@ -61,31 +61,127 @@ fapi2::ReturnCode read_training_response(const fapi2::Target l_rank0; + fapi2::buffer l_rank1; + fapi2::buffer l_rank2; + fapi2::buffer l_rank3; + + // Process bit by bit for all ranks + // TK update to be the real bits + process_bit<0>(i_response.err_resp.Failure_Lane[l_bit_start], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<1>(i_response.err_resp.Failure_Lane[l_bit_start + 1], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<2>(i_response.err_resp.Failure_Lane[l_bit_start + 2], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<3>(i_response.err_resp.Failure_Lane[l_bit_start + 3], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<4>(i_response.err_resp.Failure_Lane[l_bit_start + 4], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<5>(i_response.err_resp.Failure_Lane[l_bit_start + 5], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<6>(i_response.err_resp.Failure_Lane[l_bit_start + 6], l_rank0, l_rank1, l_rank2, l_rank3); + process_bit<7>(i_response.err_resp.Failure_Lane[l_bit_start + 7], l_rank0, l_rank1, l_rank2, l_rank3); + + // Assign the results to the bad bits internal structure + // At this point, we want to assign all data + // We'll only copy real data over to the bad bit attribute IFF + iv_bad_bits[0][l_byte] = l_rank0; + iv_bad_bits[1][l_byte] = l_rank1; + iv_bad_bits[2][l_byte] = l_rank2; + iv_bad_bits[3][l_byte] = l_rank3; + } + } + + /// + /// @brief Processes a single bit from the response structure + /// @tparam B the bit position to process + /// @param[in] i_data the encoded data from the response structure + /// @param[in,out] io_rank0 rank 0's values + /// @param[in,out] io_rank1 rank 1's values + /// @param[in,out] io_rank2 rank 2's values + /// @param[in,out] io_rank3 rank 3's values + /// + template + void process_bit(const fapi2::buffer& i_data, + fapi2::buffer& io_rank0, + fapi2::buffer& io_rank1, + fapi2::buffer& io_rank2, + fapi2::buffer& io_rank3) + { + constexpr uint64_t RANK_LEN = 4; + constexpr uint64_t RANK0 = 12; + constexpr uint64_t RANK1 = 8; + constexpr uint64_t RANK2 = 4; + constexpr uint64_t RANK3 = 0; + + io_rank0.writeBit(i_data.getBit()); + io_rank1.writeBit(i_data.getBit()); + io_rank2.writeBit(i_data.getBit()); + io_rank3.writeBit(i_data.getBit()); + } + /// /// @param[in] i_target the DIMM to record training results on /// @param[out] o_bad_bits the processed bad bits - /// @return FAPI2_RC_SUCCESS if ok /// fapi2::ReturnCode record_bad_bits_interface( const fapi2::Target& i_target, uint8_t (&o_bad_dq)[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT]) const { + // Gets the rank offset for this DIMM + const uint64_t DIMM_OFFSET = mss::index(i_target) == 0 ? 0 : 2; + + // Loops through all of the ranks on this DIMM + uint8_t l_num_ranks = 0; + FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_num_ranks)); + + // TK Add in num ranks check here + // TK update for the ranks API + + for(uint64_t l_rank = 0; l_rank < l_num_ranks; ++l_rank) + { + const uint64_t RANK = DIMM_OFFSET + l_rank; + FAPI_ASSERT(RANK < mss::exp::MAX_RANK_PER_DIMM, + fapi2::MSS_EXP_DRAMINIT_BAD_NUM_RANKS() + .set_NUM_RANKS(RANK) + .set_MAX_RANKS(mss::exp::MAX_RANK_PER_DIMM) + .set_TARGET(i_target), + "%s bad number of ranks passed num:%u, max:%u", + mss::c_str(i_target), RANK, mss::exp::MAX_RANK_PER_DIMM); + + memcpy(&o_bad_dq[RANK], &iv_bad_bits[RANK], sizeof(uint8_t[BAD_DQ_BYTE_COUNT])); + } + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; } }; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index 3e514ff99de..c55d2d4d531 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -77,6 +77,7 @@ enum sizes { MAX_DIMM_PER_PORT = 2, MAX_RANK_PER_DIMM = 4, + MAX_BITS_PER_PORT = 80, }; /// diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml index 278d3790d44..d2b864abf58 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml @@ -5,7 +5,7 @@ - + @@ -24,6 +24,18 @@ + + RC_MSS_EXP_DRAMINIT_BAD_NUM_RANKS + Bad number of ranks were passed in the bad bits functionality + TARGET + NUM_RANKS + MAX_RANKS + + CODE + HIGH + + + RC_MSS_EXP_DRAMINIT_UNSUPPORTED_DIMM_TYPE Unsupported DIMM type encountered in draminit_training procedure diff --git a/src/import/generic/memory/lib/utils/mss_bad_bits.H b/src/import/generic/memory/lib/utils/mss_bad_bits.H index 84e62da5e4e..e6d2cdfa5aa 100644 --- a/src/import/generic/memory/lib/utils/mss_bad_bits.H +++ b/src/import/generic/memory/lib/utils/mss_bad_bits.H @@ -38,9 +38,9 @@ #include #include +#include #include #include -#include namespace mss { @@ -101,5 +101,5 @@ fapi_try_exit: return fapi2::current_err; } -} // ns +} // ns mss #endif diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 7a15bdfe079..bcf4f120791 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -355,6 +355,7 @@ enum class throttle_type THERMAL = 1, }; + /// /// @brief Trait classes for mc_type /// @tparam MC the mc_type @@ -399,7 +400,6 @@ struct mcTypeTraits }; }; - }// mss #endif