From be4329ca37507ac3dfc049d0ba9828e879683e69 Mon Sep 17 00:00:00 2001 From: Luke Mulkey Date: Wed, 4 Jan 2017 13:55:33 -0600 Subject: [PATCH] Edit ECID+Perv code to use new gen'd centaur scom headers RTC 163585 - Done Change-Id: I36c3476d07594382e70772eab050702c80992807 Original-Change-Id: I4fe900e3c1e919ff03158dd4cd02c268667dcbec Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34371 Dev-Ready: Brent Wieman Tested-by: Jenkins Server Reviewed-by: Brent Wieman Reviewed-by: Peng Fei Gou Reviewed-by: Benjamin Gass Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44950 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes --- .../include/cen_gen_scom_addresses_fixes.H | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H b/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H index 36a87141f31..4d9b572e3ea 100644 --- a/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H +++ b/src/import/chips/centaur/common/include/cen_gen_scom_addresses_fixes.H @@ -25,4 +25,37 @@ //Example: To fix an existing definiton //CEN_FIXREG32 (CEN_MBA_1_CCS_INST_ARR0_10, RULL(0x01234567)); +#include +#include +#ifndef CEN_GEN_SCOM_ADDRESSES_FIXES_H +#define CEN_GEN_SCOM_ADDRESSES_FIXES_H +REG64( CEN_WRITE_ALL_FUNC_GP3 , RULL(0x6B0F0012), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_WRITE_ALL_FUNC_GP3_AND , RULL(0x6B0F0013), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_WRITE_ALL_FUNC_GP3_OR , RULL(0x6B0F0014), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_WRITE_ALL_PCB_SLAVE_ERRREG , RULL(0x6B0F001F), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_PERV_LOCAL_FIR , RULL(0x0004000A), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( CEN_PERV_TP_LOCAL_FIR , RULL(0x0104000A), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( CEN_PERV_LOCAL_FIR_AND , RULL(0x0004000B), SH_UNT_PERV , SH_ACS_SCOM1_AND ); +REG64( CEN_PERV_TP_LOCAL_FIR_AND , RULL(0x0104000B), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( CEN_PERV_LOCAL_FIR_OR , RULL(0x0004000C), SH_UNT_PERV , SH_ACS_SCOM2_OR ); +REG64( CEN_PERV_TP_LOCAL_FIR_OR , RULL(0x0104000C), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); +REG64( CEN_PERV_LOCAL_FIR_MASK , RULL(0x0004000D), SH_UNT_PERV , SH_ACS_SCOM_RW ); +REG64( CEN_PERV_TP_LOCAL_FIR_MASK , RULL(0x0104000D), SH_UNT_PERV_1 , SH_ACS_SCOM_RW ); +REG64( CEN_PERV_LOCAL_FIR_MASK_AND , RULL(0x0004000E), SH_UNT_PERV , SH_ACS_SCOM1_AND ); +REG64( CEN_PERV_TP_LOCAL_FIR_MASK_AND , RULL(0x0104000E), SH_UNT_PERV_1 , SH_ACS_SCOM1_AND ); +REG64( CEN_PERV_LOCAL_FIR_MASK_OR , RULL(0x0004000F), SH_UNT_PERV , SH_ACS_SCOM2_OR ); +REG64( CEN_PERV_TP_LOCAL_FIR_MASK_OR , RULL(0x0104000F), SH_UNT_PERV_1 , SH_ACS_SCOM2_OR ); +REG64( CEN_GENERIC_GP1 , RULL(0x00000001), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_GP0_AND , RULL(0x00000004), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_GP0_OR , RULL(0x00000005), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_GP3_AND , RULL(0x000F0013), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_GP3_OR , RULL(0x000F0014), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_OPCG_CNTL0 , RULL(0x00030002), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_OPCG_CNTL2 , RULL(0x00030004), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_CLK_REGION , RULL(0x00030006), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_CLK_SCANSEL , RULL(0x00030007), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_CLK_STATUS , RULL(0x00030008), SH_UNT_PERV, SH_ACS_FSI ); +REG64( CEN_GENERIC_CLK_SCANDATA0 , RULL(0x00038000), SH_UNT_PERV, SH_ACS_FSI ); + +#endif