From c815997b70ee8d9e268cfee0a9ffcf76e2d8df92 Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Mon, 23 Mar 2020 08:50:10 -0500 Subject: [PATCH] Pass complete mmio address into runtime ocmb scom interface For OCMB register access, Hostboot will handle all of the strange address translation rather than pushing the logic into opal/phyp. Rather than passing through the local scom/register address, we will pass the system-wide MMIO address. Change-Id: I35139594db567be9a9adb898c4442b76f274e468 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/93844 Tested-by: Daniel M Crowell Reviewed-by: Daniel M Crowell Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R Geddes Reviewed-by: Matt Derksen Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E Bofferding --- src/usr/mmio/runtime/rt_mmio.C | 9 +++++++-- src/usr/targeting/common/hbrt_target.C | 9 ++++++--- src/usr/targeting/test/testtargeting.H | 12 +++++++----- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/usr/mmio/runtime/rt_mmio.C b/src/usr/mmio/runtime/rt_mmio.C index 620dff85568..be231807d95 100644 --- a/src/usr/mmio/runtime/rt_mmio.C +++ b/src/usr/mmio/runtime/rt_mmio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -72,9 +72,14 @@ errlHndl_t ocmbMmioPerformOp(DeviceFW::OperationType i_opType, // Verify offset is within scom mmio range if ( (l_offset >= (4 * GIGABYTE)) && (l_offset < (6 * GIGABYTE)) ) { + // add the base physical address to create a complete system-wide + // address + uint64_t l_fullAddr = i_ocmbTarget->getAttr(); + l_fullAddr += l_offset; + // send message to hypervisor level to do the mmio operation l_err = SCOM::sendScomToHyp(i_opType, i_ocmbTarget, - l_offset, io_buffer); + l_fullAddr, io_buffer); } else { diff --git a/src/usr/targeting/common/hbrt_target.C b/src/usr/targeting/common/hbrt_target.C index 801cacdd91e..61111d35390 100644 --- a/src/usr/targeting/common/hbrt_target.C +++ b/src/usr/targeting/common/hbrt_target.C @@ -136,14 +136,17 @@ errlHndl_t getMemTargetMmioInfo ( TARGETING::Target * i_memTarget, o_ocmbMmioSpaces.push_back(l_tmpRange); // Microchip Scom Access Space ( 128 MB ) + // Scom addresses 0x00000000..0x07FFFFFF, no shifting l_tmpRange.mmioBaseAddr = l_ocmbBaseMmioPhysAddr + (4 * GIGABYTE); l_tmpRange.mmioEndAddr = l_tmpRange.mmioBaseAddr + (128 * MEGABYTE) - 1; l_tmpRange.accessSize = 4; o_ocmbMmioSpaces.push_back(l_tmpRange); - // IBM Scom Access Space ( 16 MB ) + // IBM Scom Access Space ( Remainder ) + // Scom addresses 0x08000000..0x08FFFFFF, then shifted 3 bits left + // but we can just cheat and reserve the rest of the 4G..6G range l_tmpRange.mmioBaseAddr = l_ocmbBaseMmioPhysAddr + (4 * GIGABYTE) + (128 * MEGABYTE); - l_tmpRange.mmioEndAddr = l_tmpRange.mmioBaseAddr + (16 * MEGABYTE) - 1; + l_tmpRange.mmioEndAddr = l_ocmbBaseMmioPhysAddr + (6 * GIGABYTE) - 1; l_tmpRange.accessSize = 8; o_ocmbMmioSpaces.push_back(l_tmpRange); @@ -152,4 +155,4 @@ errlHndl_t getMemTargetMmioInfo ( TARGETING::Target * i_memTarget, return l_err; } -} \ No newline at end of file +} diff --git a/src/usr/targeting/test/testtargeting.H b/src/usr/targeting/test/testtargeting.H index db1c081404b..8b3dc8977a3 100644 --- a/src/usr/targeting/test/testtargeting.H +++ b/src/usr/targeting/test/testtargeting.H @@ -875,7 +875,9 @@ class TargetingTestSuite : public CxxTest::TestSuite const uint64_t SM_MMIO_SPACE_OFFSET = 4 * GIGABYTE; const uint64_t SM_MMIO_SPACE_SIZE = 128 * MEGABYTE; const uint64_t IBM_MMIO_SPACE_OFFSET = SM_MMIO_SPACE_OFFSET + SM_MMIO_SPACE_SIZE; - const uint64_t IBM_MMIO_SPACE_SIZE = 16 * MEGABYTE; + // Actual MMIO SPACE for IBM scoms is only 16 MB but we reserve + // remainder of the entire 2 GB window + const uint64_t IBM_MMIO_SPACE_RSV_SIZE = 2 * GIGABYTE - SM_MMIO_SPACE_SIZE; const uint8_t SUPPORTS_8_BYTE = 8; const uint8_t SUPPORTS_4_BYTE = 4; @@ -895,7 +897,7 @@ class TargetingTestSuite : public CxxTest::TestSuite // IBM MMIO Space TARGETING::ocmbMmioAddressRange_t(OCMB0_RT_ID, OCMB0_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, - IBM_MMIO_SPACE_SIZE + OCMB0_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + IBM_MMIO_SPACE_RSV_SIZE + OCMB0_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, SUPPORTS_8_BYTE) }, // OCMB 8 info @@ -913,7 +915,7 @@ class TargetingTestSuite : public CxxTest::TestSuite // IBM MMIO Space TARGETING::ocmbMmioAddressRange_t(OCMB8_RT_ID, OCMB8_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, - IBM_MMIO_SPACE_SIZE + OCMB8_MMIO_BAR + IBM_MMIO_SPACE_OFFSET -1, + IBM_MMIO_SPACE_RSV_SIZE + OCMB8_MMIO_BAR + IBM_MMIO_SPACE_OFFSET -1, SUPPORTS_8_BYTE) }, // OCMB 16 info @@ -931,7 +933,7 @@ class TargetingTestSuite : public CxxTest::TestSuite // IBM MMIO Space TARGETING::ocmbMmioAddressRange_t(OCMB16_RT_ID, OCMB16_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, - IBM_MMIO_SPACE_SIZE + OCMB16_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + IBM_MMIO_SPACE_RSV_SIZE + OCMB16_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, SUPPORTS_8_BYTE) }, // OCMB 24 info @@ -949,7 +951,7 @@ class TargetingTestSuite : public CxxTest::TestSuite // IBM MMIO Space TARGETING::ocmbMmioAddressRange_t(OCMB24_RT_ID, OCMB24_MMIO_BAR + IBM_MMIO_SPACE_OFFSET, - IBM_MMIO_SPACE_SIZE + OCMB24_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, + IBM_MMIO_SPACE_RSV_SIZE + OCMB24_MMIO_BAR + IBM_MMIO_SPACE_OFFSET - 1, SUPPORTS_8_BYTE) } };