From 13d024aaeadaaea9803d27029be5416305509162 Mon Sep 17 00:00:00 2001 From: Yue Du Date: Mon, 24 Oct 2016 10:59:37 -0500 Subject: [PATCH] Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup changes in this commit: 1) enable dpll lock checking in non-sim envrionment 2) change FAPI_DBG lines on set/reset sdis_n ops as removing prints saying they are DD1 only workaround due to they are permenant steps now 3) add missing content of p9_hcd_core_dcc_skewadjust 4) add DD2 sram_enable support (NOOP for DD1) Change-Id: I9a87c9fb68bd3b8df156ca07ba384e38cac85e94 Original-Change-Id: I74fc3b05781e7cd13bb8c95b0dc7389029d7c5af Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31719 Reviewed-by: Joseph E. Dery Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej Reviewed-by: CHRISTOPHER M. RIEDL Reviewed-by: Jennifer A. Stofer --- .../xml/attribute_info/chip_ec_attributes.xml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 4ce0125c3..dfdb2e763 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -182,6 +182,24 @@ + + ATTR_CHIP_EC_FEATURE_SDISN_SETUP + TARGET_TYPE_PROC_CHIP + + Sdis_n set or clear : flushing LCBES condition woraround. True if: + Nimbus EC less than 20 + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + ATTR_CHIP_EC_FEATURE_HW388878 TARGET_TYPE_PROC_CHIP