diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index fb982ccc4..6bdb7ddbe 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -31,11 +31,10 @@ - ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES + ATTR_CHIP_EC_FEATURE_P9_NO_NDL_IOVALID TARGET_TYPE_PROC_CHIP - Returns true if spy name has changed from dd1 to dd2. - Less than Nimbus ec 0x20 + Returns true if the chip has no NDL IOValid bits @@ -48,42 +47,6 @@ - - ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES - TARGET_TYPE_PROC_CHIP - - Returns true if spy name has changed from dd1 to dd2. - Greater than or equal to 0x20 - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - GREATER_THAN_OR_EQUAL - - - - - - - ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID - TARGET_TYPE_PROC_CHIP - - Returns true if the chip has NDL IOValid bits - P9N dd2 - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - GREATER_THAN_OR_EQUAL - - - - - ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX TARGET_TYPE_PROC_CHIP @@ -102,18 +65,18 @@ - ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE + ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE TARGET_TYPE_PROC_CHIP - Returns true if the core trace arrays are dumpable via SCOM. - Nimbus EC 0x20 or greater + Returns true if the core trace arrays are not dumpable via SCOM. + Nimbus EC 0x10 ENUM_ATTR_NAME_NIMBUS 0x20 - GREATER_THAN_OR_EQUAL + LESS_THAN @@ -1691,24 +1654,17 @@ - ATTR_CHIP_EC_FEATURE_NMMU_DMT_DD2 + ATTR_CHIP_EC_FEATURE_NMMU_NDD1 TARGET_TYPE_PROC_CHIP - Sets inits for DD2, also DMT mode + Configure NMMU for Nimbus DD1 ENUM_ATTR_NAME_NIMBUS 0x20 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL + LESS_THAN @@ -1749,24 +1705,18 @@ - ATTR_CHIP_EC_FEATURE_NMMU_ISS734_DD2_1 + ATTR_CHIP_EC_FEATURE_NMMU_NOT_ISS734 TARGET_TYPE_PROC_CHIP - issue734 dial, exists dd2.1+ + NMMU does not require application of issue734 fixes + Issue734 exists on Nimbus dd2.1+ ENUM_ATTR_NAME_NIMBUS 0x21 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL + LESS_THAN @@ -2002,7 +1952,7 @@ - ATTR_CHIP_EC_FEATURE_HW396230_SCAN_ONLY + ATTR_CHIP_EC_FEATURE_HW396230 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: set L3/NCU skip group scope via scan only @@ -2018,30 +1968,6 @@ - - ATTR_CHIP_EC_FEATURE_HW396230_SCOM - TARGET_TYPE_PROC_CHIP - - Nimbus DD2+: able to set L3/NCU skip group scope via SCOM - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL - - - - - ATTR_CHIP_EC_FEATURE_HW405880_LCO_IN_RETENTION TARGET_TYPE_PROC_CHIP @@ -2061,10 +1987,10 @@ - ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY + ATTR_CHIP_EC_FEATURE_HW386657 TARGET_TYPE_PROC_CHIP - Nimbus DD1 only: set the optimal dial setups for LCO's + Nimbus DD1 only: set the optimal dial setups for LCO's via scan @@ -2077,30 +2003,6 @@ - - ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCOM - TARGET_TYPE_PROC_CHIP - - Nimbus DD2+: set the optimal dial setups for LCO's - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL - - - - - ATTR_CHIP_EC_FEATURE_DISABLE_CP_ME TARGET_TYPE_PROC_CHIP @@ -2119,31 +2021,24 @@ - ATTR_CHIP_EC_FEATURE_OPTIMAL_LARX_STCX_PERF + ATTR_CHIP_EC_FEATURE_UNTUNED_LARX_STCX_PERF TARGET_TYPE_PROC_CHIP - Nimbus DD2+: set the optimal dial setups for larx/stcx + Nimbus DD1: Larx/stcx dials are non performance tuned ENUM_ATTR_NAME_NIMBUS 0x20 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL + LESS_THAN - ATTR_CHIP_EC_FEATURE_HW409069 + ATTR_CHIP_EC_FEATURE_NOT_HW409069 TARGET_TYPE_PROC_CHIP Nimbus DD2+: HW409069 load_larx protection not activated because of dtag_data_resp @@ -2154,14 +2049,7 @@ ENUM_ATTR_NAME_NIMBUS 0x20 - GREATER_THAN_OR_EQUAL - - - - ENUM_ATTR_NAME_CUMULUS - - 0x10 - GREATER_THAN_OR_EQUAL + LESS_THAN @@ -3148,6 +3036,113 @@ + + ATTR_CHIP_EC_FEATURE_HW391162 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: spoof pb_init in cache contained mode + Enables L2 checkers to monitor for transactions arbitrating + to broadcast onto the fabric + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_SCAN_SICR_TLBIE_QUIESCE + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: scan ON NCU_TLBIE_QUISCE fence + for non-cache contained modes. Flush state corrected in HW + for future revisions + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_CXA_P9NDD1_SPY_NAMES + TARGET_TYPE_PROC_CHIP + + Use Nimbus DD1 CXA spy register definition names + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_DDRPHY_P9NDD1_SPY_NAMES + TARGET_TYPE_PROC_CHIP + + Use Nimbus DD1 DDR PHY spy register definition names + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_MCA_P9NDD1_ASYNC + TARGET_TYPE_PROC_CHIP + + Program MCA ECC logic to support Nimbus DD1 + asynchronus boundary crossing requirements + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_CORE_P9NDD1 + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 core spy behavior qualifier + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + @@ -3524,7 +3519,7 @@ ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK TARGET_TYPE_PROC_CHIP - Only MC in Cumulus need to generate scan clock in even cycle instead of odd + Cumulus only: MC chiplet requires scan clock in even cycle instead of odd @@ -3541,7 +3536,7 @@ ATTR_CHIP_EC_FEATURE_HW406337 TARGET_TYPE_PROC_CHIP - Cumulus only dropping MC chiplet fence during arrayinit + Cumulus only: dropping MC chiplet fence during arrayinit @@ -3645,24 +3640,6 @@ - - ATTR_CHIP_EC_FEATURE_POSTDD1N_DPLL_SETTINGS - TARGET_TYPE_PROC_CHIP - - Post DD1 update : Used for new DD2 settings such as ..._EXTERNAL_JUMP_VALUES latch is new for DD2. True if: - Nimbus EC greater than or equal to 20 - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - GREATER_THAN_OR_EQUAL - - - - - ATTR_CHIP_EC_FEATURE_INT_DD1 TARGET_TYPE_PROC_CHIP