diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
index 583a34fcc..9fe395dfa 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C
@@ -378,6 +378,13 @@ fapi2::ReturnCode p9_sbe_select_ex(
         FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX  EX 0x%016llX",
                  l_core_config, l_quad_config);
 
+        // Prior to writing to PFET_DELAY register, ensure that the PPM write disable
+        // bit on the Core Power Management Mode Register is cleared
+        FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", l_core_num);
+        l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>();
+
+        FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64));
+
         // Write the default PFET Controller Delay values for the Core
         // as it will be used for istep 4
         FAPI_DBG("Setting PFET Delays in core %d", l_core_num);
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H
index 15efd37ca..7a09e03c8 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H
@@ -46,6 +46,7 @@
 #include <p9_quad_scom_addresses.H>
 #include <p9_perv_scom_addresses.H>
 #include <p9n2_perv_scom_addresses_fld.H>
+#include <p9_quad_scom_addresses_fld.H>
 
 namespace p9selectex
 {