From 35f762935b3f898e6cca58431a12ecf49ffd9a2f Mon Sep 17 00:00:00 2001 From: crgeddes Date: Thu, 17 Aug 2017 15:40:12 -0500 Subject: [PATCH] Clear disable_ppm_writes bit on CPPM register prior to setting PFDLY We were hitting problems in the MPIPL path where this bit was set causing scom writes to the PFDLY register to fail CQ: SW398564 Change-Id: Idd13cb3b8fe2ba90fceb37c330f06adcf11a44ad Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44759 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: YUE DU Reviewed-by: Gregory S. Still Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44774 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C | 7 +++++++ src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H | 1 + 2 files changed, 8 insertions(+) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C index 583a34fcc..9fe395dfa 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -378,6 +378,13 @@ fapi2::ReturnCode p9_sbe_select_ex( FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX EX 0x%016llX", l_core_config, l_quad_config); + // Prior to writing to PFET_DELAY register, ensure that the PPM write disable + // bit on the Core Power Management Mode Register is cleared + FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", l_core_num); + l_data64.flush<0>().setBit(); + + FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64)); + // Write the default PFET Controller Delay values for the Core // as it will be used for istep 4 FAPI_DBG("Setting PFET Delays in core %d", l_core_num); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H index 15efd37ca..7a09e03c8 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.H @@ -46,6 +46,7 @@ #include #include #include +#include namespace p9selectex {