From 72a62b5a72b0cb7acedc818f05a7023f461687c6 Mon Sep 17 00:00:00 2001 From: Mark Pizzutillo Date: Mon, 15 Apr 2019 16:08:22 -0400 Subject: [PATCH] Add PMIC enable procedure code and UTs Change-Id: I46ab8808d535acba4f88926f25e66c5b276bef2b Original-Change-Id: Iac5cd8016efa705be6512b842e0e793eb3d4c5fa Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/74639 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: HWSV CI Reviewed-by: Louis Stermole Reviewed-by: STEPHEN GLANCY Reviewed-by: Thi N. Tran --- src/import/generic/memory/lib/utils/shared/mss_generic_consts.H | 1 + 1 file changed, 1 insertion(+) diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index ae9e5f5bb..68d46b024 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -180,6 +180,7 @@ enum generic_ffdc_codes SET_DIMM_RANKS_CNFG = 0x1039, DDIMM_RAWCARD_DECODE = 0x103a, INIT_RANK_INFO = 0x103B, + BIAS_PMIC_FROM_SPD = 0x103C, SET_DRAM_WIDTH = 0x1040, SET_SI_VREF_DRAM_WR = 0x1041,