From 8e1da2df553644f5f6fb5c6131c1f00a6ddccade Mon Sep 17 00:00:00 2001
From: Stephen Glancy <sglancy@us.ibm.com>
Date: Thu, 20 Apr 2017 14:54:26 -0500
Subject: [PATCH] Added DQS alignment workaround

Change-Id: I2f04a7a14a4b9b2f1a740e89a4921f98f11c585b
Original-Change-Id: Id03b903b964ae088bd427e333d4620a3412ea23c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39508
Dev-Ready: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
---
 .../xml/attribute_info/chip_ec_attributes.xml | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index ce2453c26..ccd2e5289 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -2850,6 +2850,25 @@
     </chipEcFeature>
   </attribute>
 
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_MSS_RUN_DQS_LOOP</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+        In DD1.** Nimbus, if we get a DQS fail from DQS_ALIGN in draminit_training,
+        we rerun DQS_ALIGN for the failing bit for a set number of times or until it passed
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
+
   <attribute>
     <id>ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE</id>
     <targetType>TARGET_TYPE_PROC_CHIP</targetType>