From 9dc8b5aa9b5f9f159a0b1dd460af3f7670b270dd Mon Sep 17 00:00:00 2001
From: Joe McGill <jmcgill@us.ibm.com>
Date: Fri, 20 Jan 2017 18:27:15 -0600
Subject: [PATCH] p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulse

Change-Id: I11c9c68ed140ab8593a1a6eee54c9dd3ee2464d3
Original-Change-Id: I838703170232b7ad39ae752f0fcde996f5bd577e
CQ: HW401184
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35199
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
---
 .../xml/attribute_info/chip_ec_attributes.xml   | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index b0a884717..b484c15b6 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -1867,6 +1867,23 @@
       </chip>
     </chipEcFeature>
   </attribute>
+  <!-- ******************************************************************** -->
+  <attribute>
+    <id>ATTR_CHIP_EC_FEATURE_HW401184</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>
+      Nimbus DD1: Silent Baron: TB and DEC SPRs stray apart with TOD enabled
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_NIMBUS</name>
+        <ec>
+          <value>0x20</value>
+          <test>LESS_THAN</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
 
   <!-- ******************************************************************** -->
   <!-- Memory Section                                                       -->