From bce2afea3ded558f567b11cc360460030e6e9ac8 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Wed, 22 Feb 2017 20:52:23 -0600 Subject: [PATCH] adjust SRAM timings Change-Id: Ic3e5e66c9076c021d023f1bc5d745e761a413ec6 Original-Change-Id: Iae2a281eeebe46f316dc4c7d23e869f103b88abb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36892 Reviewed-by: Kevin F. Reick Reviewed-by: ALEXANDER M. TAFT Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran Reviewed-by: Joseph J. McGill --- .../xml/attribute_info/chip_ec_attributes.xml | 21 ++----------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index c9d49a4de..28295d639 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -1184,10 +1184,10 @@ - ATTR_CHIP_EC_FEATURE_L3_SRAM_RELAXED_SETTINGS + ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS TARGET_TYPE_PROC_CHIP - Nimbus DD1 only: SRAM relaced settings + Nimbus DD1 only: adjust/relax SRAM timing parameters @@ -1322,23 +1322,6 @@ - - ATTR_CHIP_EC_FEATURE_L2_DUMMY_PULSE_POK_BITS - TARGET_TYPE_PROC_CHIP - - DD1 only: CAY_L2C_A102_MAC dummy pulse pok bits - - - - ENUM_ATTR_NAME_NIMBUS - - 0x20 - LESS_THAN - - - - - ATTR_CHIP_EC_FEATURE_HW374111 TARGET_TYPE_PROC_CHIP