diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
index 9a43337b9..ddb7009fe 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml
@@ -71,7 +71,7 @@
TARGET_TYPE_PROC_CHIP
Returns true if the chip has NDL IOValid bits
- P9N dd2
+ P9N dd2
@@ -162,7 +162,7 @@
-
+
ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE
TARGET_TYPE_PROC_CHIP
@@ -257,7 +257,7 @@
TARGET_TYPE_PROC_CHIP
Filter pll setting differences.
- Cumulus matches nimbus dd2.
+ Cumulus matches nimbus dd2.
@@ -345,7 +345,7 @@
ATTR_CHIP_EC_FEATURE_HW405413
TARGET_TYPE_PROC_CHIP
- HW405413 : NCU sends data out of order
+ HW405413 : NCU sends data out of order
@@ -1363,7 +1363,7 @@
ATTR_CHIP_EC_FEATURE_HW377094
TARGET_TYPE_PROC_CHIP
- DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU
+ DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU
while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override.
@@ -2459,7 +2459,7 @@
ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR
TARGET_TYPE_PROC_CHIP
- DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
+ DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers
@@ -2737,7 +2737,7 @@
- ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND
+ ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND
TARGET_TYPE_PROC_CHIP
In below DD2 Nimbus, a workaround after read centering might need to be run.
@@ -2897,7 +2897,7 @@
ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL
TARGET_TYPE_PROC_CHIP
- For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL
+ For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL