From d372aa8418c3f0dde8c2ca610ffc85424cb79e70 Mon Sep 17 00:00:00 2001 From: Lennard Streat Date: Mon, 21 Aug 2017 10:47:29 -0500 Subject: [PATCH] Expanding MCU tag fifo settings to be freq dependent. Change-Id: I0b4b7b61a7fa4920c7bd1152cb33a25789a2fd60 Original-Change-Id: I46baeb1bb6f076c132e735724b094ee8a99e9257 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44917 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Reviewed-by: SHELTON LEUNG Reviewed-by: Joseph J. McGill Reviewed-by: Matt K. Light Reviewed-by: Daniel M. Crowell Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46974 Reviewed-by: Sachin Gupta --- .../xml/attribute_info/nest_attributes.xml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 4e2a28b82..15cabe12a 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -46,6 +46,27 @@ freq_pb_mhz + + ATTR_FREQ_MCA_MHZ + TARGET_TYPE_SYSTEM + + The frequency of the memory controller channel. In synchronous mode, + this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set + per pair of memory channels if operating in asynchronous mode, + but this configuration is not anticipated. This clock drives the MCU queues, + and all the associated logic that drives the inputs to the DMI and reads + its outputs. + + uint32 + + 2000 = 2000, + 2400 = 2400 + + + + freq_mca_mhz + + ATTR_FREQ_O_MHZ TARGET_TYPE_PROC_CHIP