From e15c80ad9743e5d5d9d6da585f0c598d00832930 Mon Sep 17 00:00:00 2001 From: Thi Tran Date: Fri, 20 Oct 2017 14:28:00 -0500 Subject: [PATCH] Need to clear OCB3 errors before a PBA operation Change-Id: Iaa7246b82bc490222162ef74011db78bc8631e23 CQ:SW405593 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48647 Tested-by: FSP CI Jenkins Reviewed-by: Joseph J. McGill Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Benjamin Gass Reviewed-by: Thi N. Tran Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48649 Reviewed-by: Hostboot Team Reviewed-by: Sachin Gupta --- .../chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C index 6e3221135..ce44b0900 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C @@ -199,11 +199,14 @@ extern "C" //Write the OCB3 Status Control Register //Configure linear stream mode (auto-increment +8 with each data register read/write) - //set bit 4 and unset bit 5 of OCB3 Status Control Register - ocb_status_ctl_data.flush<0>().setBit<5>(); + // Set bits 0:1 to clear PULL_READ_UNDERFLOW and PUSH_WRITE_OVERFLOW + // Set bit 5 to clear stream type (enables linear mode) + // Set bits 6:15 to clear other errors + ocb_status_ctl_data.flush<0>().setBit<0, 2>().setBit<5, 11>(); FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_CLEAR, ocb_status_ctl_data), "Error writing to the OCB3 Status Control Register with and mask"); + // Set bit 4 to enable stream mode ocb_status_ctl_data.flush<0>().setBit<4>(); FAPI_TRY(fapi2::putScom(i_target, PU_OCB_PIB_OCBCSR3_OR, ocb_status_ctl_data),