From 83a92e3b409a732b2e89f651d0bc14a642615dc8 Mon Sep 17 00:00:00 2001 From: Oliver O'Halloran Date: Tue, 5 Nov 2019 18:43:53 +1100 Subject: [PATCH] platforms/qemu: Add slot table entries for a PCIe switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a more complex slot table example to the Qemu platform. A more complex PCIe topology in qemu is useful for testing and it's simple enough to serve as an good example of how to use the slot table construction macros. Test in Qemu with: ./qemu-system-ppc64 -machine powernv -nographic -m 2G \ -bios ./skiboot.lid -kernel ./vmlinux -initrd ./petitfs \ -device x3130-upstream,id=sw0_up,bus=pcie.2 \ -device xio3130-downstream,id=sw0_down0,chassis=1,slot=0,bus=sw0_up,addr=0 \ -drive file=./disk1.img,format=raw,if=none,id=nvme1 \ -device nvme,drive=nvme1,bus=sw0_down0,serial=1 \ -device xio3130-downstream,id=sw0_down1,chassis=1,slot=1,bus=sw0_up,addr=1 \ -device xio3130-downstream,id=sw0_down2,chassis=1,slot=2,bus=sw0_up,addr=2 \ -device e1000e,bus=sw0_down2 Results in: PHB#0002:00:00.0 [ROOT] 1014 04c1 R:00 C:060400 B:01..05 SLOT=pcie.2 PHB#0002:01:00.0 [SWUP] 104c 8232 R:02 C:060400 B:02..05 SLOT=sw0_up PHB#0002:02:00.0 [SWDN] 104c 8233 R:01 C:060400 B:03..03 SLOT=sw0_down0 PHB#0002:03:00.0 [EP ] 8086 5845 R:02 C:010802 ( mass-storage) LOC_CODE=sw0_down0 PHB#0002:02:01.0 [SWDN] 104c 8233 R:01 C:060400 B:04..04 SLOT=sw0_down1 PHB#0002:02:02.0 [SWDN] 104c 8233 R:01 C:060400 B:05..05 SLOT=sw0_down2 PHB#0002:05:00.0 [EP ] 8086 10d3 R:00 C:020000 ( ethernet) LOC_CODE=sw0_down2 Reviewed-by: Cédric Le Goater Signed-off-by: Oliver O'Halloran --- platforms/qemu/qemu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/platforms/qemu/qemu.c b/platforms/qemu/qemu.c index c73bf255f9b4..e4e7c1815996 100644 --- a/platforms/qemu/qemu.c +++ b/platforms/qemu/qemu.c @@ -12,7 +12,16 @@ static bool bt_device_present; ST_PLUGGABLE(qemu_slot0, "pcie.0"); ST_PLUGGABLE(qemu_slot1, "pcie.1"); -ST_PLUGGABLE(qemu_slot2, "pcie.2"); + +static const struct slot_table_entry qemu_sw_down[] = { + SW_PLUGGABLE("sw0_down0", 0x0), + SW_BUILTIN ("sw0_down1", 0x1), + SW_PLUGGABLE("sw0_down2", 0x2), + { .etype = st_end }, +}; +ST_BUILTIN_DEV(qemu_sw_up, "sw0_up", .children = qemu_sw_down); +ST_BUILTIN_DEV(qemu_sw_root, "pcie.2", .children = qemu_sw_up); + ST_PLUGGABLE(qemu_slot3, "pcie.3"); ST_PLUGGABLE(qemu_slot4, "pcie.4"); ST_PLUGGABLE(qemu_slot5, "pcie.5"); @@ -20,7 +29,7 @@ ST_PLUGGABLE(qemu_slot5, "pcie.5"); static const struct slot_table_entry qemu_phb_table[] = { ST_PHB_ENTRY(0, 0, qemu_slot0), ST_PHB_ENTRY(0, 1, qemu_slot1), - ST_PHB_ENTRY(0, 2, qemu_slot2), + ST_PHB_ENTRY(0, 2, qemu_sw_root), ST_PHB_ENTRY(0, 3, qemu_slot3), ST_PHB_ENTRY(0, 4, qemu_slot4), ST_PHB_ENTRY(0, 5, qemu_slot5),