diff --git a/hw/phb4.c b/hw/phb4.c
index 3c71427aef2f..f02e675f0a02 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -5738,6 +5738,7 @@ static void phb4_create(struct dt_node *np)
 	xive_register_hw_source(p->base_msi, p->num_irqs - 8, 16,
 				p->int_mmio, irq_flags, NULL, NULL);
 
+	/* XIVE_SRC_SHIFT_BUG is a DD1 workaround */
 	xive_register_hw_source(p->base_lsi, 8, 16,
 				p->int_mmio + ((p->num_irqs - 8) << 16),
 				XIVE_SRC_LSI | XIVE_SRC_SHIFT_BUG,
diff --git a/hw/xive.c b/hw/xive.c
index 4a2b0df7b042..84c1c107f253 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -2219,9 +2219,6 @@ static void xive_update_irq_mask(struct xive_src *s, uint32_t idx, bool masked)
 	else
 		offset = 0xc00; /* PQ = 00 */
 
-	if (s->flags & XIVE_SRC_SHIFT_BUG)
-		offset <<= 4;
-
 	in_be64(mmio_base + offset);
 }
 
@@ -2404,8 +2401,6 @@ static void __xive_source_eoi(struct irq_source *is, uint32_t isn)
 			in_be64(mmio_base);
 		else {
 			offset = 0xc00;
-			if (s->flags & XIVE_SRC_SHIFT_BUG)
-				offset <<= 4;
 			eoi_val = in_be64(mmio_base + offset);
 			xive_vdbg(s->xive, "ISN: %08x EOI=%llx\n",
 				  isn, eoi_val);
@@ -3602,8 +3597,6 @@ static uint64_t xive_convert_irq_flags(uint64_t iflags)
 
 	if (iflags & XIVE_SRC_LSI)
 		oflags |= OPAL_XIVE_IRQ_LSI;
-	if (iflags & XIVE_SRC_SHIFT_BUG)
-		oflags |= OPAL_XIVE_IRQ_SHIFT_BUG;
 	return oflags;
 }
 
diff --git a/include/opal-api.h b/include/opal-api.h
index e7156f36a756..dd74e662cd95 100644
--- a/include/opal-api.h
+++ b/include/opal-api.h
@@ -1148,7 +1148,7 @@ enum {
 	OPAL_XIVE_IRQ_TRIGGER_PAGE	= 0x00000001,
 	OPAL_XIVE_IRQ_STORE_EOI		= 0x00000002,
 	OPAL_XIVE_IRQ_LSI		= 0x00000004,
-	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008,
+	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008, /* DD1.0 workaround */
 	OPAL_XIVE_IRQ_MASK_VIA_FW	= 0x00000010, /* DD1.0 workaround */
 	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020, /* DD1.0 workaround */
 };
diff --git a/include/xive.h b/include/xive.h
index 224d65837f53..5706d275ae47 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -41,7 +41,7 @@ uint32_t xive_get_notify_base(uint32_t girq);
 #define XIVE_SRC_EOI_PAGE1	0x02 /* EOI on the second page */
 #define XIVE_SRC_STORE_EOI	0x04 /* EOI using stores supported */
 #define XIVE_SRC_LSI		0x08 /* Interrupt is an LSI */
-#define XIVE_SRC_SHIFT_BUG	0x10 /* ESB update offset << 4 */
+#define XIVE_SRC_SHIFT_BUG	0x10 /* ESB update offset << 4 (PHB4 LSI DD1) */
 
 struct irq_source_ops;
 void xive_register_hw_source(uint32_t base, uint32_t count, uint32_t shift,