OPL4 initial register values and masks

[grauw]

FM1
 
  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
0 FF FF 00 00 00 FF FF FF 00 FF FF FF FF FF FF FF
1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
2 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
3 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
4 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
5 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
6 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
7 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
8 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
9 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
A 00 00 00 00 00 00 00 00 00 00 00 FF FF FF FF FF
B 00 00 00 00 00 00 00 00 00 00 00 3F 3F 00 3F 3F
C 30 30 30 30 30 30 30 30 30 30 30 FF F1 F1 F1 FF
D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E 00 00 00 00 00 00 07 07 00 00 00 00 00 00 07 07
F 00 00 00 00 00 00 07 07 07 07 07 07 07 07 07 07
 
FM2
 
  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
0 FF FF FF FF 00 00 FF FF FF FF FF FF FF FF FF FF
1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
2 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
3 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
4 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
5 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
6 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
7 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
8 00 00 00 00 00 00 FF FF 00 00 00 00 00 00 FF FF
9 00 00 00 00 00 00 FF FF FF FF FF FF FF FF FF FF
A 00 00 00 00 00 00 00 00 00 00 00 FF FF FF FF FF
B 00 00 00 00 00 00 00 00 00 00 00 3F 3F FF 3F 3F
C 30 30 30 30 30 30 30 30 30 30 30 FF F1 F1 F1 FF
D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
E 00 00 00 00 00 00 07 07 00 00 00 00 00 00 07 07
F 00 00 00 00 00 00 07 07 07 07 07 07 07 07 07 07
 
WAVE
 
  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
0 FF FF 20 00 00 00 FF FF 00 00 00 00 00 00 00 00
1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
D 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
F 00 00 00 00 00 00 00 00 1B 00 FF FF FF FF FF FF

Notes:

1. OpenMSX returns 00H from unused registers
2. Obviously I can’t read the initial value of FM2 register 5, so I wrote down 00H (since if those bits were 1 initially FM2 and WAVE would be enabled)
3. Writing FFH to FM2 register 5 reads back 03H, so unused bits stay 0
4. Writing FFH to FM2 register CCH reads back FFH, and none of C0H-C8H change (hidden feature?)
5. Writing FFH to FM2 register B9H reads back 3FH, and changes B7H to 3FH as well. Ditto for BAH (+B8H)
6. Writing FFH to FM2 register BBH reads back 3FH, writing 00H ditto

10 SCREEN 0 : WIDTH 64 : KEY OFF : POKE &HF3B1,26 : VDP(10) = VDP(10) OR 128
20 FOR I=0 to 255 : OUT &HC4,I : PRINT RIGHT$("0" + HEX$(INP(&HC5)), 2); : NEXT
30 OUT &HC6,5 : OUT &HC7,3
40 FOR I=0 to 255 : OUT &HC6,I : PRINT RIGHT$("0" + HEX$(INP(&HC7)), 2); : NEXT
50 FOR I=0 to 255 : OUT &H7E,I : PRINT RIGHT$("0" + HEX$(INP(&H7F)), 2); : NEXT

[MBilderbeek]

Here's an initial patch that sets the values to the above ones at the reset method. (Not ideal, but better than before, I guess). I'm not sure how to implement the Notes:

1. yes, it's simply using an array which was mostly initialized with zeroes
2. OK, I guess.
3. The test program reads back 0x03 now, so I guess that's OK now.
4. I guess that's also what the FIX ITs in the reset are talking about. Not sure how to implement this. What about other writes?
5. Not sure how to implement this. What about other writes?
6. Not sure how to implement this. What about other writes?

init_reg_vals.patch.txt

[m9710797]

Hi, @manuel: thanks for the initial patch. I tweaked it a bit, new version attached. I think Laurens' BASIC test program now prints the same values in openMSX. However the notes 1-6 remain TODO. @laurens: I have a series of questions. Most are easy to test myself, but I don't have so much time, and maybe you already tested (many of) them. 1) OpenMSX returns 00H from unused registers Real HW seems to return 0xFF for most, but not all unused registers. Do you have more details about this. E.g. registers F6-FF (both banks) seem strange. Also the test registers 0,1 (both banks) are documented to have initial value 0x00, but your table shows they read as 0xFF, are these maybe write-only registers? See also note 3 about partial registers. 2 + 3) Writing FFH to FM2 register 5 reads back 03H, so unused bits stay 0 This is an example of a partial register (register with unused bits). There are more registers like this, so I wonder why you specifically mention this one? Did you test them all, and was this one different? How do the others behave? 4) Writing FFH to FM2 register CCH reads back FFH, and none of C0H-C8H change (hidden feature?) Can you elaborate? Do you mean bits 0, 1 and 2 can be changed (value changes from F1 to FF)? But the meaning of those 3 bits is unknown (hidden feature)? It's unclear to me why you mention that C0-C8 don't change. (You want to emphasis it's not some mirror of another register?). You specifically mention it's for the FM2 bank. Was this just as an example or did you test that FM1 0xCC behaves differently? 5) Writing FFH to FM2 register B9H reads back 3FH, and changes B7H to 3FH as well. Ditto for BAH (+B8H) Do you mean that writes to 0xB9 (any value) are also written to 0xB7? What about the other way around? IOW is B9 a mirror for B7 (and BA for B8)? Again you specifically mention the FM2 bank, so it's different for FM1? 6) Writing FFH to FM2 register BBH reads back 3FH, writing 00H ditto Do you mean 0xBB always reads as 0x3F, whatever value was written? What about 0xBC, 0xBE, 0xBF? Or the corresponding registers in the FM1 bank? a) The current implementation in openMSX mirrored registers 0, 1, 2, 3, 8 from bank FM1 in bank FM2. I assume that was a bug and I already corrected it in the patch. But to double check: did you see any mirroring between the two banks? Wouter

…

On Thu, Sep 21, 2017 at 10:51 PM, Manuel Bilderbeek < ***@***.***> wrote: Here's an initial patch that sets the values to the above ones at the reset method. (Not ideal, but better than before, I guess). I'm not sure how to implement the Notes: 1. yes, it's simply using an array which was mostly initialized with zeroes 2. OK, I guess. 3. The test program reads back 0x03 now, so I guess that's OK now. 4. I guess that's also what the FIX ITs in the reset are talking about. Not sure how to implement this. What about other writes? 5. Not sure how to implement this. What about other writes? 6. Not sure how to implement this. What about other writes? init_reg_vals.patch.txt <https://github.com/openMSX/openMSX/files/1322672/init_reg_vals.patch.txt> — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1084 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AGYpQTnZMDvRoOxpofZjPTXQ0bani164ks5sksw2gaJpZM4PbkL9> .

[MBilderbeek]

Wouter, by the way, your patch is not attached to the ticket. (I guess attaching via e-mails doesn't work.)

[m9710797]

init-opl4.patch.txt

[MBilderbeek]

@grauw Can you comment on the questions above, please?

[grauw]

When you write a value to FM1 register 4 (timer control) with bit 7 set, the value is not stored. The value read back is always the last value written where bit 7 was not set, with mask 63H (unused bits zeroed).

(Values with bit 7 set are IRQ reset commands.)