/
pci.c
2137 lines (1739 loc) · 58 KB
/
pci.c
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/*
* OpenBIOS pci driver
*
* This driver is compliant to the
* PCI bus binding to IEEE 1275-1994 Rev 2.1
*
* (C) 2004 Stefan Reinauer
* (C) 2005 Ed Schouten <ed@fxq.nl>
*
* Some parts from OpenHackWare-0.4, Copyright (c) 2004-2005 Jocelyn Mayer
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2
*
*/
#include "config.h"
#include "libopenbios/bindings.h"
#include "libopenbios/ofmem.h"
#include "kernel/kernel.h"
#include "drivers/pci.h"
#include "libc/byteorder.h"
#include "libc/vsprintf.h"
#include "drivers/drivers.h"
#include "drivers/vga.h"
#include "packages/video.h"
#include "libopenbios/video.h"
#include "timer.h"
#include "pci.h"
#include "pci_database.h"
#ifdef CONFIG_DRIVER_MACIO
#include "macio.h"
#endif
#ifdef CONFIG_DRIVER_USB
#include "drivers/usb.h"
#endif
#ifdef CONFIG_DRIVER_VIRTIO_BLK
#include "virtio.h"
#endif
#if defined (CONFIG_DEBUG_PCI)
# define PCI_DPRINTF(format, ...) printk(format, ## __VA_ARGS__)
#else
# define PCI_DPRINTF(format, ...) do { } while (0)
#endif
#define set_bool_property(ph, name) set_property(ph, name, NULL, 0);
/* DECLARE data structures for the nodes. */
DECLARE_UNNAMED_NODE( ob_pci_bus_node, INSTALL_OPEN, 2*sizeof(int) );
DECLARE_UNNAMED_NODE( ob_pci_bridge_node, INSTALL_OPEN, 2*sizeof(int) );
DECLARE_UNNAMED_NODE( ob_pci_simple_node, 0, 2*sizeof(int) );
const pci_arch_t *arch;
#define IS_NOT_RELOCATABLE 0x80000000
#define IS_PREFETCHABLE 0x40000000
#define IS_ALIASED 0x20000000
static int encode_int32_cells(int num_cells, u32 *prop, ucell val)
{
int i = 0;
/* hi ... lo */
for (i=0; i < num_cells; ++i) {
prop[num_cells - i - 1] = val;
val >>= 16;
val >>= 16;
}
return num_cells;
}
static inline int pci_encode_phys_addr(u32 *phys, int flags, int space_code,
pci_addr dev, uint8_t reg, uint64_t addr)
{
/* phys.hi */
phys[0] = flags | (space_code << 24) | dev | reg;
/* phys.mid */
phys[1] = addr >> 32;
/* phys.lo */
phys[2] = addr;
return 3;
}
static inline int pci_encode_size(u32 *prop, uint64_t size)
{
return encode_int32_cells(2, prop, size);
}
static int host_address_cells(void)
{
return get_int_property(find_dev("/"), "#address-cells", NULL);
}
static int host_encode_phys_addr(u32 *prop, ucell addr)
{
return encode_int32_cells(host_address_cells(), prop, addr);
}
static int host_size_cells(void)
{
return get_int_property(find_dev("/"), "#size-cells", NULL);
}
/*
static int parent_address_cells(void)
{
phandle_t parent_ph = ih_to_phandle(my_parent());
return get_int_property(parent_ph, "#address-cells", NULL);
}
static int parent_size_cells(void)
{
phandle_t parent_ph = ih_to_phandle(my_parent());
return get_int_property(parent_ph, "#size-cells", NULL);
}
*/
#if defined(CONFIG_DEBUG_PCI)
static void dump_reg_property(const char* description, int nreg, u32 *reg)
{
int i;
printk("%s reg", description);
for (i=0; i < nreg; ++i) {
printk(" %08X", reg[i]);
}
printk("\n");
}
#endif
static unsigned long pci_bus_addr_to_host_addr(int space, uint32_t ba)
{
if (space == IO_SPACE) {
return arch->io_base + (unsigned long)ba;
} else if (space == MEMORY_SPACE_32) {
return arch->host_pci_base + (unsigned long)ba;
} else {
/* Return unaltered to aid debugging property values */
return (unsigned long)ba;
}
}
static inline void pci_decode_pci_addr(pci_addr addr, int *flags,
int *space_code, uint32_t *mask)
{
*flags = 0;
if (addr & 0x01) {
*space_code = IO_SPACE;
*mask = 0x00000001;
} else {
if (addr & 0x04) {
*space_code = MEMORY_SPACE_64;
*flags |= IS_NOT_RELOCATABLE; /* XXX: why not relocatable? */
} else {
*space_code = MEMORY_SPACE_32;
}
if (addr & 0x08) {
*flags |= IS_PREFETCHABLE;
}
*mask = 0x0000000F;
}
}
static void
ob_pci_open(int *idx)
{
int ret=1;
RET ( -ret );
}
static void
ob_pci_close(int *idx)
{
}
/* ( str len -- phys.lo phys.mid phys.hi ) */
static void
ob_pci_decode_unit(int *idx)
{
ucell hi, mid, lo;
const char *arg = pop_fstr_copy();
int dev, fn, reg, ss, n, p, t;
int bus, len;
char *ptr;
PCI_DPRINTF("ob_pci_decode_unit idx=%p\n", idx);
fn = 0;
reg = 0;
n = 0;
p = 0;
t = 0;
ptr = (char*)arg;
if (*ptr == 'n') {
n = IS_NOT_RELOCATABLE;
ptr++;
}
if (*ptr == 'i') {
ss = IO_SPACE;
ptr++;
if (*ptr == 't') {
t = IS_ALIASED;
ptr++;
}
/* DD,F,RR,NNNNNNNN */
dev = strtol(ptr, &ptr, 16);
ptr++;
fn = strtol(ptr, &ptr, 16);
ptr++;
reg = strtol(ptr, &ptr, 16);
ptr++;
lo = strtol(ptr, &ptr, 16);
mid = 0;
} else if (*ptr == 'm') {
ss = MEMORY_SPACE_32;
ptr++;
if (*ptr == 't') {
t = IS_ALIASED;
ptr++;
}
if (*ptr == 'p') {
p = IS_PREFETCHABLE;
ptr++;
}
/* DD,F,RR,NNNNNNNN */
dev = strtol(ptr, &ptr, 16);
ptr++;
fn = strtol(ptr, &ptr, 16);
ptr++;
reg = strtol(ptr, &ptr, 16);
ptr++;
lo = strtol(ptr, &ptr, 16);
mid = 0;
} else if (*ptr == 'x') {
unsigned long long addr64;
ss = MEMORY_SPACE_64;
ptr++;
if (*ptr == 'p') {
p = IS_PREFETCHABLE;
ptr++;
}
/* DD,F,RR,NNNNNNNNNNNNNNNN */
dev = strtol(ptr, &ptr, 16);
ptr++;
fn = strtol(ptr, &ptr, 16);
ptr++;
reg = strtol(ptr, &ptr, 16);
ptr++;
addr64 = strtoll(ptr, &ptr, 16);
lo = (ucell)addr64;
mid = addr64 >> 32;
} else {
ss = CONFIGURATION_SPACE;
/* "DD" or "DD,FF" */
dev = strtol(ptr, &ptr, 16);
if (*ptr == ',') {
ptr++;
fn = strtol(ptr, NULL, 16);
}
lo = 0;
mid = 0;
}
free((char*)arg);
bus = get_int_property(get_cur_dev(), "bus-range", &len);
hi = n | p | t | (ss << 24) | (bus << 16) | (dev << 11) | (fn << 8) | reg;
PUSH(lo);
PUSH(mid);
PUSH(hi);
PCI_DPRINTF("ob_pci_decode_unit idx=%p addr="
FMT_ucellx " " FMT_ucellx " " FMT_ucellx "\n",
idx, lo, mid, hi);
}
/* ( phys.lo phy.mid phys.hi -- str len ) */
static void
ob_pci_encode_unit(int *idx)
{
char buf[28];
cell hi = POP();
cell mid = POP();
cell lo = POP();
int n, p, t, ss, dev, fn, reg;
n = hi & IS_NOT_RELOCATABLE;
p = hi & IS_PREFETCHABLE;
t = hi & IS_ALIASED;
ss = (hi >> 24) & 0x03;
dev = (hi >> 11) & 0x1F;
fn = (hi >> 8) & 0x07;
reg = hi & 0xFF;
switch(ss) {
case CONFIGURATION_SPACE:
if (fn == 0) /* DD */
snprintf(buf, sizeof(buf), "%x", dev);
else /* DD,F */
snprintf(buf, sizeof(buf), "%x,%x", dev, fn);
break;
case IO_SPACE:
/* [n]i[t]DD,F,RR,NNNNNNNN */
snprintf(buf, sizeof(buf), "%si%s%x,%x,%x," FMT_ucellx,
n ? "n" : "", /* relocatable */
t ? "t" : "", /* aliased */
dev, fn, reg, t ? lo & 0x03FF : lo);
break;
case MEMORY_SPACE_32:
/* [n]m[t][p]DD,F,RR,NNNNNNNN */
snprintf(buf, sizeof(buf), "%sm%s%s%x,%x,%x," FMT_ucellx,
n ? "n" : "", /* relocatable */
t ? "t" : "", /* aliased */
p ? "p" : "", /* prefetchable */
dev, fn, reg, lo );
break;
case MEMORY_SPACE_64:
/* [n]x[p]DD,F,RR,NNNNNNNNNNNNNNNN */
snprintf(buf, sizeof(buf), "%sx%s%x,%x,%x,%llx",
n ? "n" : "", /* relocatable */
p ? "p" : "", /* prefetchable */
dev, fn, reg, ((long long)mid << 32) | (long long)lo);
break;
}
push_str(buf);
PCI_DPRINTF("ob_pci_encode_unit space=%d dev=%d fn=%d buf=%s\n",
ss, dev, fn, buf);
}
/* Map PCI MMIO or IO space from the BAR address. Note it is up to the caller
to understand whether the resulting address is in MEM or IO space and
use the appropriate accesses */
static ucell ob_pci_map(uint32_t ba, ucell size) {
phys_addr_t phys;
uint32_t mask;
int flags, space_code;
ucell virt;
pci_decode_pci_addr(ba, &flags, &space_code, &mask);
phys = pci_bus_addr_to_host_addr(space_code,
ba & ~mask);
#if defined(CONFIG_OFMEM)
ofmem_claim_phys(phys, size, 0);
#if defined(CONFIG_PPC)
/* For some reason PPC gets upset when virt != phys for map-in... */
virt = ofmem_claim_virt(phys, size, 0);
#else
virt = ofmem_claim_virt(-1, size, size);
#endif
ofmem_map(phys, virt, size, ofmem_arch_io_translation_mode(phys));
#else
virt = size; /* Keep compiler quiet */
virt = phys;
#endif
return virt;
}
static void ob_pci_unmap(ucell virt, ucell size) {
#if defined(CONFIG_OFMEM)
ofmem_unmap(virt, size);
#endif
}
/* ( pci-addr.lo pci-addr.mid pci-addr.hi size -- virt ) */
static void
ob_pci_bus_map_in(int *idx)
{
uint32_t ba;
ucell size;
ucell virt;
PCI_DPRINTF("ob_pci_bar_map_in idx=%p\n", idx);
size = POP();
POP();
POP();
ba = POP();
virt = ob_pci_map(ba, size);
PUSH(virt);
}
static void
ob_pci_dma_alloc(int *idx)
{
call_parent_method("dma-alloc");
}
static void
ob_pci_dma_free(int *idx)
{
call_parent_method("dma-free");
}
static void
ob_pci_dma_map_in(int *idx)
{
call_parent_method("dma-map-in");
}
static void
ob_pci_dma_map_out(int *idx)
{
call_parent_method("dma-map-out");
}
static void
ob_pci_dma_sync(int *idx)
{
call_parent_method("dma-sync");
}
NODE_METHODS(ob_pci_bus_node) = {
{ "open", ob_pci_open },
{ "close", ob_pci_close },
{ "decode-unit", ob_pci_decode_unit },
{ "encode-unit", ob_pci_encode_unit },
{ "pci-map-in", ob_pci_bus_map_in },
{ "dma-alloc", ob_pci_dma_alloc },
{ "dma-free", ob_pci_dma_free },
{ "dma-map-in", ob_pci_dma_map_in },
{ "dma-map-out", ob_pci_dma_map_out },
{ "dma-sync", ob_pci_dma_sync },
};
/* ( pci-addr.lo pci-addr.mid pci-addr.hi size -- virt ) */
static void
ob_pci_bridge_map_in(int *idx)
{
/* As per the IEEE-1275 PCI specification, chain up to the parent */
call_parent_method("pci-map-in");
}
NODE_METHODS(ob_pci_bridge_node) = {
{ "open", ob_pci_open },
{ "close", ob_pci_close },
{ "decode-unit", ob_pci_decode_unit },
{ "encode-unit", ob_pci_encode_unit },
{ "pci-map-in", ob_pci_bridge_map_in },
{ "dma-alloc", ob_pci_dma_alloc },
{ "dma-free", ob_pci_dma_free },
{ "dma-map-in", ob_pci_dma_map_in },
{ "dma-map-out", ob_pci_dma_map_out },
{ "dma-sync", ob_pci_dma_sync },
};
NODE_METHODS(ob_pci_simple_node) = {
{ "open", ob_pci_open },
{ "close", ob_pci_close },
};
static void pci_set_bus_range(const pci_config_t *config)
{
phandle_t dev = find_dev(config->path);
u32 props[2];
props[0] = config->secondary_bus;
props[1] = config->subordinate_bus;
PCI_DPRINTF("setting bus range for %s PCI device, "
"package handle " FMT_ucellx " "
"bus primary=%d secondary=%d subordinate=%d\n",
config->path,
dev,
config->primary_bus,
config->secondary_bus,
config->subordinate_bus);
set_property(dev, "bus-range", (char *)props, 2 * sizeof(props[0]));
}
static void ob_pci_reload_device_path(phandle_t phandle, pci_config_t *config);
static void pci_host_set_reg(phandle_t phandle, pci_config_t *config)
{
phandle_t dev = phandle;
/* at most 2 integers for address and size */
u32 props[4];
int ncells = 0;
ncells += encode_int32_cells(host_address_cells(), props + ncells,
arch->cfg_base);
ncells += encode_int32_cells(host_size_cells(), props + ncells,
arch->cfg_len);
set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
ob_pci_reload_device_path(dev, config);
#if defined(CONFIG_DEBUG_PCI)
dump_reg_property("pci_host_set_reg", 4, props);
#endif
}
/* child-phys : parent-phys : size */
/* 3 cells for PCI : 2 cells for 64bit parent : 2 cells for PCI */
static void pci_host_set_ranges(const pci_config_t *config)
{
phandle_t dev = get_cur_dev();
u32 props[32];
int ncells = 0;
pci_range_t range;
int i;
for (i = 0; i < 4; i++) {
range = arch->host_ranges[i];
/* End of range list reached */
if (range.type == 0x0 && range.len == 0x0) {
break;
}
ncells += pci_encode_phys_addr(props + ncells, 0, range.type,
0, 0, range.parentaddr);
ncells += host_encode_phys_addr(props + ncells, range.childaddr);
ncells += pci_encode_size(props + ncells, range.len);
}
set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
}
int host_config_cb(const pci_config_t *config)
{
pci_host_set_ranges(config);
return 0;
}
static int sabre_configure(phandle_t dev)
{
uint32_t props[28];
/* Sabre has a custom reg property from the default */
props[0] = 0x1fe;
props[1] = 0x0;
props[2] = 0x0;
props[3] = 0x10000;
props[4] = 0x1fe;
props[5] = 0x1000000;
props[6] = 0x0;
props[7] = 0x100;
set_property(dev, "reg", (char *)props, 8 * sizeof(props[0]));
props[0] = 0xc0000000;
props[1] = 0x20000000;
set_property(dev, "virtual-dma", (char *)props, 2 * sizeof(props[0]));
props[0] = 1;
set_property(dev, "#virtual-dma-size-cells", (char *)props,
sizeof(props[0]));
set_property(dev, "#virtual-dma-addr-cells", (char *)props,
sizeof(props[0]));
set_property(dev, "no-streaming-cache", (char *)props, 0);
props[0] = 0x000007f0;
props[1] = 0x000007ee;
props[2] = 0x000007ef;
props[3] = 0x000007e5;
set_property(dev, "interrupts", (char *)props, 4 * sizeof(props[0]));
props[0] = 0x0000001f;
set_property(dev, "upa-portid", (char *)props, 1 * sizeof(props[0]));
return 0;
}
int sabre_config_cb(const pci_config_t *config)
{
host_config_cb(config);
return sabre_configure(get_cur_dev());
}
int bridge_config_cb(const pci_config_t *config)
{
phandle_t aliases;
aliases = find_dev("/aliases");
set_property(aliases, "bridge", config->path, strlen(config->path) + 1);
return 0;
}
int simba_config_cb(const pci_config_t *config)
{
u32 props[128];
int ncells = 0;
bridge_config_cb(config);
/* Configure the simba ranges as per the mostly undocumented
PCI config register in Linux's apb_fake_ranges():
pci@1,1 (pciA):
IO: 0x1fe02000000-0x1fe027fffff
MEM: 0x1ff20000000-0x1ff5fffffff
pci@1 (pciB):
IO: 0x1fe02800000-0x1fe02ffffff
MEM: 0x1ff60000000-0x1ff9fffffff
*/
switch (PCI_FN(config->dev)) {
case 1:
/* IO: 0x1fe02000000-0x1fe027fffff */
pci_config_write8(config->dev, 0xde, 0x0f);
/* MEM: 0x1ff20000000-0x1ff5fffffff */
pci_config_write8(config->dev, 0xdf, 0x06);
/* Onboard NIC: slot 1, intno 0x21 */
ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 1, 0), 0, 0);
props[ncells++] = 0x1;
props[ncells++] = find_dev("/pci");
props[ncells++] = 0x21;
/* Onboard IDE: slot 3, intno 0x20 */
ncells += pci_encode_phys_addr(props + ncells, 0, 0, PCI_ADDR(1, 3, 0), 0, 0);
props[ncells++] = 0x1;
props[ncells++] = find_dev("/pci");
props[ncells++] = 0x20;
set_property(get_cur_dev(), "interrupt-map", (char *)props, ncells * sizeof(props[0]));
props[0] = 0x00fff800;
props[1] = 0x0;
props[2] = 0x0;
props[3] = 0x7;
set_property(get_cur_dev(), "interrupt-map-mask", (char *)props, 4 * sizeof(props[0]));
break;
case 0:
/* IO: 0x1fe02800000-0x1fe02ffffff */
pci_config_write8(config->dev, 0xde, 0xf0);
/* MEM: 0x1ff60000000-0x1ff9fffffff */
pci_config_write8(config->dev, 0xdf, 0x18);
break;
}
return 0;
}
int ide_config_cb2 (const pci_config_t *config)
{
ob_ide_init(config->path,
config->assigned[0] & ~0x0000000F,
(config->assigned[1] & ~0x0000000F) + 2,
config->assigned[2] & ~0x0000000F,
(config->assigned[3] & ~0x0000000F) + 2);
return 0;
}
int eth_config_cb (const pci_config_t *config)
{
phandle_t ph = get_cur_dev();
set_property(ph, "network-type", "ethernet", 9);
set_property(ph, "removable", "network", 8);
set_property(ph, "category", "net", 4);
return 0;
}
int sunhme_config_cb(const pci_config_t *config)
{
phandle_t ph = get_cur_dev();
set_int_property(ph, "hm-rev", 0x21);
return eth_config_cb(config);
}
int rtl8139_config_cb(const pci_config_t *config)
{
#ifdef CONFIG_PPC
/* Apple's OF seemingly enables bus mastering on some cards by
* default, which means that some buggy drivers forget to
* explicitly set it (OS X, MorphOS). Mimic this behaviour so
* that these buggy drivers work under emulation. */
if (is_apple()) {
ob_pci_enable_bus_master(config);
}
#endif
return eth_config_cb(config);
}
int sungem_config_cb (const pci_config_t *config)
{
phandle_t ph = get_cur_dev();
uint32_t val, *mmio;
uint8_t mac[6];
ucell virt;
#define MAC_ADDR0 (0x6080UL/4) /* MAC Address 0 Register */
#define MAC_ADDR1 (0x6084UL/4) /* MAC Address 1 Register */
#define MAC_ADDR2 (0x6088UL/4) /* MAC Address 2 Register */
/* Map PCI memory BAR 0 to access the sungem registers */
virt = ob_pci_map(config->assigned[0], 0x8000);
mmio = (void *)(uintptr_t)virt;
val = __le32_to_cpu(*(mmio + MAC_ADDR0));
mac[5] = val & 0xff;
mac[4] = (val >> 8) & 0xff;
val = __le32_to_cpu(*(mmio + MAC_ADDR1));
mac[3] = val & 0xff;
mac[2] = (val >> 8) & 0xff;
val = __le32_to_cpu(*(mmio + MAC_ADDR2));
mac[1] = val & 0xff;
mac[0] = (val >> 8) & 0xff;
set_property(ph, "local-mac-address", (char *)mac, 6);
ob_pci_unmap(virt, 0x8000);
return 0;
}
int virtio_blk_config_cb(const pci_config_t *config)
{
#ifdef CONFIG_DRIVER_VIRTIO_BLK
pci_addr addr;
uint8_t idx, cap_idx, cap_vndr;
uint8_t cfg_type, bar;
uint16_t status;
uint32_t offset, notify_mult = 0;
uint64_t common_cfg = 0, device_cfg = 0, notify_base = 0;
addr = PCI_ADDR(
PCI_BUS(config->dev),
PCI_DEV(config->dev),
PCI_FN(config->dev));
idx = (uint8_t)(pci_config_read16(addr, PCI_DEVICE_ID) & 0xff) - 1;
/* Check PCI capabilties: if they don't exist then we're certainly not
a 1.0 device */
status = pci_config_read16(addr, PCI_STATUS);
if (!(status & PCI_STATUS_CAP_LIST)) {
return 0;
}
/* Locate VIRTIO_PCI_CAP_COMMON_CFG and VIRTIO_PCI_CAP_DEVICE_CFG */
cap_idx = pci_config_read8(addr, PCI_CAPABILITY_LIST);
while ((cap_vndr = pci_config_read8(addr, cap_idx)) != 0) {
if (cap_vndr == PCI_CAP_ID_VNDR) {
cfg_type = pci_config_read8(addr, cap_idx + 0x3);
bar = pci_config_read8(addr, cap_idx + 0x4);
offset = pci_config_read32(addr, cap_idx + 0x8);
switch (cfg_type) {
case VIRTIO_PCI_CAP_COMMON_CFG:
common_cfg = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
break;
case VIRTIO_PCI_CAP_NOTIFY_CFG:
notify_base = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
notify_mult = pci_config_read32(addr, cap_idx + 16);
break;
case VIRTIO_PCI_CAP_DEVICE_CFG:
device_cfg = arch->host_pci_base + (config->assigned[bar] & ~0x0000000F) + offset;
break;
}
}
cap_idx = pci_config_read8(addr, cap_idx + 1);
}
/* If we didn't find the required configuration then exit */
if (common_cfg == 0 || device_cfg == 0 || notify_base == 0) {
return 0;
}
/* Enable bus mastering to ensure vring processing will run. */
ob_pci_enable_bus_master(config);
ob_virtio_init(config->path, "virtio-blk", common_cfg, device_cfg,
notify_base, notify_mult, idx);
#endif
return 0;
}
/*
* "Designing PCI Cards and Drivers for Power Macintosh Computers", p. 454
*
* "AAPL,address" provides an array of 32-bit logical addresses
* Nth entry corresponding to Nth "assigned-address" base address entry.
*/
static void pci_set_AAPL_address(const pci_config_t *config)
{
phandle_t dev = get_cur_dev();
cell props[7];
uint32_t mask;
int ncells, i, flags, space_code;
ncells = 0;
for (i = 0; i < 6; i++) {
if (!config->assigned[i] || !config->sizes[i])
continue;
pci_decode_pci_addr(config->assigned[i],
&flags, &space_code, &mask);
props[ncells++] = pci_bus_addr_to_host_addr(space_code,
config->assigned[i] & ~mask);
}
if (ncells)
set_property(dev, "AAPL,address", (char *)props,
ncells * sizeof(cell));
}
static void pci_set_assigned_addresses(phandle_t phandle,
const pci_config_t *config, int num_bars)
{
phandle_t dev = phandle;
u32 props[32];
int ncells;
int i;
uint32_t mask;
int flags, space_code;
ncells = 0;
for (i = 0; i < num_bars; i++) {
/* consider only bars with non-zero region size */
if (!config->sizes[i])
continue;
pci_decode_pci_addr(config->assigned[i],
&flags, &space_code, &mask);
ncells += pci_encode_phys_addr(props + ncells,
flags, space_code, config->dev,
PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
config->assigned[i] & ~mask);
props[ncells++] = 0x00000000;
props[ncells++] = config->sizes[i];
}
if (ncells)
set_property(dev, "assigned-addresses", (char *)props,
ncells * sizeof(props[0]));
}
/* call after writing "reg" property to update config->path */
static void ob_pci_reload_device_path(phandle_t phandle, pci_config_t *config)
{
/* since "name" and "reg" are now assigned
we need to reload current node name */
char *new_path = get_path_from_ph(phandle);
if (new_path) {
if (0 != strcmp(config->path, new_path)) {
PCI_DPRINTF("\n=== CHANGED === package path old=%s new=%s\n",
config->path, new_path);
strncpy(config->path, new_path, sizeof(config->path));
config->path[sizeof(config->path)-1] = '\0';
}
free(new_path);
} else {
PCI_DPRINTF("\n=== package path old=%s new=NULL\n", config->path);
}
}
static void pci_set_reg(phandle_t phandle,
pci_config_t *config, int num_bars)
{
phandle_t dev = phandle;
u32 props[38];
int ncells;
int i;
uint32_t mask;
int space_code, flags;
ncells = 0;
/* first (addr, size) pair is the beginning of configuration address space */
ncells += pci_encode_phys_addr(props + ncells, 0, CONFIGURATION_SPACE,
config->dev, 0, 0);
ncells += pci_encode_size(props + ncells, 0);
for (i = 0; i < num_bars; i++) {
/* consider only bars with non-zero region size */
if (!config->sizes[i])
continue;
pci_decode_pci_addr(config->regions[i],
&flags, &space_code, &mask);
ncells += pci_encode_phys_addr(props + ncells,
flags, space_code, config->dev,
PCI_BASE_ADDR_0 + (i * sizeof(uint32_t)),
config->regions[i] & ~mask);
/* set size */
ncells += pci_encode_size(props + ncells, config->sizes[i]);
}
set_property(dev, "reg", (char *)props, ncells * sizeof(props[0]));
ob_pci_reload_device_path(dev, config);
#if defined(CONFIG_DEBUG_PCI)
dump_reg_property("pci_set_reg", ncells, props);
#endif
}
static void pci_set_ranges(const pci_config_t *config)
{
phandle_t dev = get_cur_dev();
u32 props[32];
int ncells;
int i;
uint32_t mask;
int flags;
int space_code;
ncells = 0;
for (i = 0; i < 6; i++) {
if (!config->assigned[i] || !config->sizes[i])
continue;
/* child address */
props[ncells++] = 0x00000000;
/* parent address */
pci_decode_pci_addr(config->assigned[i],
&flags, &space_code, &mask);
ncells += pci_encode_phys_addr(props + ncells, flags, space_code,
config->dev, 0x10 + i * 4,
config->assigned[i] & ~mask);
/* size */
props[ncells++] = config->sizes[i];
}
set_property(dev, "ranges", (char *)props, ncells * sizeof(props[0]));
}
int macio_heathrow_config_cb (const pci_config_t *config)
{
pci_set_ranges(config);
#ifdef CONFIG_DRIVER_MACIO
ob_macio_heathrow_init(config->path, config->assigned[0] & ~0x0000000F);
#endif
return 0;
}
int macio_keylargo_config_cb (const pci_config_t *config)
{
pci_set_ranges(config);
#ifdef CONFIG_DRIVER_MACIO
ob_macio_keylargo_init(config->path, config->assigned[0] & ~0x0000000F);