/
if_em_hw.c
11629 lines (10520 loc) · 335 KB
/
if_em_hw.c
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/*******************************************************************************
Copyright (c) 2001-2005, Intel Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Intel Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* $OpenBSD: if_em_hw.c,v 1.109 2020/07/13 10:35:55 dlg Exp $ */
/*
* if_em_hw.c Shared functions for accessing and configuring the MAC
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sockio.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/device.h>
#include <sys/socket.h>
#include <sys/kstat.h>
#include <net/if.h>
#include <net/if_media.h>
#include <netinet/in.h>
#include <netinet/if_ether.h>
#include <uvm/uvm_extern.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/if_em.h>
#include <dev/pci/if_em_hw.h>
#include <dev/pci/if_em_soc.h>
#include <dev/mii/rgephyreg.h>
#define STATIC
static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t);
static void em_swfw_sync_release(struct em_hw *, uint16_t);
static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);
static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);
static int32_t em_get_software_semaphore(struct em_hw *);
static void em_release_software_semaphore(struct em_hw *);
static int32_t em_check_downshift(struct em_hw *);
static void em_clear_vfta(struct em_hw *);
void em_clear_vfta_i350(struct em_hw *);
static int32_t em_commit_shadow_ram(struct em_hw *);
static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t);
static int32_t em_config_fc_after_link_up(struct em_hw *);
static int32_t em_match_gig_phy(struct em_hw *);
static int32_t em_detect_gig_phy(struct em_hw *);
static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t);
static int32_t em_get_auto_rd_done(struct em_hw *);
static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *);
static int32_t em_get_hw_eeprom_semaphore(struct em_hw *);
static int32_t em_get_phy_cfg_done(struct em_hw *);
static int32_t em_get_software_flag(struct em_hw *);
static int32_t em_ich8_cycle_init(struct em_hw *);
static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t);
static int32_t em_id_led_init(struct em_hw *);
static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t,
uint32_t);
static int32_t em_init_lcd_from_nvm(struct em_hw *);
static int32_t em_phy_no_cable_workaround(struct em_hw *);
static void em_init_rx_addrs(struct em_hw *);
static void em_initialize_hardware_bits(struct em_softc *);
static void em_toggle_lanphypc_pch_lpt(struct em_hw *);
static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force);
static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *);
static int32_t em_kumeran_lock_loss_workaround(struct em_hw *);
static int32_t em_mng_enable_host_if(struct em_hw *);
static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t,
uint16_t *data);
static int32_t em_poll_eerd_eewr_done(struct em_hw *, int);
static void em_put_hw_eeprom_semaphore(struct em_hw *);
static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);
static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);
static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);
static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,
uint16_t *);
static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,
uint16_t);
static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *);
static void em_release_software_flag(struct em_hw *);
static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t);
static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t);
static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t);
static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);
static void em_set_pci_express_master_disable(struct em_hw *);
static int32_t em_wait_autoneg(struct em_hw *);
static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t);
static int32_t em_set_phy_type(struct em_hw *);
static void em_phy_init_script(struct em_hw *);
static int32_t em_setup_copper_link(struct em_hw *);
static int32_t em_setup_fiber_serdes_link(struct em_hw *);
static int32_t em_adjust_serdes_amplitude(struct em_hw *);
static int32_t em_phy_force_speed_duplex(struct em_hw *);
static int32_t em_config_mac_to_phy(struct em_hw *);
static void em_raise_mdi_clk(struct em_hw *, uint32_t *);
static void em_lower_mdi_clk(struct em_hw *, uint32_t *);
static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);
static uint16_t em_shift_in_mdi_bits(struct em_hw *);
static int32_t em_phy_reset_dsp(struct em_hw *);
static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t,
uint16_t *);
static int32_t em_spi_eeprom_ready(struct em_hw *);
static void em_raise_ee_clk(struct em_hw *, uint32_t *);
static void em_lower_ee_clk(struct em_hw *, uint32_t *);
static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t);
static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);
static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);
static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t);
static int32_t em_acquire_eeprom(struct em_hw *);
static void em_release_eeprom(struct em_hw *);
static void em_standby_eeprom(struct em_hw *);
static int32_t em_set_vco_speed(struct em_hw *);
static int32_t em_polarity_reversal_workaround(struct em_hw *);
static int32_t em_set_phy_mode(struct em_hw *);
static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *);
static uint8_t em_calculate_mng_checksum(char *, uint32_t);
static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t);
static int32_t em_configure_kmrn_for_1000(struct em_hw *);
static int32_t em_set_pciex_completion_timeout(struct em_hw *hw);
static int32_t em_set_mdio_slow_mode_hv(struct em_hw *);
int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *);
int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *);
int32_t em_link_stall_workaround_hv(struct em_hw *);
int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t);
int32_t em_k1_workaround_lv(struct em_hw *);
int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t);
int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t);
void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t);
int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,
uint16_t *, boolean_t);
int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,
uint16_t *, boolean_t);
int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,
boolean_t);
int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t);
void em_power_up_serdes_link_82575(struct em_hw *);
int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *,
uint16_t *);
int32_t em_set_eee_i350(struct em_hw *);
int32_t em_set_eee_pchlan(struct em_hw *);
int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
int32_t em_initialize_M88E1512_phy(struct em_hw *);
/* IGP cable length table */
static const uint16_t
em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
{5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
110,
110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
120};
static const uint16_t
em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
{0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118,
121, 124};
/******************************************************************************
* Set the phy type member in the hw struct.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
STATIC int32_t
em_set_phy_type(struct em_hw *hw)
{
DEBUGFUNC("em_set_phy_type");
if (hw->mac_type == em_undefined)
return -E1000_ERR_PHY_TYPE;
switch (hw->phy_id) {
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
case M88E1111_I_PHY_ID:
case M88E1112_E_PHY_ID:
case M88E1543_E_PHY_ID:
case M88E1512_E_PHY_ID:
case I210_I_PHY_ID:
case I347AT4_E_PHY_ID:
hw->phy_type = em_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if (hw->mac_type == em_82541 ||
hw->mac_type == em_82541_rev_2 ||
hw->mac_type == em_82547 ||
hw->mac_type == em_82547_rev_2) {
hw->phy_type = em_phy_igp;
break;
}
case IGP03E1000_E_PHY_ID:
case IGP04E1000_E_PHY_ID:
hw->phy_type = em_phy_igp_3;
break;
case IFE_E_PHY_ID:
case IFE_PLUS_E_PHY_ID:
case IFE_C_E_PHY_ID:
hw->phy_type = em_phy_ife;
break;
case M88E1141_E_PHY_ID:
hw->phy_type = em_phy_oem;
break;
case I82577_E_PHY_ID:
hw->phy_type = em_phy_82577;
break;
case I82578_E_PHY_ID:
hw->phy_type = em_phy_82578;
break;
case I82579_E_PHY_ID:
hw->phy_type = em_phy_82579;
break;
case I217_E_PHY_ID:
hw->phy_type = em_phy_i217;
break;
case I82580_I_PHY_ID:
case I350_I_PHY_ID:
hw->phy_type = em_phy_82580;
break;
case RTL8211_E_PHY_ID:
hw->phy_type = em_phy_rtl8211;
break;
case BME1000_E_PHY_ID:
if (hw->phy_revision == 1) {
hw->phy_type = em_phy_bm;
break;
}
/* FALLTHROUGH */
case GG82563_E_PHY_ID:
if (hw->mac_type == em_80003es2lan) {
hw->phy_type = em_phy_gg82563;
break;
}
/* FALLTHROUGH */
default:
/* Should never have loaded on this device */
hw->phy_type = em_phy_undefined;
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
}
/******************************************************************************
* IGP phy init script - initializes the GbE PHY
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
static void
em_phy_init_script(struct em_hw *hw)
{
uint16_t phy_saved_data;
DEBUGFUNC("em_phy_init_script");
if (hw->phy_init_script) {
msec_delay(20);
/*
* Save off the current value of register 0x2F5B to be
* restored at the end of this routine.
*/
em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
/* Disabled the PHY transmitter */
em_write_phy_reg(hw, 0x2F5B, 0x0003);
msec_delay(20);
em_write_phy_reg(hw, 0x0000, 0x0140);
msec_delay(5);
switch (hw->mac_type) {
case em_82541:
case em_82547:
em_write_phy_reg(hw, 0x1F95, 0x0001);
em_write_phy_reg(hw, 0x1F71, 0xBD21);
em_write_phy_reg(hw, 0x1F79, 0x0018);
em_write_phy_reg(hw, 0x1F30, 0x1600);
em_write_phy_reg(hw, 0x1F31, 0x0014);
em_write_phy_reg(hw, 0x1F32, 0x161C);
em_write_phy_reg(hw, 0x1F94, 0x0003);
em_write_phy_reg(hw, 0x1F96, 0x003F);
em_write_phy_reg(hw, 0x2010, 0x0008);
break;
case em_82541_rev_2:
case em_82547_rev_2:
em_write_phy_reg(hw, 0x1F73, 0x0099);
break;
default:
break;
}
em_write_phy_reg(hw, 0x0000, 0x3300);
msec_delay(20);
/* Now enable the transmitter */
em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
if (hw->mac_type == em_82547) {
uint16_t fused, fine, coarse;
/* Move to analog registers page */
em_read_phy_reg(hw,
IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
em_read_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_STATUS, &fused);
fine = fused &
IGP01E1000_ANALOG_FUSE_FINE_MASK;
coarse = fused &
IGP01E1000_ANALOG_FUSE_COARSE_MASK;
if (coarse >
IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
coarse -=
IGP01E1000_ANALOG_FUSE_COARSE_10;
fine -=
IGP01E1000_ANALOG_FUSE_FINE_1;
} else if (coarse ==
IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
fused = (fused &
IGP01E1000_ANALOG_FUSE_POLY_MASK) |
(fine &
IGP01E1000_ANALOG_FUSE_FINE_MASK) |
(coarse &
IGP01E1000_ANALOG_FUSE_COARSE_MASK);
em_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_CONTROL,
fused);
em_write_phy_reg(hw,
IGP01E1000_ANALOG_FUSE_BYPASS,
IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
}
}
}
}
/******************************************************************************
* Set the mac type member in the hw struct.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
int32_t
em_set_mac_type(struct em_hw *hw)
{
DEBUGFUNC("em_set_mac_type");
switch (hw->device_id) {
case E1000_DEV_ID_82542:
switch (hw->revision_id) {
case E1000_82542_2_0_REV_ID:
hw->mac_type = em_82542_rev2_0;
break;
case E1000_82542_2_1_REV_ID:
hw->mac_type = em_82542_rev2_1;
break;
default:
/* Invalid 82542 revision ID */
return -E1000_ERR_MAC_TYPE;
}
break;
case E1000_DEV_ID_82543GC_FIBER:
case E1000_DEV_ID_82543GC_COPPER:
hw->mac_type = em_82543;
break;
case E1000_DEV_ID_82544EI_COPPER:
case E1000_DEV_ID_82544EI_FIBER:
case E1000_DEV_ID_82544GC_COPPER:
case E1000_DEV_ID_82544GC_LOM:
hw->mac_type = em_82544;
break;
case E1000_DEV_ID_82540EM:
case E1000_DEV_ID_82540EM_LOM:
case E1000_DEV_ID_82540EP:
case E1000_DEV_ID_82540EP_LOM:
case E1000_DEV_ID_82540EP_LP:
hw->mac_type = em_82540;
break;
case E1000_DEV_ID_82545EM_COPPER:
case E1000_DEV_ID_82545EM_FIBER:
hw->mac_type = em_82545;
break;
case E1000_DEV_ID_82545GM_COPPER:
case E1000_DEV_ID_82545GM_FIBER:
case E1000_DEV_ID_82545GM_SERDES:
hw->mac_type = em_82545_rev_3;
break;
case E1000_DEV_ID_82546EB_COPPER:
case E1000_DEV_ID_82546EB_FIBER:
case E1000_DEV_ID_82546EB_QUAD_COPPER:
hw->mac_type = em_82546;
break;
case E1000_DEV_ID_82546GB_COPPER:
case E1000_DEV_ID_82546GB_FIBER:
case E1000_DEV_ID_82546GB_SERDES:
case E1000_DEV_ID_82546GB_PCIE:
case E1000_DEV_ID_82546GB_QUAD_COPPER:
case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
case E1000_DEV_ID_82546GB_2:
hw->mac_type = em_82546_rev_3;
break;
case E1000_DEV_ID_82541EI:
case E1000_DEV_ID_82541EI_MOBILE:
case E1000_DEV_ID_82541ER_LOM:
hw->mac_type = em_82541;
break;
case E1000_DEV_ID_82541ER:
case E1000_DEV_ID_82541GI:
case E1000_DEV_ID_82541GI_LF:
case E1000_DEV_ID_82541GI_MOBILE:
hw->mac_type = em_82541_rev_2;
break;
case E1000_DEV_ID_82547EI:
case E1000_DEV_ID_82547EI_MOBILE:
hw->mac_type = em_82547;
break;
case E1000_DEV_ID_82547GI:
hw->mac_type = em_82547_rev_2;
break;
case E1000_DEV_ID_82571EB_AF:
case E1000_DEV_ID_82571EB_AT:
case E1000_DEV_ID_82571EB_COPPER:
case E1000_DEV_ID_82571EB_FIBER:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_QUAD_COPPER:
case E1000_DEV_ID_82571EB_QUAD_FIBER:
case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
case E1000_DEV_ID_82571EB_SERDES_DUAL:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
case E1000_DEV_ID_82571PT_QUAD_COPPER:
hw->mac_type = em_82571;
break;
case E1000_DEV_ID_82572EI_COPPER:
case E1000_DEV_ID_82572EI_FIBER:
case E1000_DEV_ID_82572EI_SERDES:
case E1000_DEV_ID_82572EI:
hw->mac_type = em_82572;
break;
case E1000_DEV_ID_82573E:
case E1000_DEV_ID_82573E_IAMT:
case E1000_DEV_ID_82573E_PM:
case E1000_DEV_ID_82573L:
case E1000_DEV_ID_82573L_PL_1:
case E1000_DEV_ID_82573L_PL_2:
case E1000_DEV_ID_82573V_PM:
hw->mac_type = em_82573;
break;
case E1000_DEV_ID_82574L:
case E1000_DEV_ID_82574LA:
case E1000_DEV_ID_82583V:
hw->mac_type = em_82574;
break;
case E1000_DEV_ID_82575EB_PT:
case E1000_DEV_ID_82575EB_PF:
case E1000_DEV_ID_82575GB_QP:
case E1000_DEV_ID_82575GB_QP_PM:
hw->mac_type = em_82575;
hw->initialize_hw_bits_disable = 1;
break;
case E1000_DEV_ID_82576:
case E1000_DEV_ID_82576_FIBER:
case E1000_DEV_ID_82576_SERDES:
case E1000_DEV_ID_82576_QUAD_COPPER:
case E1000_DEV_ID_82576_QUAD_CU_ET2:
case E1000_DEV_ID_82576_NS:
case E1000_DEV_ID_82576_NS_SERDES:
case E1000_DEV_ID_82576_SERDES_QUAD:
hw->mac_type = em_82576;
hw->initialize_hw_bits_disable = 1;
break;
case E1000_DEV_ID_82580_COPPER:
case E1000_DEV_ID_82580_FIBER:
case E1000_DEV_ID_82580_QUAD_FIBER:
case E1000_DEV_ID_82580_SERDES:
case E1000_DEV_ID_82580_SGMII:
case E1000_DEV_ID_82580_COPPER_DUAL:
case E1000_DEV_ID_DH89XXCC_SGMII:
case E1000_DEV_ID_DH89XXCC_SERDES:
case E1000_DEV_ID_DH89XXCC_BACKPLANE:
case E1000_DEV_ID_DH89XXCC_SFP:
hw->mac_type = em_82580;
hw->initialize_hw_bits_disable = 1;
break;
case E1000_DEV_ID_I210_COPPER:
case E1000_DEV_ID_I210_COPPER_OEM1:
case E1000_DEV_ID_I210_COPPER_IT:
case E1000_DEV_ID_I210_FIBER:
case E1000_DEV_ID_I210_SERDES:
case E1000_DEV_ID_I210_SGMII:
case E1000_DEV_ID_I210_COPPER_FLASHLESS:
case E1000_DEV_ID_I210_SERDES_FLASHLESS:
case E1000_DEV_ID_I211_COPPER:
hw->mac_type = em_i210;
hw->initialize_hw_bits_disable = 1;
hw->eee_enable = 1;
break;
case E1000_DEV_ID_I350_COPPER:
case E1000_DEV_ID_I350_FIBER:
case E1000_DEV_ID_I350_SERDES:
case E1000_DEV_ID_I350_SGMII:
case E1000_DEV_ID_I350_DA4:
case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
case E1000_DEV_ID_I354_SGMII:
case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
hw->mac_type = em_i350;
hw->initialize_hw_bits_disable = 1;
hw->eee_enable = 1;
break;
case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->mac_type = em_80003es2lan;
break;
case E1000_DEV_ID_ICH8_IFE:
case E1000_DEV_ID_ICH8_IFE_G:
case E1000_DEV_ID_ICH8_IFE_GT:
case E1000_DEV_ID_ICH8_IGP_AMT:
case E1000_DEV_ID_ICH8_IGP_C:
case E1000_DEV_ID_ICH8_IGP_M:
case E1000_DEV_ID_ICH8_IGP_M_AMT:
case E1000_DEV_ID_ICH8_82567V_3:
hw->mac_type = em_ich8lan;
break;
case E1000_DEV_ID_ICH9_BM:
case E1000_DEV_ID_ICH9_IFE:
case E1000_DEV_ID_ICH9_IFE_G:
case E1000_DEV_ID_ICH9_IFE_GT:
case E1000_DEV_ID_ICH9_IGP_AMT:
case E1000_DEV_ID_ICH9_IGP_C:
case E1000_DEV_ID_ICH9_IGP_M:
case E1000_DEV_ID_ICH9_IGP_M_AMT:
case E1000_DEV_ID_ICH9_IGP_M_V:
case E1000_DEV_ID_ICH10_R_BM_LF:
case E1000_DEV_ID_ICH10_R_BM_LM:
case E1000_DEV_ID_ICH10_R_BM_V:
hw->mac_type = em_ich9lan;
break;
case E1000_DEV_ID_ICH10_D_BM_LF:
case E1000_DEV_ID_ICH10_D_BM_LM:
case E1000_DEV_ID_ICH10_D_BM_V:
hw->mac_type = em_ich10lan;
break;
case E1000_DEV_ID_PCH_M_HV_LC:
case E1000_DEV_ID_PCH_M_HV_LM:
case E1000_DEV_ID_PCH_D_HV_DC:
case E1000_DEV_ID_PCH_D_HV_DM:
hw->mac_type = em_pchlan;
hw->eee_enable = 1;
break;
case E1000_DEV_ID_PCH2_LV_LM:
case E1000_DEV_ID_PCH2_LV_V:
hw->mac_type = em_pch2lan;
break;
case E1000_DEV_ID_PCH_LPT_I217_LM:
case E1000_DEV_ID_PCH_LPT_I217_V:
case E1000_DEV_ID_PCH_LPTLP_I218_LM:
case E1000_DEV_ID_PCH_LPTLP_I218_V:
case E1000_DEV_ID_PCH_I218_LM2:
case E1000_DEV_ID_PCH_I218_V2:
case E1000_DEV_ID_PCH_I218_LM3:
case E1000_DEV_ID_PCH_I218_V3:
hw->mac_type = em_pch_lpt;
break;
case E1000_DEV_ID_PCH_SPT_I219_LM:
case E1000_DEV_ID_PCH_SPT_I219_V:
case E1000_DEV_ID_PCH_SPT_I219_LM2:
case E1000_DEV_ID_PCH_SPT_I219_V2:
case E1000_DEV_ID_PCH_LBG_I219_LM3:
case E1000_DEV_ID_PCH_SPT_I219_LM4:
case E1000_DEV_ID_PCH_SPT_I219_V4:
case E1000_DEV_ID_PCH_SPT_I219_LM5:
case E1000_DEV_ID_PCH_SPT_I219_V5:
case E1000_DEV_ID_PCH_CMP_I219_LM12:
case E1000_DEV_ID_PCH_CMP_I219_V12:
hw->mac_type = em_pch_spt;
break;
case E1000_DEV_ID_PCH_CNP_I219_LM6:
case E1000_DEV_ID_PCH_CNP_I219_V6:
case E1000_DEV_ID_PCH_CNP_I219_LM7:
case E1000_DEV_ID_PCH_CNP_I219_V7:
case E1000_DEV_ID_PCH_ICP_I219_LM8:
case E1000_DEV_ID_PCH_ICP_I219_V8:
case E1000_DEV_ID_PCH_ICP_I219_LM9:
case E1000_DEV_ID_PCH_ICP_I219_V9:
case E1000_DEV_ID_PCH_CMP_I219_LM10:
case E1000_DEV_ID_PCH_CMP_I219_V10:
case E1000_DEV_ID_PCH_CMP_I219_LM11:
case E1000_DEV_ID_PCH_CMP_I219_V11:
case E1000_DEV_ID_PCH_TGP_I219_LM13:
case E1000_DEV_ID_PCH_TGP_I219_V13:
case E1000_DEV_ID_PCH_TGP_I219_LM14:
case E1000_DEV_ID_PCH_TGP_I219_V14:
case E1000_DEV_ID_PCH_TGP_I219_LM15:
hw->mac_type = em_pch_cnp;
break;
case E1000_DEV_ID_EP80579_LAN_1:
hw->mac_type = em_icp_xxxx;
hw->icp_xxxx_port_num = 0;
break;
case E1000_DEV_ID_EP80579_LAN_2:
case E1000_DEV_ID_EP80579_LAN_4:
hw->mac_type = em_icp_xxxx;
hw->icp_xxxx_port_num = 1;
break;
case E1000_DEV_ID_EP80579_LAN_3:
case E1000_DEV_ID_EP80579_LAN_5:
hw->mac_type = em_icp_xxxx;
hw->icp_xxxx_port_num = 2;
break;
case E1000_DEV_ID_EP80579_LAN_6:
hw->mac_type = em_icp_xxxx;
hw->icp_xxxx_port_num = 3;
break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
}
switch (hw->mac_type) {
case em_ich8lan:
case em_ich9lan:
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
hw->swfwhw_semaphore_present = TRUE;
hw->asf_firmware_present = TRUE;
break;
case em_80003es2lan:
case em_82575:
case em_82576:
case em_82580:
case em_i210:
case em_i350:
hw->swfw_sync_present = TRUE;
/* FALLTHROUGH */
case em_82571:
case em_82572:
case em_82573:
case em_82574:
hw->eeprom_semaphore_present = TRUE;
/* FALLTHROUGH */
case em_82541:
case em_82547:
case em_82541_rev_2:
case em_82547_rev_2:
hw->asf_firmware_present = TRUE;
break;
default:
break;
}
return E1000_SUCCESS;
}
/*****************************************************************************
* Set media type and TBI compatibility.
*
* hw - Struct containing variables accessed by shared code
* **************************************************************************/
void
em_set_media_type(struct em_hw *hw)
{
uint32_t status, ctrl_ext;
DEBUGFUNC("em_set_media_type");
if (hw->mac_type != em_82543) {
/* tbi_compatibility is only valid on 82543 */
hw->tbi_compatibility_en = FALSE;
}
if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
hw->mac_type == em_82576 ||
hw->mac_type == em_i210 || hw->mac_type == em_i350) {
hw->media_type = em_media_type_copper;
ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
case E1000_CTRL_EXT_LINK_MODE_SGMII:
ctrl_ext |= E1000_CTRL_I2C_ENA;
break;
case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
hw->media_type = em_media_type_internal_serdes;
ctrl_ext |= E1000_CTRL_I2C_ENA;
break;
default:
ctrl_ext &= ~E1000_CTRL_I2C_ENA;
break;
}
E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
return;
}
switch (hw->device_id) {
case E1000_DEV_ID_82545GM_SERDES:
case E1000_DEV_ID_82546GB_SERDES:
case E1000_DEV_ID_82571EB_SERDES:
case E1000_DEV_ID_82571EB_SERDES_DUAL:
case E1000_DEV_ID_82571EB_SERDES_QUAD:
case E1000_DEV_ID_82572EI_SERDES:
case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
hw->media_type = em_media_type_internal_serdes;
break;
case E1000_DEV_ID_EP80579_LAN_1:
case E1000_DEV_ID_EP80579_LAN_2:
case E1000_DEV_ID_EP80579_LAN_3:
case E1000_DEV_ID_EP80579_LAN_4:
case E1000_DEV_ID_EP80579_LAN_5:
case E1000_DEV_ID_EP80579_LAN_6:
hw->media_type = em_media_type_copper;
break;
default:
switch (hw->mac_type) {
case em_82542_rev2_0:
case em_82542_rev2_1:
hw->media_type = em_media_type_fiber;
break;
case em_ich8lan:
case em_ich9lan:
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
case em_82573:
case em_82574:
/*
* The STATUS_TBIMODE bit is reserved or reused for
* the this device.
*/
hw->media_type = em_media_type_copper;
break;
default:
status = E1000_READ_REG(hw, STATUS);
if (status & E1000_STATUS_TBIMODE) {
hw->media_type = em_media_type_fiber;
/* tbi_compatibility not valid on fiber */
hw->tbi_compatibility_en = FALSE;
} else {
hw->media_type = em_media_type_copper;
}
break;
}
}
}
/******************************************************************************
* Reset the transmit and receive units; mask and clear all interrupts.
*
* hw - Struct containing variables accessed by shared code
*****************************************************************************/
int32_t
em_reset_hw(struct em_hw *hw)
{
uint32_t ctrl;
uint32_t ctrl_ext;
uint32_t icr;
uint32_t manc;
uint32_t led_ctrl;
uint32_t timeout;
uint32_t extcnf_ctrl;
int32_t ret_val;
DEBUGFUNC("em_reset_hw");
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == em_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
em_pci_clear_mwi(hw);
}
if (hw->bus_type == em_bus_type_pci_express) {
/*
* Prevent the PCI-E bus from sticking if there is no TLP
* connection on the last TLP read/write transaction when MAC
* is reset.
*/
if (em_disable_pciex_master(hw) != E1000_SUCCESS) {
DEBUGOUT("PCI-E Master disable polling has failed.\n");
}
}
/* Set the completion timeout for 82575 chips */
if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
hw->mac_type == em_82576 ||
hw->mac_type == em_i210 || hw->mac_type == em_i350) {
ret_val = em_set_pciex_completion_timeout(hw);
if (ret_val) {
DEBUGOUT("PCI-E Set completion timeout has failed.\n");
}
}
/* Clear interrupt mask to stop board from generating interrupts */
DEBUGOUT("Masking off all interrupts\n");
E1000_WRITE_REG(hw, IMC, 0xffffffff);
/*
* Disable the Transmit and Receive units. Then delay to allow any
* pending transactions to complete before we hit the MAC with the
* global reset.
*/
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
E1000_WRITE_FLUSH(hw);
/*
* The tbi_compatibility_on Flag must be cleared when Rctl is
* cleared.
*/
hw->tbi_compatibility_on = FALSE;
/*
* Delay to allow any outstanding PCI transactions to complete before
* resetting the device
*/
msec_delay(10);
ctrl = E1000_READ_REG(hw, CTRL);
/* Must reset the PHY before resetting the MAC */
if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
msec_delay(5);
}
/*
* Must acquire the MDIO ownership before MAC reset. Ownership
* defaults to firmware after a reset.
*/
if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
timeout = 10;
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
do {
E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
break;
else
extcnf_ctrl |=
E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
msec_delay(2);
timeout--;
} while (timeout);
}
/* Workaround for ICH8 bit corruption issue in FIFO memory */
if (hw->mac_type == em_ich8lan) {
/* Set Tx and Rx buffer allocation to 8k apiece. */
E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
/* Set Packet Buffer Size to 16k. */
E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
}
/*
* Issue a global reset to the MAC. This will reset the chip's
* transmit, receive, DMA, and link units. It will not effect the
* current PCI configuration. The global reset bit is self-
* clearing, and should clear within a microsecond.
*/
DEBUGOUT("Issuing a global reset to MAC\n");
switch (hw->mac_type) {
case em_82544:
case em_82540:
case em_82545:
case em_82546:
case em_82541:
case em_82541_rev_2:
/*
* These controllers can't ack the 64-bit write when issuing
* the reset, so use IO-mapping as a workaround to issue the
* reset
*/
E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
break;
case em_82545_rev_3:
case em_82546_rev_3:
/* Reset is performed on a shadow of the control register */
E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
break;
case em_ich8lan:
case em_ich9lan:
case em_ich10lan:
case em_pchlan:
case em_pch2lan:
case em_pch_lpt:
case em_pch_spt:
case em_pch_cnp:
if (!hw->phy_reset_disable &&
em_check_phy_reset_block(hw) == E1000_SUCCESS) {
/*
* PHY HW reset requires MAC CORE reset at the same
* time to make sure the interface between MAC and
* the external PHY is reset.
*/
ctrl |= E1000_CTRL_PHY_RST;
/*
* Gate automatic PHY configuration by hardware on
* non-managed 82579
*/
if ((hw->mac_type == em_pch2lan) &&
!(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
em_gate_hw_phy_config_ich8lan(hw, TRUE);
}
}
em_get_software_flag(hw);
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
/* HW reset releases software_flag */
hw->sw_flag = 0;
msec_delay(20);
/* Ungate automatic PHY configuration on non-managed 82579 */
if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
!(E1000_READ_REG(hw, FWSM) & E1000_FWSM_FW_VALID)) {
msec_delay(10);
em_gate_hw_phy_config_ich8lan(hw, FALSE);
}
break;
default:
E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
break;
}
if (em_check_phy_reset_block(hw) == E1000_SUCCESS) {
if (hw->mac_type == em_pchlan) {
ret_val = em_hv_phy_workarounds_ich8lan(hw);
if (ret_val)
return ret_val;
}
else if (hw->mac_type == em_pch2lan) {
ret_val = em_lv_phy_workarounds_ich8lan(hw);
if (ret_val)
return ret_val;
}
}
/*
* After MAC reset, force reload of EEPROM to restore power-on
* settings to device. Later controllers reload the EEPROM
* automatically, so just wait for reload to complete.