diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..c779659 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,6 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +custom: ["https://www.paypal.com/donate/?hosted_button_id=N7HXKEL8VJ9CN"] diff --git a/.github/ISSUE_TEMPLATE/BUG_REPORT.yml b/.github/ISSUE_TEMPLATE/BUG_REPORT.yml new file mode 100644 index 0000000..09e0038 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/BUG_REPORT.yml @@ -0,0 +1,82 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +name: "Bug Report" +description: "Let us know about an unexpected error, a crash, or an incorrect behavior." +title: 'Title of your Bug Report' +labels: + - bug +assignees: + - boogermann +body: + - type: markdown + attributes: + value: | + Hi there, + + Thank you for opening an issue. Please note that we try to keep the issue tracker reserved for bug reports. + Make sure to [search for existing issues](https://github.com/opengateware/arcade-xevious/issues?q=label%3Abug) before filing a new one! + + - type: input + id: version + attributes: + label: Version (or build number) + placeholder: "1.0.0" + description: | + You can find the version in the about dialog. + + If you are not running the latest version, please try upgrading because your issue may have already been fixed. + validations: + required: true + + - type: textarea + id: steps + attributes: + label: Steps to reproduce + description: | + Please list the full steps required to reproduce the issue + placeholder: | + - Be precise + - Include exact data used during testing for easy reference + - The steps have to be in the exact order + - Mention pre-requisites when applicable + validations: + required: false + + - type: textarea + id: expected_behavior + attributes: + label: Expected Behavior + description: If you want to include screenshots, paste them into the markdown editor below or follow up with a separate comment. + placeholder: What were you expecting? + validations: + required: false + + - type: textarea + id: actual_behavior + attributes: + label: Actual Behavior + placeholder: What happened instead? + validations: + required: true + + - type: textarea + id: bug_context + attributes: + label: Additional Context + description: | + Are there anything atypical about your situation that we should know? + validations: + required: false + + - type: input + id: bug_firmware + attributes: + label: Opened Issues and Pull Requests + placeholder: "#1234" + description: | + Are there any other GitHub issues (open or closed) or Pull Requests that should be linked here? For example: #1234 + validations: + required: false diff --git a/.github/ISSUE_TEMPLATE/QUESTION.yml b/.github/ISSUE_TEMPLATE/QUESTION.yml new file mode 100644 index 0000000..2f22c4c --- /dev/null +++ b/.github/ISSUE_TEMPLATE/QUESTION.yml @@ -0,0 +1,29 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +name: "Question" +description: "Ask a question about the project." +title: 'Title of your Question' +labels: + - question +assignees: + - boogermann +body: + - type: markdown + attributes: + value: | + Hi there, + + Please note that we try to keep the issue tracker reserved for bug reports. + Make sure to [search for existing questions](https://github.com/opengateware/arcade-xevious/issues?q=label%3Aquestion) before filing a new one! + + - type: textarea + id: question + attributes: + label: Ask a question about Galaga Compatible Gateware IP Core + placeholder: | + Ask your question here! Please keep the questions related to the FPGA Core only. + validations: + required: true diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000..3113e01 --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,44 @@ + + + + + + +## What does this do / why do we need it? + + + +{Please write here} + +Fixes # (issue) + +## Type of change + + + +- [ ] Bug fix (non-breaking change which fixes an issue) +- [ ] New feature (non-breaking change which adds functionality) +- [ ] Breaking change (fix or feature that would cause existing functionality to not work as expected) +- [ ] This change requires a documentation update +- [ ] Coding style (indentation, etc) +- [ ] {Please write custom change here} + +## What should a reviewer look out for in this PR? + + + +{Please write here} + +## Additional Comments (if any) + +{Please write here} diff --git a/.github/workflows/build-pocket.yml b/.github/workflows/build-pocket.yml new file mode 100644 index 0000000..e90433a --- /dev/null +++ b/.github/workflows/build-pocket.yml @@ -0,0 +1,128 @@ +################################################################################ +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +################################################################################ +name: Build/Release +################################################################################ +# How to create a tag to launch the workflow +# git tag -a "0.1.0" -m "Release v0.1.0" +# git push origin --tags +################################################################################ +on: + push: + tags: + - "[0-9]+.[0-9]+.[0-9]+" +################################################################################ +jobs: + synthesis: + runs-on: ubuntu-latest + env: + CORE: xevious + DISPLAY_NAME: "Namco Xevious" + CATEGORY: arcade + AUTHOR: boogermann + TARGET: pocket + STAGE_FOLDER: staging + RELEASE_FOLDER: release + RECIPE_FOLDER: rom-recipes + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + RAETRO_WEBHOOK: ${{ secrets.RAETRO_WEBHOOK }} + FPGAGAMING_WEBHOOK: ${{ secrets.FPGAGAMING_WEBHOOK }} + + steps: + - name: "🧰 Checkout Repository" + uses: actions/checkout@v3 + + - name: "🏗️ Compile Design" + run: | + docker run --rm -v ${{ github.workspace }}:/build raetro/quartus:pocket \ + quartus_sh --flow compile projects/${CORE}_${TARGET}.qpf + + - name: "🟦 Staging Files for Release" + if: startsWith(github.ref, 'refs/tags/') + id: stage + run: | + ############################################################ + # Create Tags + ############################################################ + VERSION=${GITHUB_REF#refs/*/} + DATE=$(date +'%Y-%m-%d') + CORE_FOLDER=${AUTHOR}.${CORE} + RBF_FILE=${CORE}_${TARGET}.rbf + echo ::set-output name=VERSION::${VERSION} + echo ::set-output name=REPO::${CATEGORY}-${CORE} + echo ::set-output name=TITLE::${DISPLAY_NAME} + echo ::set-output name=RELEASE_FOLDER::${RELEASE_FOLDER} + echo ::set-output name=RELEASE_FILE::${CORE_FOLDER}_${TARGET}-${VERSION}.zip + echo ::set-output name=RECIPE_FILE::${CORE_FOLDER}_rom-recipes-${VERSION}.zip + ############################################################ + # Clear/Create Folders + ############################################################ + rm -rf ${STAGE_FOLDER} ${RELEASE_FOLDER} + mkdir -p ${STAGE_FOLDER} ${RELEASE_FOLDER} + ############################################################ + # Copy Packaging Folder + ############################################################ + cp -R pkg/${TARGET}/* ${STAGE_FOLDER} + ############################################################ + # Clear git and png source files + ############################################################ + find ./${STAGE_FOLDER} -type f \( -name "*.png*" -o -name "*.gitkeep*" \) -delete; + ############################################################ + # Update core.json Version and Release Date + ############################################################ + sed -i -e "s/<%- VERSION %>/${VERSION}/g" -e "s/<%- RELEASE_DATE %>/${DATE}/g" ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/core.json + ############################################################ + # Reverse Bitstream + ############################################################ + wget https://gist.githubusercontent.com/boogermann/fba1f59c87f9c8c9404cc68878b4eb1a/raw/7e93a3560902e0136dcb29fa6c41d06f06d78fb2/reverse_bits.c + g++ reverse_bits.c -o reverse_bits + ./reverse_bits projects/output_files/${RBF_FILE} ${STAGE_FOLDER}/Cores/${CORE_FOLDER}/bitstream.rbf_r + + - name: "📦 Create Distribution Files" + if: startsWith(github.ref, 'refs/tags/') + id: zip + run: | + pushd ./${STAGE_FOLDER} + zip -r ../${RELEASE_FOLDER}/${{ steps.stage.outputs.RELEASE_FILE }} . + popd + pushd ./pkg/${RECIPE_FOLDER} + zip -r ../../${RELEASE_FOLDER}/${{ steps.stage.outputs.RECIPE_FILE }} . + popd + + - name: "🚀 Create a new GitHub Release" + uses: softprops/action-gh-release@v0.1.14 + if: startsWith(github.ref, 'refs/tags/') + with: + name: Release v${{ steps.stage.outputs.VERSION }} + files: | + ${{ steps.stage.outputs.RELEASE_FOLDER }}/* + + - name: "📢 Send Discord Announcements" + if: startsWith(github.ref, 'refs/tags/') + run: | + declare -a StringArray=("${RAETRO_WEBHOOK}" "${FPGAGAMING_WEBHOOK}") + for webhook_url in ${StringArray[@]}; do + curl \ + -H "Content-Type: application/json" \ + -d '{ + "username": "OpenGateware", + "avatar_url": "https://avatars.githubusercontent.com/u/112050328", + "embeds": [{ + "color": 2021216, + "title": "A new core stable release is available for the Pocket", + "thumbnail": { "url": "https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/raw/master/docs/git-social.jpg" }, + "fields": [ + { "name": "Title", "value": "[${{ steps.stage.outputs.TITLE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/)", "inline": true }, + { "name": "Version", "value": "[${{ steps.stage.outputs.VERSION }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/tag/${{ steps.stage.outputs.VERSION }})", "inline": true }, + { "name": "Category", "value": "Arcade" }, + { "name": "Developer", "value": "[Boogermann](https://github.com/boogermann)" }, + { "name": "Download Core", "value": "[${{ steps.stage.outputs.RELEASE_FILE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/download/${{ steps.stage.outputs.VERSION }}/${{ steps.stage.outputs.RELEASE_FILE }})" }, + { "name": "Download ROM Recipes", "value": "[${{ steps.stage.outputs.RECIPE_FILE }}](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases/download/${{ steps.stage.outputs.VERSION }}/${{ steps.stage.outputs.RECIPE_FILE }})" }, + { "name": "Previous Releases", "value": "[https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases](https://github.com/opengateware/${{ steps.stage.outputs.REPO }}/releases)" } + ] + }] + }' \ + $webhook_url + done diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b184a5b --- /dev/null +++ b/.gitignore @@ -0,0 +1,68 @@ +db +greybox_tmp +hps_isw_handoff +incremental_db +output_files +PLLJ_PLLSPE_INFO.txt +simulation +vip +.qsys_edit +*_netlist +*_sim +*.bak +*.bsf +*.cdf +*.cmp +*.csv +*.done +*.f +*.pin +*.pof +*.ptf.* +*.qar +*.qarlog +*.qdf +*.qws +*.rbf +*.rbf_r +*.rpt +*.sip +*.sld +*.smsg +*.sof +*.sopc_builder +*.sopcinfo +*.spd +*.summary +*.txt +*.xml +*~ +**/.DS_Store +build_id.mif +build_id.v +c5_pin_model_dump.txt +cr_ie_info.json +# Gateman directories and files +!.gateman/* +!gateware.json +!/pkg/* +/pkg/**/*.rom +/pkg/**/*.zip +/staging/* +/release/* +# Editor directories and files +.vscode/* +!.vscode/extensions.json +.idea +*.suo +*.ntvs* +*.njsproj +*.sln +*.sw? + +# Pocket directories and files +!info.txt + +# ROMS Checklist +!checklist.sha1 +!checklist.md5 diff --git a/AUTHORS b/AUTHORS new file mode 100644 index 0000000..ce73b30 --- /dev/null +++ b/AUTHORS @@ -0,0 +1,24 @@ +##################################################################### +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: OTHER +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +##################################################################### +# Names should be added to this file as: +# Name or Organization +# eg: git log --pretty="%aN <%aE>%n%cN <%cE>" | sort | uniq +# Core Team Members +# Current project authors, maintainers and contributors. +##################################################################### +Marcus Andrade + +##################################################################### +# Partial list of people who authored and/or contributed code in +# other iterations or versions of the project. +# +# Thanks to all for their valuable +# time/code/hints/fixes/discussions and contributions. +##################################################################### +Alan Steremberg +Alexey Melnikov +Dar +Kuba Winnicki diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..745e604 --- /dev/null +++ b/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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But first, please read +. diff --git a/docs/CODE_OF_CONDUCT.md b/docs/CODE_OF_CONDUCT.md new file mode 100644 index 0000000..43aeed4 --- /dev/null +++ b/docs/CODE_OF_CONDUCT.md @@ -0,0 +1,64 @@ +# Code Of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as contributors and leaders pledge to making participation in our project and our community a harassment-free experience for everyone, regardless of age, body size, disability, ethnicity, gender identity and expression, level or type of experience, education, socio-economic status, nationality, personal appearance, race, religion, or sexual identity and orientation. +Note, however, that religion, political party, or other ideological affiliation provide no exemptions for the behavior we outline as unacceptable in this Code of Conduct. + +## Our Standards + +We are committed to providing a friendly, safe and welcoming environment for all. + +Examples of behavior that contributes to creating a positive environment include: + +- Be kind and courteous to others +- Using welcoming and inclusive language +- Being respectful of differing viewpoints and experiences +- Collaborating with other community members +- Gracefully accepting constructive criticism +- Focusing on what is best for the community +- Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +- The use of sexualized language or imagery and sexual attention or advances +- The use of inappropriate images, including in a community member's avatar +- The use of inappropriate language, including in a community member's nickname +- Any spamming, flaming, baiting or other attention-stealing behavior +- Excessive or unwelcome helping; answering outside the scope of the question asked +- Trolling, insulting/derogatory comments, and personal or political attacks +- Public or private harassment +- Publishing others' private information, such as a physical or electronic address, without explicit permission +- Other conduct which could reasonably be considered inappropriate + +The goal of the standards and moderation guidelines outlined here is to build and maintain a respectful community. We ask that you don’t just aim to be "technically unimpeachable", but rather try to be your best self. + +We value many things beyond technical expertise, including collaboration and supporting others within our community. Providing a positive experience for other community members can have a much more significant impact than simply providing the correct answer. + +## Our Responsibilities + +Project leaders are responsible for clarifying the standards of acceptable behavior and are expected to take appropriate and fair corrective action in response to any instances of unacceptable behavior. + +Project leaders respect all people who contribute through reporting issues, posting feature requests, updating documentation, metadata, artwork, manuals, videos, submitting pull requests or patches, and other activities. But also have the right and responsibility to remove, edit, or reject messages, comments, commits, code, issues, and other contributions that are not aligned to this Code of Conduct, or to ban temporarily or permanently any community member for other behaviors that they deem inappropriate, threatening, offensive, or harmful. + +## Scope + +This Code of Conduct and the enforcement policies listed above apply to all Rætro Community venues. This includes but is not limited to any community spaces (both public and private), the entire Rætro Discord server, and all Rætro associated GitHub repositories. Examples of Rætro Community spaces include but are not limited to meet-ups, audio chats on the Rætro Discord, or interaction at a conference. + +This Code of Conduct applies both within project spaces and in public spaces when an individual is representing the project or its community. As a community member, you are representing our community, and are expected to behave accordingly. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting the project team at or contact [community@raetro.org][conduct-email]. +All complaints will be reviewed and investigated and will result in a response that is deemed necessary and appropriate to the circumstances. +The project team is obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good faith may face temporary or permanent repercussions as determined by other members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html, and the Rust Code of Conduct, available at https://www.rust-lang.org/en-US/conduct.html and the Adafruit Community Code of Conduct, available at https://github.com/adafruit/Adafruit_Community_Code_of_Conduct. + +[homepage]: https://www.contributor-covenant.org +[conduct-email]: mailto:community@raetro.org diff --git a/docs/Manual and Schematics/Xevious - Operators Manual.pdf b/docs/Manual and Schematics/Xevious - Operators Manual.pdf new file mode 100644 index 0000000..b78c075 Binary files /dev/null and b/docs/Manual and Schematics/Xevious - Operators Manual.pdf differ diff --git a/docs/Manual and Schematics/Xevious - Schematics.pdf b/docs/Manual and Schematics/Xevious - Schematics.pdf new file mode 100644 index 0000000..e8cae1b Binary files /dev/null and b/docs/Manual and Schematics/Xevious - Schematics.pdf differ diff --git a/docs/Misc/Xevious - Cabinet.png b/docs/Misc/Xevious - Cabinet.png new file mode 100644 index 0000000..afbb374 Binary files /dev/null and b/docs/Misc/Xevious - Cabinet.png differ diff --git a/docs/Misc/atari-xevious-video-arcade-game-pcb_1.jpg b/docs/Misc/atari-xevious-video-arcade-game-pcb_1.jpg new file mode 100644 index 0000000..7dfc31e Binary files /dev/null and b/docs/Misc/atari-xevious-video-arcade-game-pcb_1.jpg differ diff --git a/docs/Misc/atari-xevious-video-arcade-game-pcb_2.jpg b/docs/Misc/atari-xevious-video-arcade-game-pcb_2.jpg new file mode 100644 index 0000000..91d89b5 Binary files /dev/null and b/docs/Misc/atari-xevious-video-arcade-game-pcb_2.jpg differ diff --git a/docs/Print/Xevious - Flyer (Atari).png b/docs/Print/Xevious - Flyer (Atari).png new file mode 100644 index 0000000..bb17e14 Binary files /dev/null and b/docs/Print/Xevious - Flyer (Atari).png differ diff --git a/docs/Print/Xevious - Flyer (Namco).png b/docs/Print/Xevious - Flyer (Namco).png new file mode 100644 index 0000000..d8bf342 Binary files /dev/null and b/docs/Print/Xevious - Flyer (Namco).png differ diff --git a/docs/Print/Xevious - Marquee.png b/docs/Print/Xevious - Marquee.png new file mode 100644 index 0000000..b57e369 Binary files /dev/null and b/docs/Print/Xevious - Marquee.png differ diff --git a/docs/README.md b/docs/README.md new file mode 100644 index 0000000..4940bed --- /dev/null +++ b/docs/README.md @@ -0,0 +1,112 @@ +[![Xevious Logo](xevious-logo.png)](#) + +--- + +[![Active Development](https://img.shields.io/badge/Maintenance%20Level-Actively%20Developed-brightgreen.svg)](#status-of-features) +[![Build](https://github.com/opengateware/arcade-xevious/actions/workflows/build-pocket.yml/badge.svg)](https://github.com/opengateware/arcade-xevious/actions/workflows/build-pocket.yml) +[![release](https://img.shields.io/github/release/opengateware/arcade-xevious.svg)](https://github.com/opengateware/arcade-xevious/releases) +[![license](https://img.shields.io/github/license/opengateware/arcade-xevious.svg?label=License&color=yellow)](#legal-notices) +[![issues](https://img.shields.io/github/issues/opengateware/arcade-xevious.svg?label=Issues&color=red)](https://github.com/opengateware/arcade-xevious/issues) +[![stars](https://img.shields.io/github/stars/opengateware/arcade-xevious.svg?label=Project%20Stars)](https://github.com/opengateware/arcade-xevious/stargazers) +[![discord](https://img.shields.io/discord/676418475635507210.svg?logo=discord&logoColor=white&label=Discord&color=5865F2)](https://chat.raetro.org) +[![Twitter Follow](https://img.shields.io/twitter/follow/marcusjordan?style=social)](https://twitter.com/marcusjordan) + +## Namco [Xevious] Compatible Gateware IP Core + +This Implementation of a compatible Xavious/Super Xavious arcade hardware in HDL is the work of [Dar](https://sourceforge.net/projects/darfpga/). + +## Overview + +Xevious (pronounced 'zeevious') is a vertically-scrolling shoot-em-up in which the player pilots the heavily-armed 'Solvalou' combat ship and must destroy the evil Xevious forces trying to take over the planet. The Solvalou is equipped with two weapon systems; the forwards-firing "air zapper" for shooting air-based enemies and 'blaster bombs', for destroying ground-based enemies. To enable accurate targetting of the air-to-ground blaster bombs, a white and blue targeting indicator is situated in front of the Solvalou. This flashes when an enemy is in its sights. + +## Technical specifications + +- **Main CPU:** Zilog Z80 @ 3.72 MHz +- **Graphics CPU:** Zilog Z80 @ 3.72 MHz +- **Sound CPU:** Zilog Z80 @ 3.72 MHz +- **Sound Chip:** Fujitsu MB8842, MB8843 and MB8844 @ 1.536 MHz +- **Resolution:** 288×224, 4096 colors +- **Display Box:** 384×264 @ 6.144 MHz +- **Aspect Ratio:** 9:7 +- **Orientation:** Vertical (90º) + +## Compatible Platforms + +- Analogue Pocket + +## Compatible Games + +> **ROMs NOT INCLUDED:** By using this gateware you agree to provide your own roms. + +| Officials | Status | +| :------------------------- | :----: | +| Xevious | ✅ | +| Super Xevious | ✅ | +| **HBMAME (HomeBrew MAME)** | | +| Gaous | ✅ | +| Xevious 2002 | ✅ | +| Xevious 2003 | ✅ | +| Xevious 2004 | ✅ | +| Xevious 2005 | ✅ | +| Xevious Black | ✅ | +| **Bootlegs** | | +| Battles (set 2) | ✅ | +| Xevios | ✅ | + +### ROM Instructions + +1. Download and Install [ORCA](https://github.com/opengateware/tools-orca/releases/latest) (Open ROM Conversion Assistant) +2. Download the [ROM Recipes](https://github.com/opengateware/arcade-xevious/releases/latest) and extract to your computer. +3. Copy the required MAME `.zip` file(s) into the `roms` folder. +4. Inside the `tools` folder execute the script related to your system. + 1. **Windows:** right click `make_roms.ps1` and select `Run with Powershell`. + 2. **Linux and MacOS:** run script `make_roms.sh`. +5. After the conversion is completed, copy the `Assets` folder to the Root of your SD Card. +6. **Optional:** an `.md5` file is included to verify if the hash of the ROMs are valid. (eg: `md5sum -c checklist.md5`) + +> **Note:** Make sure your `.rom` files are in the `Assets/xevious/common` directory. + +## Status of Features + +> **WARNING**: This repository is in active development. There are no guarantees about stability. Breaking changes might occur until a stable release is made and announced. + +- [ ] Add Second Player +- [ ] Dip Switches +- [ ] Pause +- [ ] Hi-Score Save + +## Known Issues + +- A completely random bug seems to occur where you insert a coin and the game starts as 2 players, the ship will also get stuck to the bottom left of the screen. Pressing start gets back to normal. + +## Credits and acknowledgment + +- [Alan Steremberg](https://github.com/alanswx) +- [Alexey Melnikov](https://github.com/sorgelig) +- [Daniel Wallner](https://opencores.org/projects/t80) +- [Dar](https://github.com/darfpga) +- [Kuba Winnicki](https://github.com/blackwine) +- [Peter Wendrich](https://github.com/pwsoft) + +## Powered by Open-Source Software + +This project borrowed and use code from several other projects. A great thanks to their efforts! + +| Modules | Copyright/Developer | +| :----------------------------- | :---------------------- | +| [Data Loader] | 2022 (c) Adam Gastineau | +| [T80] | 2001 (c) Daniel Wallner | +| [Xevious RTL] | 2017 (c) Dar | + +## Legal Notices + +Xevious/Super Xevious © 1983-1984 NAMCO LTD. All rights reserved. Xevious is a trademark of BANDAI NAMCO ENTERTAINMENT INC. +All other trademarks, logos, and copyrights are property of their respective owners. + +The authors and contributors or any of its maintainers are in no way associated with or endorsed by Bandai Namco Entertainment Inc. + +[Data Loader]: https://github.com/agg23/analogue-pocket-utils +[T80]: https://opencores.org/projects/t80 +[Xevious RTL]: https://github.com/MiSTer-devel/Arcade-Xevious_MiSTer/tree/master/rtl + +[Xevious]: https://en.wikipedia.org/wiki/Xevious diff --git a/docs/git-social.jpg b/docs/git-social.jpg new file mode 100644 index 0000000..b89d913 Binary files /dev/null and b/docs/git-social.jpg differ diff --git a/docs/xevious-logo.png b/docs/xevious-logo.png new file mode 100644 index 0000000..cc42002 Binary files /dev/null and b/docs/xevious-logo.png differ diff --git a/gateware.json b/gateware.json new file mode 100644 index 0000000..4cf3475 --- /dev/null +++ b/gateware.json @@ -0,0 +1,37 @@ +{ + "name": "xevious", + "displayName": "xevious", + "description": "Namco Xevious Compatible Gateware IP Core for FPGA", + "author": "boogermann", + "version": "0.1.0", + "license": "GPL-3.0-or-later", + "repository": "https://github.com/opengateware/arcade-xevious", + "keywords": [ + "namco", + "xevious", + "vertical", + "arcade", + "1983", + "ecosystem:raetro", + "ecosystem:gateman" + ], + "scripts": { + "verilator": "echo \"Error: no simulation specified\" && exit 1" + }, + "hardware": { + "id": "xevious", + "name": "Xevious", + "year": 1983, + "manufacturer": "Namco" + }, + "platforms": { + "pocket": "1.1.0" + }, + "modules": { + "cpu-mb88xx": "0.3.0", + "cpu-t80": "2.4.2", + "pocket-dataloader": "1.0.0", + "pocket-i2s": "1.0.0", + "pocket-joypad": "1.0.0" + } +} \ No newline at end of file diff --git a/modules/cpu-mb88xx/index.qip b/modules/cpu-mb88xx/index.qip new file mode 100644 index 0000000..1d47a5f --- /dev/null +++ b/modules/cpu-mb88xx/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mb88.vhd"] diff --git a/modules/cpu-mb88xx/mb88.vhd b/modules/cpu-mb88xx/mb88.vhd new file mode 100644 index 0000000..5cd49e0 --- /dev/null +++ b/modules/cpu-mb88xx/mb88.vhd @@ -0,0 +1,603 @@ +--------------------------------------------------------------------------------- +-- mb88 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- +-- Version 0.3 -- 28/02/2017 -- +-- fixed instruction JMP (0xC0..0xFF) let r_pa be incremented when r_pc = 0x3F +-- +-- Version 0.2 -- 26/02/2017 -- +-- corrected r_stf for tstR instruction (0x24) +-- corrected r_stf for tbit instruction (0x38-0x3B) +-- +-- Version 0.1 -- 25/02/2017 -- +-- outO instruction write to ol,oh depending on r_cf +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- + +-- Todo : Timer, Serial + +-- Features : + +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity mb88 is +port( + clock : in std_logic; + ena : in std_logic; + reset_n : in std_logic; + + r0_port_in : in std_logic_vector(3 downto 0); + r1_port_in : in std_logic_vector(3 downto 0); + r2_port_in : in std_logic_vector(3 downto 0); + r3_port_in : in std_logic_vector(3 downto 0); + r0_port_out : out std_logic_vector(3 downto 0); + r1_port_out : out std_logic_vector(3 downto 0); + r2_port_out : out std_logic_vector(3 downto 0); + r3_port_out : out std_logic_vector(3 downto 0); + k_port_in : in std_logic_vector(3 downto 0); + ol_port_out : out std_logic_vector(3 downto 0); + oh_port_out : out std_logic_vector(3 downto 0); + p_port_out : out std_logic_vector(3 downto 0); + + stby_n : in std_logic; + tc_n : in std_logic; + irq_n : in std_logic; + sc_in_n : in std_logic; + si_n : in std_logic; + sc_out_n : out std_logic; + so_n : out std_logic; + to_n : out std_logic; + + rom_addr : out std_logic_vector(10 downto 0); + rom_data : in std_logic_vector( 7 downto 0) + + ); +end mb88; + +architecture struct of mb88 is + + signal reset : std_logic; + signal clock_n : std_logic; + + signal ram_addr : std_logic_vector(6 downto 0); + signal ram_we : std_logic; + signal ram_di : std_logic_vector(3 downto 0); + signal ram_do : std_logic_vector(3 downto 0); + + signal r_pc : std_logic_vector(5 downto 0) := (others=>'0'); + signal r_pa : std_logic_vector(4 downto 0) := (others=>'0'); + signal r_si : std_logic_vector(1 downto 0) := (others=>'0'); + signal r_a : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_x : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_y : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_stf : std_logic := '1'; + signal r_zf : std_logic := '0'; + signal r_cf : std_logic := '0'; + signal r_vf : std_logic := '0'; + signal r_sf : std_logic := '0'; + signal r_nf : std_logic := '0'; + + signal r_pio : std_logic_vector(7 downto 0) := (others=>'0'); + signal r_th : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_tl : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_tp : std_logic_vector(5 downto 0) := (others=>'0'); + signal r_ctr : std_logic_vector(5 downto 0) := (others=>'0'); + + signal r_sb : std_logic_vector(3 downto 0) := (others=>'0'); + signal r_sbcnt : std_logic_vector(3 downto 0) := (others=>'0'); + + signal interrupt_pending : std_logic := '0'; + signal timer_interrupt_pending : std_logic := '0'; + signal irq_n_r : std_logic := '0'; + + signal tc_n_r : std_logic := '0'; + + subtype stack_size is integer range 0 to 3; + type stack_def is array(stack_size) of std_logic_vector(15 downto 0); + signal stack : stack_def := (others=>(others=>'0')); + + subtype ram_size is integer range 0 to 127; + type ram_def is array(ram_size) of std_logic_vector(3 downto 0); + signal ram : ram_def := (others=>(others=>'0')); + + signal single_byte_op : std_logic := '1'; + signal op_code : std_logic_vector(7 downto 0) := X"00"; + + signal a_p1 : std_logic_vector(3 downto 0); + signal a_p1_z : std_logic; + signal a_p1_c : std_logic; + signal a_m1 : std_logic_vector(3 downto 0); + signal a_m1_z : std_logic; + signal a_m1_c : std_logic; + signal y_p1 : std_logic_vector(3 downto 0); + signal y_p1_z : std_logic; + signal y_p1_c : std_logic; + signal y_m1 : std_logic_vector(3 downto 0); + signal y_m1_z : std_logic; + signal y_m1_c : std_logic; + signal m_p1 : std_logic_vector(3 downto 0); + signal m_p1_z : std_logic; + signal m_p1_c : std_logic; + signal m_m1 : std_logic_vector(3 downto 0); + signal m_m1_z : std_logic; + signal m_m1_c : std_logic; + signal adc : std_logic_vector(4 downto 0); + signal adc_z : std_logic; + signal adc_c : std_logic; + signal sbc : std_logic_vector(4 downto 0); + signal sbc_z : std_logic; + signal sbc_c : std_logic; + signal cma : std_logic_vector(4 downto 0); + signal cma_z : std_logic; + signal cma_c : std_logic; + signal a_pim : std_logic_vector(4 downto 0); + signal a_pim_z: std_logic; + signal a_pim_c: std_logic; + signal im_my : std_logic_vector(4 downto 0); + signal im_my_z: std_logic; + signal im_my_c: std_logic; + signal im_ma : std_logic_vector(4 downto 0); + signal im_ma_z: std_logic; + signal im_ma_c: std_logic; + signal a_and_m : std_logic_vector(3 downto 0); + signal a_and_m_z : std_logic; + signal a_or_m : std_logic_vector(3 downto 0); + signal a_or_m_z : std_logic; + signal a_xor_m : std_logic_vector(3 downto 0); + signal a_xor_m_z : std_logic; + signal nega : std_logic_vector(3 downto 0); + signal nega_z : std_logic; + signal rola : std_logic_vector(3 downto 0); + signal rola_z : std_logic; + signal rora : std_logic_vector(3 downto 0); + signal rora_z : std_logic; + signal do_da : std_logic; + signal daa : std_logic_vector(3 downto 0); + signal daa_z : std_logic; + signal daa_c : std_logic; + signal das : std_logic_vector(3 downto 0); + signal das_z : std_logic; + signal das_c : std_logic; + signal dca : std_logic_vector(3 downto 0); + signal dca_z : std_logic; + signal dca_c : std_logic; + signal x_z : std_logic; + signal y_z : std_logic; + signal tl_z : std_logic; + signal th_z : std_logic; + signal sb_z : std_logic; + signal k_port_in_z : std_logic; + signal r0_port_in_z : std_logic; + signal r1_port_in_z : std_logic; + signal r2_port_in_z : std_logic; + signal r3_port_in_z : std_logic; + signal sel_bit_y : std_logic_vector(3 downto 0); + + signal m_set_bit : std_logic_vector(3 downto 0); + signal m_clr_bit : std_logic_vector(3 downto 0); + signal m_tst_bit : std_logic; + + signal mem : std_logic_vector(3 downto 0); + signal mem_z : std_logic; + signal imm_x7_z : std_logic; + signal imm_xF_z : std_logic; + +begin + +clock_n <= not clock; +reset <= not reset_n; + +rom_addr <= r_pa & r_pc; + +ram_addr <= X"0" & rom_data(2 downto 0) when ((rom_data >= X"50") and (rom_data <= X"57")) else r_x(2 downto 0) & r_y; + +ram_we <= '1' when(( (rom_data = X"1D") or (rom_data = X"1A") or + (rom_data = X"0A") or (rom_data = X"0B") or + (rom_data = X"2A") or + (rom_data = X"19") or (rom_data = X"09") or + ((rom_data >= X"30") and (rom_data <= X"37") ) or + ((rom_data >= X"50") and (rom_data <= X"57") ) + ) and (single_byte_op = '1')and ena = '1') + else '0'; + +with rom_data select +ram_di <= r_a when X"1D", r_a when X"1A", + r_a when X"0A", r_a when X"0B", + r_sb when X"2A", + m_m1 when X"19", m_p1 when X"09", + m_set_bit when X"30", m_clr_bit when X"34", + m_set_bit when X"31", m_clr_bit when X"35", + m_set_bit when X"32", m_clr_bit when X"36", + m_set_bit when X"33", m_clr_bit when X"37", + r_a when X"50", r_y when X"54", + r_a when X"51", r_y when X"55", + r_a when X"52", r_y when X"56", + r_a when X"53", r_y when X"57", + X"A" when others; + + +a_p1 <= r_a + X"1"; +a_p1_z <= '1' when a_p1 = X"0" else '0'; +a_p1_c <= '1' when a_p1 = X"0" else '0'; + +a_m1 <= r_a - X"1"; +a_m1_z <= '1' when a_m1 = X"0" else '0'; +a_m1_c <= '1' when a_m1 = X"F" else '0'; + +y_p1 <= r_y + X"1"; +y_p1_z <= '1' when y_p1 = X"0" else '0'; +y_p1_c <= '1' when y_p1 = X"0" else '0'; + +y_m1 <= r_y - X"1"; +y_m1_z <= '1' when y_m1 = X"0" else '0'; +y_m1_c <= '1' when y_m1 = X"F" else '0'; + +m_p1 <= ram_do + X"1"; +--m_p1_z <= '1' when m_p1 = X"0" else '0'; +--m_p1_c <= '1' when m_p1 = X"0" else '0'; + +m_m1 <= ram_do - X"1"; +--m_m1_z <= '1' when m_m1 = X"0" else '0'; +--m_m1_c <= '1' when m_m1 = X"F" else '0'; + +with rom_data(2 downto 0) select +m_set_bit <= ram_do or X"1" when "000", + ram_do or X"2" when "001", + ram_do or X"4" when "010", + ram_do or X"8" when others; + +with rom_data(2 downto 0) select +m_clr_bit <= ram_do and not X"1" when "000", + ram_do and not X"2" when "001", + ram_do and not X"4" when "010", + ram_do and not X"8" when others; + +m_tst_bit <= ram_do(to_integer(unsigned(rom_data(1 downto 0)))); + +rola <= r_a(2 downto 0) & r_cf; +rola_z <= '1' when rola = X"0" else '0'; + +rora <= r_cf & r_a(3 downto 1); +rora_z <= '1' when rora = X"0" else '0'; + +nega <= not(r_a) + X"1"; +nega_z <= '1' when nega = X"0" else '0'; + +adc <= ('0'&ram_do) + ('0'&r_a) + ("0000"&r_cf); +adc_z <= '1' when adc(3 downto 0) = X"0" else '0'; +adc_c <= '1' when adc(4) = '1' else '0'; + +sbc <= ('0'&ram_do) - ('0'&r_a) - ("0000"&r_cf); +sbc_z <= '1' when sbc(3 downto 0) = X"0" else '0'; +sbc_c <= '1' when sbc(4) = '1' else '0'; + +cma <= ('0'&ram_do) - ('0'&r_a); +cma_z <= '1' when cma(3 downto 0) = X"0" else '0'; +cma_c <= '1' when cma(4) = '1' else '0'; + +a_pim <= ('0'&rom_data(3 downto 0)) + ('0'&r_a); +a_pim_z <= '1' when a_pim(3 downto 0) = X"0" else '0'; +a_pim_c <= '1' when a_pim(4) = '1' else '0'; + +im_my <= ('0'&rom_data(3 downto 0)) - ('0'&r_y); +im_my_z <= '1' when im_my(3 downto 0) = X"0" else '0'; +im_my_c <= '1' when im_my(4) = '1' else '0'; + +im_ma <= ('0'&rom_data(3 downto 0)) - ('0'&r_a); +im_ma_z <= '1' when im_ma(3 downto 0) = X"0" else '0'; +im_ma_c <= '1' when im_ma(4) = '1' else '0'; + +a_and_m <= r_a and ram_do; +a_and_m_z <= '1' when a_and_m = X"0" else '0'; + +a_or_m <= r_a or ram_do; +a_or_m_z <= '1' when a_or_m = X"0" else '0'; + +a_xor_m <= r_a xor ram_do; +a_xor_m_z <= '1' when a_xor_m = X"0" else '0'; + +do_da <= '1' when (r_a > X"9") or (r_cf = '1') else '0'; + +daa <= r_a + X"6"; +daa_z <= '1' when daa = X"0" else '0'; +daa_c <= '1' when r_a > X"9" else '0'; + +das <= r_a + X"A"; +das_z <= '1' when das = X"0" else '0'; +das_c <= '1' when r_a > X"5" else '0'; + +dca <= r_a + X"F"; +dca_z <= '1' when dca = X"0" else '0'; +dca_c <= '1' when dca = X"F" else '0'; + +x_z <= '1' when r_x = X"0" else '0'; +y_z <= '1' when r_y = X"0" else '0'; +tl_z <= '1' when r_tl = X"0" else '0'; +th_z <= '1' when r_th = X"0" else '0'; +sb_z <= '1' when r_sb = X"0" else '0'; +k_port_in_z <= '1' when k_port_in = X"0" else '0'; +r0_port_in_z <= '1' when r0_port_in = X"0" else '0'; +r1_port_in_z <= '1' when r1_port_in = X"0" else '0'; +r2_port_in_z <= '1' when r2_port_in = X"0" else '0'; +r3_port_in_z <= '1' when r3_port_in = X"0" else '0'; + +with r_y(1 downto 0) select +sel_bit_y <= "0001" when "00", + "0010" when "01", + "0100" when "10", + "1000" when others; + +imm_x7_z <= '1' when rom_data(2 downto 0) = "000" else '0'; +imm_xF_z <= '1' when rom_data(3 downto 0) = "0000" else '0'; + +process (clock_n) -- register data before memory value update at middle cycle +begin + if rising_edge(clock_n) then + mem <= ram_do; + if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if; + if m_p1 = X"0" then m_p1_z <= '1'; else m_p1_z <= '0'; end if; + if m_p1 = X"0" then m_p1_c <= '1'; else m_p1_c <= '0'; end if; + if m_m1 = X"0" then m_m1_z <= '1'; else m_m1_z <= '0'; end if; + if m_m1 = X"F" then m_m1_c <= '1'; else m_m1_c <= '0'; end if; +end if; +end process; + +process (clock) +begin + if rising_edge(clock) then +-- mem <= ram_do; +-- if ram_do = X"0" then mem_z <= '1'; else mem_z <= '0'; end if; + irq_n_r <= irq_n; + r_nf <= not irq_n; + if irq_n = '0' and irq_n_r = '1' and r_pio(2) = '1' then + interrupt_pending <= '1'; + end if; + + if reset = '1' then + r_pc <= (others=>'0'); + r_pa <= (others=>'0'); + r_si <= (others=>'0'); + r_a <= (others=>'0'); + r_x <= (others=>'0'); + r_y <= (others=>'0'); + r_stf <= '1'; + r_zf <= '0'; + r_cf <= '0'; + r_vf <= '0'; + r_sf <= '0'; + r_nf <= '0'; + r_pio <= (others=>'0'); + r_th <= (others=>'0'); + r_tl <= (others=>'0'); + r_tp <= (others=>'0'); + r_ctr <= (others=>'0'); + r_sb <= (others=>'0'); + r_sbcnt <= (others=>'0'); + interrupt_pending <= '0'; + timer_interrupt_pending <= '0'; + stack <= (others=>(others=>'0')); + single_byte_op <= '1'; + else + tc_n_r <= tc_n; + if (tc_n = '0' and tc_n_r = '1' and r_pio(6) = '1') or + (ena = '1' and r_pio(7) = '1') + then + r_tl <= r_tl + 1; + if r_tl = X"F" then + r_th <= r_th + 1; + if r_th = X"F" then + if r_pio(1) = '1' then + timer_interrupt_pending <= '1'; + end if; + r_vf <= '1'; + end if; + end if; + end if; + + if ena = '1' then + + op_code <= rom_data; + single_byte_op <= '1'; + + if r_pc = "111111" then + r_pc <= "000000"; + r_pa <= r_pa + "0001"; + else + r_pc <= r_pc + "000001"; + end if; + + if single_byte_op = '1' then + if interrupt_pending = '1' or timer_interrupt_pending = '1' then + stack(to_integer(unsigned(r_si)))(13 downto 0) <= (r_cf & r_zf & r_stf & r_pa & r_pc); + r_pc <= "000010"; + r_pa <= "00000"; + r_si <= r_si + "01"; + if interrupt_pending = '1' then + interrupt_pending <= '0'; + elsif timer_interrupt_pending = '1' then + timer_interrupt_pending <= '0'; + end if; + else -- no irq + case rom_data is + when X"00" => r_stf <='1'; -- nop + when X"01" => r_stf <='1'; -- outO portO <- A //!PLA todo + if r_cf = '0' then ol_port_out <= r_a; end if; + if r_cf = '1' then oh_port_out <= r_a; end if; + when X"02" => r_stf <='1'; p_port_out <= r_a; -- outP portP <- A + when X"03" => r_stf <='1'; -- outR(Y) portR(Y) <- A + if r_y = X"0" then r0_port_out <= r_a; end if; + if r_y = X"1" then r1_port_out <= r_a; end if; + if r_y = X"2" then r2_port_out <= r_a; end if; + if r_y = X"3" then r3_port_out <= r_a; end if; + when X"04" => r_stf <='1'; r_y <= r_a; -- tay Y <- A + when X"05" => r_stf <='1'; r_th <= r_a; -- tath TH <- A + when X"06" => r_stf <='1'; r_tl <= r_a; -- tatl TL <- A + when X"07" => r_stf <='1'; r_sb <= r_a; -- tas SB <- A + when X"08" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- icy Y <- Y+1 + when X"09" => r_stf <= not m_p1_c; r_zf <= m_p1_z; -- icm M[X,Y] <- M[X,Y]+1 + when X"0A" => r_stf <= not y_p1_c; r_y <= y_p1; r_zf <= y_p1_z; -- stic M[X,Y] <- A; Y <- Y+1 + when X"0B" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- x A <- M[X,Y]; M[X,Y] <- A + when X"0C" => r_stf <= not r_a(3); r_a <= rola; r_zf <= rola_z; r_cf <= r_a(3); -- rol + when X"0D" => r_stf <='1'; r_a <= mem; r_zf <= mem_z; -- l A <- M[X,Y]; + when X"0E" => r_stf <= not adc_c; r_a <= adc(3 downto 0); r_zf <= adc_z; r_cf <= adc_c; -- adc A <- M[X,Y]+A+CF; + when X"0F" => r_stf <= not a_and_m_z; r_a <= a_and_m; r_zf <= a_and_m_z; -- and A <- A & M[X,Y]; + when X"10" => + if do_da = '1' then r_stf <= not daa_c; r_a <= daa; r_cf <= daa_c; -- daa A <- A + 6 ; si A>9 or CF + else r_stf <= '1'; r_cf <= '0'; end if; + when X"11" => + if do_da = '1' then r_stf <= not das_c; r_a <= das; r_cf <= das_c; -- das A <- A + 10; si A>9 or CF + else r_stf <= '1'; r_cf <= '0'; end if; + when X"12" => r_stf <='1'; r_a <= k_port_in; r_zf <= k_port_in_z; -- inK A <- K + when X"13" => r_stf <='1'; -- inR A <- R(Y) + if r_y = X"0" then r_a <= r0_port_in; r_zf <= r0_port_in_z; end if; + if r_y = X"1" then r_a <= r1_port_in; r_zf <= r1_port_in_z; end if; + if r_y = X"2" then r_a <= r2_port_in; r_zf <= r2_port_in_z; end if; + if r_y = X"3" then r_a <= r3_port_in; r_zf <= r3_port_in_z; end if; + when X"14" => r_stf <='1'; r_a <= r_y; r_zf <= y_z; -- tya A <- Y + when X"15" => r_stf <='1'; r_a <= r_th; r_zf <= th_z; -- ttha A <- TH + when X"16" => r_stf <='1'; r_a <= r_tl; r_zf <= tl_z; -- ttla A <- TH + when X"17" => r_stf <='1'; r_a <= r_sb; r_zf <= sb_z; -- tsa A <- SB + when X"18" => r_stf <= not y_m1_c; r_y <= y_m1; -- dcy Y <- Y-1 + when X"19" => r_stf <= not m_m1_c; r_zf <= m_m1_z; -- dcm M[X,Y] <- M[X,Y]-1 + when X"1A" => r_stf <= not y_m1_c; r_y <= y_m1; r_zf <= y_m1_z; -- stdc M[X,Y] <- A; Y <- Y-1 + when X"1B" => r_stf <='1'; r_a <= r_x; r_x <= r_a; r_zf <= x_z; -- xx A <- X, X <- A + when X"1C" => r_stf <= not r_a(0); r_a <= rora; r_zf <= rora_z; r_cf <= r_a(0); -- ror + when X"1D" => r_stf <='1'; -- st M[X,Y] <- A + when X"1E" => r_stf <= not sbc_c; r_a <= sbc(3 downto 0); r_zf <= sbc_z; r_cf <= sbc_c; -- sbc A <- M[X,Y]-A-CF; + when X"1F" => r_stf <= not a_or_m_z; r_a <= a_or_m; r_zf <= a_or_m_z; -- or A <- A | M[X,Y]; + when X"20" => r_stf <='1'; -- setR + if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in or sel_bit_y ); end if; + if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in or sel_bit_y ); end if; + when X"21" => r_stf <='1'; r_cf <= '1'; -- setCF + when X"22" => r_stf <='1'; -- clrR + if r_y(3 downto 2) = "00" then r0_port_out <= (r0_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "01" then r1_port_out <= (r1_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "10" then r2_port_out <= (r2_port_in and not sel_bit_y ); end if; + if r_y(3 downto 2) = "11" then r3_port_out <= (r3_port_in and not sel_bit_y ); end if; + when X"23" => r_stf <='1'; r_cf <= '0'; -- clrCF + when X"24" => -- tstR + if r_y(3 downto 2) = "00" then r_stf <= not r0_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "01" then r_stf <= not r1_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "10" then r_stf <= not r2_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + if r_y(3 downto 2) = "11" then r_stf <= not r3_port_in(to_integer(unsigned(r_y(1 downto 0)))); end if; + when X"25" => r_stf <= not r_nf; -- tsti (interrupt) + when X"26" => r_stf <= not r_vf; r_vf <= '0'; -- tstv (timer overflow) + when X"27" => r_stf <= not r_sf; r_sf <= '0'; -- tsts (serial) + when X"28" => r_stf <= not r_cf; -- tstc (CF) + when X"29" => r_stf <= not r_zf; -- tstz (ZF) + when X"2A" => r_stf <= '1'; r_zf <= sb_z; -- sts M[X,Y] <- SB + when X"2B" => r_stf <= '1'; r_sb <= mem; r_zf <= mem_z; -- ls SB <- M[X,Y] + when X"2C" => r_stf <= '1'; -- rts + r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6); + r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0); + r_si <= r_si - "01"; + when X"2D" => r_stf <= not nega_z; r_a <= nega; -- negA A <- -A + when X"2E" => r_stf <= not cma_z; r_zf <= cma_z; r_cf <= cma_c; -- c M[X,Y]-A ?= + when X"2F" => r_stf <= not a_xor_m_z; r_a <= a_xor_m; r_zf <= a_xor_m_z;-- eor A <- A xor M[X,Y]; + when X"30" | X"31" | X"32" | X"33" => r_stf <='1'; -- sbit M[X,Y](op&3) <- 1 + when X"34" | X"35" | X"36" | X"37" => r_stf <='1'; -- rbit M[X,Y](op&3) <- 0 + when X"38" | X"39" | X"3A" | X"3B" => r_stf <= not m_tst_bit; -- tbit M[X,Y](op&3) == 1 + when X"3C" => -- rti + r_pa <= stack(to_integer(unsigned(r_si-"01")))(10 downto 6); + r_pc <= stack(to_integer(unsigned(r_si-"01")))( 5 downto 0); + r_stf <= stack(to_integer(unsigned(r_si-"01")))(11); + r_zf <= stack(to_integer(unsigned(r_si-"01")))(12); + r_cf <= stack(to_integer(unsigned(r_si-"01")))(13); + r_si <= r_si - "01"; + when X"3D" => single_byte_op <= '0'; -- jpa + when X"3E" => single_byte_op <= '0'; -- en + when X"3F" => single_byte_op <= '0'; -- dis + when X"40" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"1"); -- setd RO(op&3) <- 1 + when X"41" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"2"); -- setd RO(op&3) <- 1 + when X"42" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"4"); -- setd RO(op&3) <- 1 + when X"43" => r_stf <= '1'; r0_port_out <= (r0_port_in or X"8"); -- setd RO(op&3) <- 1 + when X"44" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"1"); -- setd RO(op&3) <- 0 + when X"45" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"2"); -- setd RO(op&3) <- 0 + when X"46" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"4"); -- setd RO(op&3) <- 0 + when X"47" => r_stf <= '1'; r0_port_out <= (r0_port_in and not X"8"); -- setd RO(op&3) <- 0 + when X"48" | X"49" | X"4A" | X"4B" => -- tstd R2(op&3) ?= + r_stf <= not r2_port_in(to_integer(unsigned(rom_data(1 downto 0)))); + when X"4C" | X"4D" | X"4E" | X"4F" => -- tba A(op&3) ?= + r_stf <= not r_a(to_integer(unsigned(rom_data(1 downto 0)))); + when X"50" | X"51" | X"52" | X"53" => -- xd A <-> M[0,op&3] + r_stf <= '1'; r_a <= mem; r_zf <= mem_z; + when X"54" | X"55" | X"56" | X"57" => -- xyd Y <-> M[0,op&3] + r_stf <= '1'; r_y <= mem; r_zf <= mem_z; + when X"58" | X"59" | X"5A" | X"5B" | X"5C" | X"5D" | X"5E" | X"5F" => -- lxi imm (op&7) + r_stf <='1'; r_x <= '0' & rom_data(2 downto 0); r_zf <= imm_x7_z; + when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr + single_byte_op <= '0'; + when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl addr + single_byte_op <= '0'; + when X"70" | X"71" | X"72" | X"73" | X"74" | X"75" | X"76" | X"77" | + X"78" | X"79" | X"7A" | X"7B" | X"7C" | X"7D" | X"7E" | X"7F" => -- ai A <- A+imm (op&F) + r_stf <= not a_pim_c; r_a <= a_pim(3 downto 0); r_zf <= a_pim_z; r_cf <= a_pim_c; + when X"80" | X"81" | X"82" | X"83" | X"84" | X"85" | X"86" | X"87" | + X"88" | X"89" | X"8A" | X"8B" | X"8C" | X"8D" | X"8E" | X"8F" => -- lyi Y <- imm (op&F) + r_stf <='1'; r_y <= rom_data(3 downto 0); r_zf <= imm_xF_z; + when X"90" | X"91" | X"92" | X"93" | X"94" | X"95" | X"96" | X"97" | + X"98" | X"99" | X"9A" | X"9B" | X"9C" | X"9D" | X"9E" | X"9F" => -- li A <- imm (op&F) + r_stf <='1'; r_a <= rom_data(3 downto 0); r_zf <= imm_xF_z; + when X"A0" | X"A1" | X"A2" | X"A3" | X"A4" | X"A5" | X"A6" | X"A7" | + X"A8" | X"A9" | X"AA" | X"AB" | X"AC" | X"AD" | X"AE" | X"AF" => -- cyi imm - Y ?= + r_stf <= not im_my_z; r_zf <= im_my_z; r_cf <= im_my_c; + when X"B0" | X"B1" | X"B2" | X"B3" | X"B4" | X"B5" | X"B6" | X"B7" | + X"B8" | X"B9" | X"BA" | X"BB" | X"BC" | X"BD" | X"BE" | X"BF" => -- ci imm - A ?= + r_stf <= not im_ma_z; r_zf <= im_ma_z; r_cf <= im_ma_c; + when others => r_stf <='1'; -- jmp addr if ST (op_code C0..FF) + if r_stf = '1' then r_pc <= rom_data(5 downto 0); end if; -- (let r_pa be incremented when r_pc = 0x3F) + end case; + end if ; + else -- 2 bytes op_code, rom_data = 2nd byte + case op_code is + when X"3D" => r_stf <='1'; r_pa <= rom_data(4 downto 0); r_pc <= r_a & "00"; -- jpa PA <- data&0x1f; PC <- A*4 + when X"3E" => r_stf <='1'; r_pio <= r_pio or rom_data; -- en PIO <- PIO or imm data + when X"3F" => r_stf <='1'; r_pio <= r_pio and not rom_data; -- dis PIO <- PIO and not imm data + when X"60" | X"61" | X"62" | X"63" | X"64" | X"65" | X"66" | X"67" => -- call addr if ST + r_stf <= '1'; + if r_stf = '1' then + stack(to_integer(unsigned(r_si)))(10 downto 0) <= (r_pa & r_pc) + '1'; + r_pc <= rom_data(5 downto 0); + r_pa <= op_code(2 downto 0) & rom_data(7 downto 6); + r_si <= r_si + "01"; + end if; + when X"68" | X"69" | X"6A" | X"6B" | X"6C" | X"6D" | X"6E" | X"6F" => -- jpl if ST + r_stf <= '1'; + if r_stf = '1' then + r_pc <= rom_data(5 downto 0); + r_pa <= op_code(2 downto 0) & rom_data(7 downto 6); + end if; + when others => r_stf <='1'; + end case; + end if; + + end if; + end if; + end if; +end process; + +-- RAM +process(clock_n) +begin + if rising_edge(clock_n) then + if ram_we = '1' then + ram(to_integer(unsigned(ram_addr))) <= ram_di; + end if; + end if; +end process; + +ram_do <= ram(to_integer(unsigned(ram_addr))); + +end struct; diff --git a/modules/cpu-t80/T80.vhd b/modules/cpu-t80/T80.vhd new file mode 100644 index 0000000..398fa0d --- /dev/null +++ b/modules/cpu-t80/T80.vhd @@ -0,0 +1,1073 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0210 : Fixed wait and halt +-- +-- 0211 : Fixed Refresh addition and IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson +-- +-- 0235 : Added clock enable and IM 2 fix by Mike Johnson +-- +-- 0237 : Changed 8080 I/O address output, added IntE output +-- +-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag +-- +-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode +-- +-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM +-- +-- 0247 : Fixed bus req/ack cycle +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80 is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); +end T80; + +architecture rtl of T80 is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; + + -- Registers + signal ACC, F : std_logic_vector(7 downto 0); + signal Ap, Fp : std_logic_vector(7 downto 0); + signal I : std_logic_vector(7 downto 0); + signal R : unsigned(7 downto 0); + signal SP, PC : unsigned(15 downto 0); + signal RegDIH : std_logic_vector(7 downto 0); + signal RegDIL : std_logic_vector(7 downto 0); + signal RegBusA : std_logic_vector(15 downto 0); + signal RegBusB : std_logic_vector(15 downto 0); + signal RegBusC : std_logic_vector(15 downto 0); + signal RegAddrA_r : std_logic_vector(2 downto 0); + signal RegAddrA : std_logic_vector(2 downto 0); + signal RegAddrB_r : std_logic_vector(2 downto 0); + signal RegAddrB : std_logic_vector(2 downto 0); + signal RegAddrC : std_logic_vector(2 downto 0); + signal RegWEH : std_logic; + signal RegWEL : std_logic; + signal Alternate : std_logic; + + -- Help Registers + signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register + signal IR : std_logic_vector(7 downto 0); -- Instruction register + signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector + signal RegBusA_r : std_logic_vector(15 downto 0); + + signal ID16 : signed(15 downto 0); + signal Save_Mux : std_logic_vector(7 downto 0); + + signal TState : unsigned(2 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal IntE_FF1 : std_logic; + signal IntE_FF2 : std_logic; + signal Halt_FF : std_logic; + signal BusReq_s : std_logic; + signal BusAck : std_logic; + signal ClkEn : std_logic; + signal NMI_s : std_logic; + signal INT_s : std_logic; + signal IStatus : std_logic_vector(1 downto 0); + + signal DI_Reg : std_logic_vector(7 downto 0); + signal T_Res : std_logic; + signal XY_State : std_logic_vector(1 downto 0); + signal Pre_XY_F_M : std_logic_vector(2 downto 0); + signal NextIs_XY_Fetch : std_logic; + signal XY_Ind : std_logic; + signal No_BTR : std_logic; + signal BTR_r : std_logic; + signal Auto_Wait : std_logic; + signal Auto_Wait_t1 : std_logic; + signal Auto_Wait_t2 : std_logic; + signal IncDecZ : std_logic; + + -- ALU signals + signal BusB : std_logic_vector(7 downto 0); + signal BusA : std_logic_vector(7 downto 0); + signal ALU_Q : std_logic_vector(7 downto 0); + signal F_Out : std_logic_vector(7 downto 0); + + -- Registered micro code outputs + signal Read_To_Reg_r : std_logic_vector(4 downto 0); + signal Arith16_r : std_logic; + signal Z16_r : std_logic; + signal ALU_Op_r : std_logic_vector(3 downto 0); + signal Save_ALU_r : std_logic; + signal PreserveC_r : std_logic; + signal MCycles : std_logic_vector(2 downto 0); + + -- Micro code outputs + signal MCycles_d : std_logic_vector(2 downto 0); + signal TStates : std_logic_vector(2 downto 0); + signal IntCycle : std_logic; + signal NMICycle : std_logic; + signal Inc_PC : std_logic; + signal Inc_WZ : std_logic; + signal IncDec_16 : std_logic_vector(3 downto 0); + signal Prefix : std_logic_vector(1 downto 0); + signal Read_To_Acc : std_logic; + signal Read_To_Reg : std_logic; + signal Set_BusB_To : std_logic_vector(3 downto 0); + signal Set_BusA_To : std_logic_vector(3 downto 0); + signal ALU_Op : std_logic_vector(3 downto 0); + signal Save_ALU : std_logic; + signal PreserveC : std_logic; + signal Arith16 : std_logic; + signal Set_Addr_To : std_logic_vector(2 downto 0); + signal Jump : std_logic; + signal JumpE : std_logic; + signal JumpXY : std_logic; + signal Call : std_logic; + signal RstP : std_logic; + signal LDZ : std_logic; + signal LDW : std_logic; + signal LDSPHL : std_logic; + signal IORQ_i : std_logic; + signal Special_LD : std_logic_vector(2 downto 0); + signal ExchangeDH : std_logic; + signal ExchangeRp : std_logic; + signal ExchangeAF : std_logic; + signal ExchangeRS : std_logic; + signal I_DJNZ : std_logic; + signal I_CPL : std_logic; + signal I_CCF : std_logic; + signal I_SCF : std_logic; + signal I_RETN : std_logic; + signal I_BT : std_logic; + signal I_BC : std_logic; + signal I_BTR : std_logic; + signal I_RLD : std_logic; + signal I_RRD : std_logic; + signal I_INRC : std_logic; + signal SetDI : std_logic; + signal SetEI : std_logic; + signal IMode : std_logic_vector(1 downto 0); + signal Halt : std_logic; + +begin + + mcode : T80_MCode + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + IR => IR, + ISet => ISet, + MCycle => MCycle, + F => F, + NMICycle => NMICycle, + IntCycle => IntCycle, + MCycles => MCycles_d, + TStates => TStates, + Prefix => Prefix, + Inc_PC => Inc_PC, + Inc_WZ => Inc_WZ, + IncDec_16 => IncDec_16, + Read_To_Acc => Read_To_Acc, + Read_To_Reg => Read_To_Reg, + Set_BusB_To => Set_BusB_To, + Set_BusA_To => Set_BusA_To, + ALU_Op => ALU_Op, + Save_ALU => Save_ALU, + PreserveC => PreserveC, + Arith16 => Arith16, + Set_Addr_To => Set_Addr_To, + IORQ => IORQ_i, + Jump => Jump, + JumpE => JumpE, + JumpXY => JumpXY, + Call => Call, + RstP => RstP, + LDZ => LDZ, + LDW => LDW, + LDSPHL => LDSPHL, + Special_LD => Special_LD, + ExchangeDH => ExchangeDH, + ExchangeRp => ExchangeRp, + ExchangeAF => ExchangeAF, + ExchangeRS => ExchangeRS, + I_DJNZ => I_DJNZ, + I_CPL => I_CPL, + I_CCF => I_CCF, + I_SCF => I_SCF, + I_RETN => I_RETN, + I_BT => I_BT, + I_BC => I_BC, + I_BTR => I_BTR, + I_RLD => I_RLD, + I_RRD => I_RRD, + I_INRC => I_INRC, + SetDI => SetDI, + SetEI => SetEI, + IMode => IMode, + Halt => Halt, + NoRead => NoRead, + Write => Write); + + alu : T80_ALU + generic map( + Mode => Mode, + Flag_C => Flag_C, + Flag_N => Flag_N, + Flag_P => Flag_P, + Flag_X => Flag_X, + Flag_H => Flag_H, + Flag_Y => Flag_Y, + Flag_Z => Flag_Z, + Flag_S => Flag_S) + port map( + Arith16 => Arith16_r, + Z16 => Z16_r, + ALU_Op => ALU_Op_r, + IR => IR(5 downto 0), + ISet => ISet, + BusA => BusA, + BusB => BusB, + F_In => F, + Q => ALU_Q, + F_Out => F_Out); + + ClkEn <= CEN and not BusAck; + + T_Res <= '1' when TState = unsigned(TStates) else '0'; + + NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and + ((Set_Addr_To = aXY) or + (MCycle = "001" and IR = "11001011") or + (MCycle = "001" and IR = "00110110")) else '0'; + + Save_Mux <= BusB when ExchangeRp = '1' else + DI_Reg when Save_ALU_r = '0' else + ALU_Q; + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + PC <= (others => '0'); -- Program Counter + A <= (others => '0'); + TmpAddr <= (others => '0'); + IR <= "00000000"; + ISet <= "00"; + XY_State <= "00"; + IStatus <= "00"; + MCycles <= "000"; + DO <= "00000000"; + + ACC <= (others => '1'); + F <= (others => '1'); + Ap <= (others => '1'); + Fp <= (others => '1'); + I <= (others => '0'); + R <= (others => '0'); + SP <= (others => '1'); + Alternate <= '0'; + + Read_To_Reg_r <= "00000"; + F <= (others => '1'); + Arith16_r <= '0'; + BTR_r <= '0'; + Z16_r <= '0'; + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + PreserveC_r <= '0'; + XY_Ind <= '0'; + + elsif CLK_n'event and CLK_n = '1' then + + if ClkEn = '1' then + + ALU_Op_r <= "0000"; + Save_ALU_r <= '0'; + Read_To_Reg_r <= "00000"; + + MCycles <= MCycles_d; + + if IMode /= "11" then + IStatus <= IMode; + end if; + + Arith16_r <= Arith16; + PreserveC_r <= PreserveC; + if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then + Z16_r <= '1'; + else + Z16_r <= '0'; + end if; + + if MCycle = "001" and TState(2) = '0' then + -- MCycle = 1 and TState = 1, 2, or 3 + + if TState = 2 and Wait_n = '1' then + if Mode < 2 then + A(7 downto 0) <= std_logic_vector(R); + A(15 downto 8) <= I; + R(6 downto 0) <= R(6 downto 0) + 1; + end if; + + if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then + PC <= PC + 1; + end if; + + if IntCycle = '1' and IStatus = "01" then + IR <= "11111111"; + elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then + IR <= "00000000"; + else + IR <= DInst; + end if; + + ISet <= "00"; + if Prefix /= "00" then + if Prefix = "11" then + if IR(5) = '1' then + XY_State <= "10"; + else + XY_State <= "01"; + end if; + else + if Prefix = "10" then + XY_State <= "00"; + XY_Ind <= '0'; + end if; + ISet <= Prefix; + end if; + else + XY_State <= "00"; + XY_Ind <= '0'; + end if; + end if; + + else + -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3) + + if MCycle = "110" then + XY_Ind <= '1'; + if Prefix = "01" then + ISet <= "01"; + end if; + end if; + + if T_Res = '1' then + BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR; + if Jump = '1' then + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(DI_Reg); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + elsif JumpXY = '1' then + A <= RegBusC; + PC <= unsigned(RegBusC); + elsif Call = '1' or RstP = '1' then + A <= TmpAddr; + PC <= unsigned(TmpAddr); + elsif MCycle = MCycles and NMICycle = '1' then + A <= "0000000001100110"; + PC <= "0000000001100110"; + elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then + A(15 downto 8) <= I; + A(7 downto 0) <= TmpAddr(7 downto 0); + PC(15 downto 8) <= unsigned(I); + PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0)); + else + case Set_Addr_To is + when aXY => + if XY_State = "00" then + A <= RegBusC; + else + if NextIs_XY_Fetch = '1' then + A <= std_logic_vector(PC); + else + A <= TmpAddr; + end if; + end if; + when aIOA => + if Mode = 3 then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + elsif Mode = 2 then + -- Duplicate I/O address on 8080 + A(15 downto 8) <= DI_Reg; + else + A(15 downto 8) <= ACC; + end if; + A(7 downto 0) <= DI_Reg; + when aSP => + A <= std_logic_vector(SP); + when aBC => + if Mode = 3 and IORQ_i = '1' then + -- Memory map I/O on GBZ80 + A(15 downto 8) <= (others => '1'); + A(7 downto 0) <= RegBusC(7 downto 0); + else + A <= RegBusC; + end if; + when aDE => + A <= RegBusC; + when aZI => + if Inc_WZ = '1' then + A <= std_logic_vector(unsigned(TmpAddr) + 1); + else + A(15 downto 8) <= DI_Reg; + A(7 downto 0) <= TmpAddr(7 downto 0); + end if; + when others => + A <= std_logic_vector(PC); + end case; + end if; + + Save_ALU_r <= Save_ALU; + ALU_Op_r <= ALU_Op; + + if I_CPL = '1' then + -- CPL + ACC <= not ACC; + F(Flag_Y) <= not ACC(5); + F(Flag_H) <= '1'; + F(Flag_X) <= not ACC(3); + F(Flag_N) <= '1'; + end if; + if I_CCF = '1' then + -- CCF + F(Flag_C) <= not F(Flag_C); + F(Flag_Y) <= ACC(5); + F(Flag_H) <= F(Flag_C); + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + if I_SCF = '1' then + -- SCF + F(Flag_C) <= '1'; + F(Flag_Y) <= ACC(5); + F(Flag_H) <= '0'; + F(Flag_X) <= ACC(3); + F(Flag_N) <= '0'; + end if; + end if; + + if TState = 2 and Wait_n = '1' then + if ISet = "01" and MCycle = "111" then + IR <= DInst; + end if; + if JumpE = '1' then + PC <= unsigned(signed(PC) + signed(DI_Reg)); + elsif Inc_PC = '1' then + PC <= PC + 1; + end if; + if BTR_r = '1' then + PC <= PC - 2; + end if; + if RstP = '1' then + TmpAddr <= (others =>'0'); + TmpAddr(5 downto 3) <= IR(5 downto 3); + end if; + end if; + if TState = 3 and MCycle = "110" then + TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg)); + end if; + + if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then + if IncDec_16(2 downto 0) = "111" then + if IncDec_16(3) = '1' then + SP <= SP - 1; + else + SP <= SP + 1; + end if; + end if; + end if; + + if LDSPHL = '1' then + SP <= unsigned(RegBusC); + end if; + if ExchangeAF = '1' then + Ap <= ACC; + ACC <= Ap; + Fp <= F; + F <= Fp; + end if; + if ExchangeRS = '1' then + Alternate <= not Alternate; + end if; + end if; + + if TState = 3 then + if LDZ = '1' then + TmpAddr(7 downto 0) <= DI_Reg; + end if; + if LDW = '1' then + TmpAddr(15 downto 8) <= DI_Reg; + end if; + + if Special_LD(2) = '1' then + case Special_LD(1 downto 0) is + when "00" => + ACC <= I; + F(Flag_P) <= IntE_FF2; + when "01" => + ACC <= std_logic_vector(R); + F(Flag_P) <= IntE_FF2; + when "10" => + I <= ACC; + when others => + R <= unsigned(ACC); + end case; + end if; + end if; + + if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then + if Mode = 3 then + F(6) <= F_Out(6); + F(5) <= F_Out(5); + F(7) <= F_Out(7); + if PreserveC_r = '0' then + F(4) <= F_Out(4); + end if; + else + F(7 downto 1) <= F_Out(7 downto 1); + if PreserveC_r = '0' then + F(Flag_C) <= F_Out(0); + end if; + end if; + end if; + if T_Res = '1' and I_INRC = '1' then + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + if DI_Reg(7 downto 0) = "00000000" then + F(Flag_Z) <= '1'; + else + F(Flag_Z) <= '0'; + end if; + F(Flag_S) <= DI_Reg(7); + F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor + DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7)); + end if; + + if TState = 1 and Auto_Wait_t1 = '0' then + DO <= BusB; + if I_RLD = '1' then + DO(3 downto 0) <= BusA(3 downto 0); + DO(7 downto 4) <= BusB(3 downto 0); + end if; + if I_RRD = '1' then + DO(3 downto 0) <= BusB(7 downto 4); + DO(7 downto 4) <= BusA(3 downto 0); + end if; + end if; + + if T_Res = '1' then + Read_To_Reg_r(3 downto 0) <= Set_BusA_To; + Read_To_Reg_r(4) <= Read_To_Reg; + if Read_To_Acc = '1' then + Read_To_Reg_r(3 downto 0) <= "0111"; + Read_To_Reg_r(4) <= '1'; + end if; + end if; + + if TState = 1 and I_BT = '1' then + F(Flag_X) <= ALU_Q(3); + F(Flag_Y) <= ALU_Q(1); + F(Flag_H) <= '0'; + F(Flag_N) <= '0'; + end if; + if I_BC = '1' or I_BT = '1' then + F(Flag_P) <= IncDecZ; + end if; + + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10111" => + ACC <= Save_Mux; + when "10110" => + DO <= Save_Mux; + when "11000" => + SP(7 downto 0) <= unsigned(Save_Mux); + when "11001" => + SP(15 downto 8) <= unsigned(Save_Mux); + when "11011" => + F <= Save_Mux; + when others => + end case; + end if; + + end if; + + end if; + + end process; + +--------------------------------------------------------------------------- +-- +-- BC('), DE('), HL('), IX and IY +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + -- Bus A / Write + RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then + RegAddrA_r <= XY_State(1) & "11"; + end if; + + -- Bus B + RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1); + if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then + RegAddrB_r <= XY_State(1) & "11"; + end if; + + -- Address from register + RegAddrC <= Alternate & Set_Addr_To(1 downto 0); + -- Jump (HL), LD SP,HL + if (JumpXY = '1' or LDSPHL = '1') then + RegAddrC <= Alternate & "10"; + end if; + if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then + RegAddrC <= XY_State(1) & "11"; + end if; + + if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then + IncDecZ <= F_Out(Flag_Z); + end if; + if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then + if ID16 = 0 then + IncDecZ <= '0'; + else + IncDecZ <= '1'; + end if; + end if; + + RegBusA_r <= RegBusA; + end if; + end if; + end process; + + RegAddrA <= + -- 16 bit increment/decrement + Alternate & IncDec_16(1 downto 0) when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else + XY_State(1) & "11" when (TState = 2 or + (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else + -- EX HL,DL + Alternate & "10" when ExchangeDH = '1' and TState = 3 else + Alternate & "01" when ExchangeDH = '1' and TState = 4 else + -- Bus A / Write + RegAddrA_r; + + RegAddrB <= + -- EX HL,DL + Alternate & "01" when ExchangeDH = '1' and TState = 3 else + -- Bus B + RegAddrB_r; + + ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else + signed(RegBusA) + 1; + + process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegWEH <= '0'; + RegWEL <= '0'; + if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or + (Save_ALU_r = '1' and ALU_OP_r /= "0111") then + case Read_To_Reg_r is + when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" => + RegWEH <= not Read_To_Reg_r(0); + RegWEL <= Read_To_Reg_r(0); + when others => + end case; + end if; + + if ExchangeDH = '1' and (TState = 3 or TState = 4) then + RegWEH <= '1'; + RegWEL <= '1'; + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + case IncDec_16(1 downto 0) is + when "00" | "01" | "10" => + RegWEH <= '1'; + RegWEL <= '1'; + when others => + end case; + end if; + end process; + + process (Save_Mux, RegBusB, RegBusA_r, ID16, + ExchangeDH, IncDec_16, MCycle, TState, Wait_n) + begin + RegDIH <= Save_Mux; + RegDIL <= Save_Mux; + + if ExchangeDH = '1' and TState = 3 then + RegDIH <= RegBusB(15 downto 8); + RegDIL <= RegBusB(7 downto 0); + end if; + if ExchangeDH = '1' and TState = 4 then + RegDIH <= RegBusA_r(15 downto 8); + RegDIL <= RegBusA_r(7 downto 0); + end if; + + if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then + RegDIH <= std_logic_vector(ID16(15 downto 8)); + RegDIL <= std_logic_vector(ID16(7 downto 0)); + end if; + end process; + + Regs : T80_Reg + port map( + Clk => CLK_n, + CEN => ClkEn, + WEH => RegWEH, + WEL => RegWEL, + AddrA => RegAddrA, + AddrB => RegAddrB, + AddrC => RegAddrC, + DIH => RegDIH, + DIL => RegDIL, + DOAH => RegBusA(15 downto 8), + DOAL => RegBusA(7 downto 0), + DOBH => RegBusB(15 downto 8), + DOBL => RegBusB(7 downto 0), + DOCH => RegBusC(15 downto 8), + DOCL => RegBusC(7 downto 0)); + +--------------------------------------------------------------------------- +-- +-- Buses +-- +--------------------------------------------------------------------------- + process (CLK_n) + begin + if CLK_n'event and CLK_n = '1' then + if ClkEn = '1' then + case Set_BusB_To is + when "0111" => + BusB <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusB_To(0) = '1' then + BusB <= RegBusB(7 downto 0); + else + BusB <= RegBusB(15 downto 8); + end if; + when "0110" => + BusB <= DI_Reg; + when "1000" => + BusB <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusB <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusB <= "00000001"; + when "1011" => + BusB <= F; + when "1100" => + BusB <= std_logic_vector(PC(7 downto 0)); + when "1101" => + BusB <= std_logic_vector(PC(15 downto 8)); + when "1110" => + BusB <= "00000000"; + when others => + BusB <= "--------"; + end case; + + case Set_BusA_To is + when "0111" => + BusA <= ACC; + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" => + if Set_BusA_To(0) = '1' then + BusA <= RegBusA(7 downto 0); + else + BusA <= RegBusA(15 downto 8); + end if; + when "0110" => + BusA <= DI_Reg; + when "1000" => + BusA <= std_logic_vector(SP(7 downto 0)); + when "1001" => + BusA <= std_logic_vector(SP(15 downto 8)); + when "1010" => + BusA <= "00000000"; + when others => + BusB <= "--------"; + end case; + end if; + end if; + end process; + +--------------------------------------------------------------------------- +-- +-- Generate external control signals +-- +--------------------------------------------------------------------------- + process (RESET_n,CLK_n) + begin + if RESET_n = '0' then + RFSH_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then + RFSH_n <= '0'; + else + RFSH_n <= '1'; + end if; + end if; + end if; + end process; + + MC <= std_logic_vector(MCycle); + TS <= std_logic_vector(TState); + DI_Reg <= DI; + HALT_n <= not Halt_FF; + BUSAK_n <= not BusAck; + IntCycle_n <= not IntCycle; + IntE <= IntE_FF1; + IORQ <= IORQ_i; + Stop <= I_DJNZ; + +------------------------------------------------------------------------- +-- +-- Syncronise inputs +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + variable OldNMI_n : std_logic; + begin + if RESET_n = '0' then + BusReq_s <= '0'; + INT_s <= '0'; + NMI_s <= '0'; + OldNMI_n := '0'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + BusReq_s <= not BUSRQ_n; + INT_s <= not INT_n; + if NMICycle = '1' then + NMI_s <= '0'; + elsif NMI_n = '0' and OldNMI_n = '1' then + NMI_s <= '1'; + end if; + OldNMI_n := NMI_n; + end if; + end if; + end process; + +------------------------------------------------------------------------- +-- +-- Main state machine +-- +------------------------------------------------------------------------- + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + MCycle <= "001"; + TState <= "000"; + Pre_XY_F_M <= "000"; + Halt_FF <= '0'; + BusAck <= '0'; + NMICycle <= '0'; + IntCycle <= '0'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + No_BTR <= '0'; + Auto_Wait_t1 <= '0'; + Auto_Wait_t2 <= '0'; + M1_n <= '1'; + elsif CLK_n'event and CLK_n = '1' then + if CEN = '1' then + if T_Res = '1' then + Auto_Wait_t1 <= '0'; + else + Auto_Wait_t1 <= Auto_Wait or IORQ_i; + end if; + Auto_Wait_t2 <= Auto_Wait_t1; + No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or + (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or + (I_BTR and (not IR(4) or F(Flag_Z))); + if TState = 2 then + if SetEI = '1' then + IntE_FF1 <= '1'; + IntE_FF2 <= '1'; + end if; + if I_RETN = '1' then + IntE_FF1 <= IntE_FF2; + end if; + end if; + if TState = 3 then + if SetDI = '1' then + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + end if; + if IntCycle = '1' or NMICycle = '1' then + Halt_FF <= '0'; + end if; + if MCycle = "001" and TState = 2 and Wait_n = '1' then + M1_n <= '1'; + end if; + if BusReq_s = '1' and BusAck = '1' then + else + BusAck <= '0'; + if TState = 2 and Wait_n = '0' then + elsif T_Res = '1' then + if Halt = '1' then + Halt_FF <= '1'; + end if; + if BusReq_s = '1' then + BusAck <= '1'; + else + TState <= "001"; + if NextIs_XY_Fetch = '1' then + MCycle <= "110"; + Pre_XY_F_M <= MCycle; + if IR = "00110110" and Mode = 0 then + Pre_XY_F_M <= "010"; + end if; + elsif (MCycle = "111") or + (MCycle = "110" and Mode = 1 and ISet /= "01") then + MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1); + elsif (MCycle = MCycles) or + No_BTR = '1' or + (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then + M1_n <= '0'; + MCycle <= "001"; + IntCycle <= '0'; + NMICycle <= '0'; + if NMI_s = '1' and Prefix = "00" then + NMICycle <= '1'; + IntE_FF1 <= '0'; + elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then + IntCycle <= '1'; + IntE_FF1 <= '0'; + IntE_FF2 <= '0'; + end if; + else + MCycle <= std_logic_vector(unsigned(MCycle) + 1); + end if; + end if; + else + if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor + (IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then + TState <= TState + 1; + end if; + end if; + end if; + if TState = 0 then + M1_n <= '0'; + end if; + end if; + end if; + end process; + + process (IntCycle, NMICycle, MCycle) + begin + Auto_Wait <= '0'; + if IntCycle = '1' or NMICycle = '1' then + if MCycle = "001" then + Auto_Wait <= '1'; + end if; + end if; + end process; + +end; diff --git a/modules/cpu-t80/T80_ALU.vhd b/modules/cpu-t80/T80_ALU.vhd new file mode 100644 index 0000000..86fddce --- /dev/null +++ b/modules/cpu-t80/T80_ALU.vhd @@ -0,0 +1,351 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0247 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0238 : Fixed zero flag for 16 bit SBC and ADC +-- +-- 0240 : Added GB operations +-- +-- 0242 : Cleanup +-- +-- 0247 : Cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_ALU is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); +end T80_ALU; + +architecture rtl of T80_ALU is + + procedure AddSub(A : std_logic_vector; + B : std_logic_vector; + Sub : std_logic; + Carry_In : std_logic; + signal Res : out std_logic_vector; + signal Carry : out std_logic) is + variable B_i : unsigned(A'length - 1 downto 0); + variable Res_i : unsigned(A'length + 1 downto 0); + begin + if Sub = '1' then + B_i := not unsigned(B); + else + B_i := unsigned(B); + end if; + Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1"); + Carry <= Res_i(A'length + 1); + Res <= std_logic_vector(Res_i(A'length downto 1)); + end; + + -- AddSub variables (temporary signals) + signal UseCarry : std_logic; + signal Carry7_v : std_logic; + signal Overflow_v : std_logic; + signal HalfCarry_v : std_logic; + signal Carry_v : std_logic; + signal Q_v : std_logic_vector(7 downto 0); + + signal BitMask : std_logic_vector(7 downto 0); + +begin + + with IR(5 downto 3) select BitMask <= "00000001" when "000", + "00000010" when "001", + "00000100" when "010", + "00001000" when "011", + "00010000" when "100", + "00100000" when "101", + "01000000" when "110", + "10000000" when others; + + UseCarry <= not ALU_Op(2) and ALU_Op(0); + AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v); + AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v); + AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v); + OverFlow_v <= Carry_v xor Carry7_v; + + process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16) + variable Q_t : std_logic_vector(7 downto 0); + variable DAA_Q : unsigned(8 downto 0); + begin + Q_t := "--------"; + F_Out <= F_In; + DAA_Q := "---------"; + case ALU_Op is + when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" => + F_Out(Flag_N) <= '0'; + F_Out(Flag_C) <= '0'; + case ALU_OP(2 downto 0) is + when "000" | "001" => -- ADD, ADC + Q_t := Q_v; + F_Out(Flag_C) <= Carry_v; + F_Out(Flag_H) <= HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "010" | "011" | "111" => -- SUB, SBC, CP + Q_t := Q_v; + F_Out(Flag_N) <= '1'; + F_Out(Flag_C) <= not Carry_v; + F_Out(Flag_H) <= not HalfCarry_v; + F_Out(Flag_P) <= OverFlow_v; + when "100" => -- AND + Q_t(7 downto 0) := BusA and BusB; + F_Out(Flag_H) <= '1'; + when "101" => -- XOR + Q_t(7 downto 0) := BusA xor BusB; + F_Out(Flag_H) <= '0'; + when others => -- OR "110" + Q_t(7 downto 0) := BusA or BusB; + F_Out(Flag_H) <= '0'; + end case; + if ALU_Op(2 downto 0) = "111" then -- CP + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + else + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + end if; + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + if Z16 = '1' then + F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC + end if; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + case ALU_Op(2 downto 0) is + when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP + when others => + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + end case; + if Arith16 = '1' then + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + F_Out(Flag_P) <= F_In(Flag_P); + end if; + when "1100" => + -- DAA + F_Out(Flag_H) <= F_In(Flag_H); + F_Out(Flag_C) <= F_In(Flag_C); + DAA_Q(7 downto 0) := unsigned(BusA); + DAA_Q(8) := '0'; + if F_In(Flag_N) = '0' then + -- After addition + -- Alow > 9 or H = 1 + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if (DAA_Q(3 downto 0) > 9) then + F_Out(Flag_H) <= '1'; + else + F_Out(Flag_H) <= '0'; + end if; + DAA_Q := DAA_Q + 6; + end if; + -- new Ahigh > 9 or C = 1 + if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q + 96; -- 0x60 + end if; + else + -- After subtraction + if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then + if DAA_Q(3 downto 0) > 5 then + F_Out(Flag_H) <= '0'; + end if; + DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6; + end if; + if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then + DAA_Q := DAA_Q - 352; -- 0x160 + end if; + end if; + F_Out(Flag_X) <= DAA_Q(3); + F_Out(Flag_Y) <= DAA_Q(5); + F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8); + Q_t := std_logic_vector(DAA_Q(7 downto 0)); + if DAA_Q(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= DAA_Q(7); + F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor + DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7)); + when "1101" | "1110" => + -- RLD, RRD + Q_t(7 downto 4) := BusA(7 downto 4); + if ALU_Op(0) = '1' then + Q_t(3 downto 0) := BusB(7 downto 4); + else + Q_t(3 downto 0) := BusB(3 downto 0); + end if; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_S) <= Q_t(7); + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + when "1001" => + -- BIT + Q_t(7 downto 0) := BusB and BitMask; + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + F_Out(Flag_P) <= '1'; + else + F_Out(Flag_Z) <= '0'; + F_Out(Flag_P) <= '0'; + end if; + F_Out(Flag_H) <= '1'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= '0'; + F_Out(Flag_Y) <= '0'; + if IR(2 downto 0) /= "110" then + F_Out(Flag_X) <= BusB(3); + F_Out(Flag_Y) <= BusB(5); + end if; + when "1010" => + -- SET + Q_t(7 downto 0) := BusB or BitMask; + when "1011" => + -- RES + Q_t(7 downto 0) := BusB and not BitMask; + when "1000" => + -- ROT + case IR(5 downto 3) is + when "000" => -- RLC + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := BusA(7); + F_Out(Flag_C) <= BusA(7); + when "010" => -- RL + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(7); + when "001" => -- RRC + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(0); + F_Out(Flag_C) <= BusA(0); + when "011" => -- RR + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := F_In(Flag_C); + F_Out(Flag_C) <= BusA(0); + when "100" => -- SLA + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '0'; + F_Out(Flag_C) <= BusA(7); + when "110" => -- SLL (Undocumented) / SWAP + if Mode = 3 then + Q_t(7 downto 4) := BusA(3 downto 0); + Q_t(3 downto 0) := BusA(7 downto 4); + F_Out(Flag_C) <= '0'; + else + Q_t(7 downto 1) := BusA(6 downto 0); + Q_t(0) := '1'; + F_Out(Flag_C) <= BusA(7); + end if; + when "101" => -- SRA + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := BusA(7); + F_Out(Flag_C) <= BusA(0); + when others => -- SRL + Q_t(6 downto 0) := BusA(7 downto 1); + Q_t(7) := '0'; + F_Out(Flag_C) <= BusA(0); + end case; + F_Out(Flag_H) <= '0'; + F_Out(Flag_N) <= '0'; + F_Out(Flag_X) <= Q_t(3); + F_Out(Flag_Y) <= Q_t(5); + F_Out(Flag_S) <= Q_t(7); + if Q_t(7 downto 0) = "00000000" then + F_Out(Flag_Z) <= '1'; + else + F_Out(Flag_Z) <= '0'; + end if; + F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor + Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7)); + if ISet = "00" then + F_Out(Flag_P) <= F_In(Flag_P); + F_Out(Flag_S) <= F_In(Flag_S); + F_Out(Flag_Z) <= F_In(Flag_Z); + end if; + when others => + null; + end case; + Q <= Q_t; + end process; + +end; diff --git a/modules/cpu-t80/T80_MCode.vhd b/modules/cpu-t80/T80_MCode.vhd new file mode 100644 index 0000000..4cc30f3 --- /dev/null +++ b/modules/cpu-t80/T80_MCode.vhd @@ -0,0 +1,1934 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0208 : First complete release +-- +-- 0211 : Fixed IM 1 +-- +-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test +-- +-- 0235 : Added IM 2 fix by Mike Johnson +-- +-- 0238 : Added NoRead signal +-- +-- 0238b: Fixed instruction timing for POP and DJNZ +-- +-- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes +-- +-- 0242 : Fixed I/O instruction timing, cleanup +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_MCode is + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); +end T80_MCode; + +architecture rtl of T80_MCode is + + constant aNone : std_logic_vector(2 downto 0) := "111"; + constant aBC : std_logic_vector(2 downto 0) := "000"; + constant aDE : std_logic_vector(2 downto 0) := "001"; + constant aXY : std_logic_vector(2 downto 0) := "010"; + constant aIOA : std_logic_vector(2 downto 0) := "100"; + constant aSP : std_logic_vector(2 downto 0) := "101"; + constant aZI : std_logic_vector(2 downto 0) := "110"; +-- constant aNone : std_logic_vector(2 downto 0) := "000"; +-- constant aXY : std_logic_vector(2 downto 0) := "001"; +-- constant aIOA : std_logic_vector(2 downto 0) := "010"; +-- constant aSP : std_logic_vector(2 downto 0) := "011"; +-- constant aBC : std_logic_vector(2 downto 0) := "100"; +-- constant aDE : std_logic_vector(2 downto 0) := "101"; +-- constant aZI : std_logic_vector(2 downto 0) := "110"; + + function is_cc_true( + F : std_logic_vector(7 downto 0); + cc : bit_vector(2 downto 0) + ) return boolean is + begin + if Mode = 3 then + case cc is + when "000" => return F(7) = '0'; -- NZ + when "001" => return F(7) = '1'; -- Z + when "010" => return F(4) = '0'; -- NC + when "011" => return F(4) = '1'; -- C + when "100" => return false; + when "101" => return false; + when "110" => return false; + when "111" => return false; + end case; + else + case cc is + when "000" => return F(6) = '0'; -- NZ + when "001" => return F(6) = '1'; -- Z + when "010" => return F(0) = '0'; -- NC + when "011" => return F(0) = '1'; -- C + when "100" => return F(2) = '0'; -- PO + when "101" => return F(2) = '1'; -- PE + when "110" => return F(7) = '0'; -- P + when "111" => return F(7) = '1'; -- M + end case; + end if; + end; + +begin + + process (IR, ISet, MCycle, F, NMICycle, IntCycle) + variable DDD : std_logic_vector(2 downto 0); + variable SSS : std_logic_vector(2 downto 0); + variable DPair : std_logic_vector(1 downto 0); + variable IRB : bit_vector(7 downto 0); + begin + DDD := IR(5 downto 3); + SSS := IR(2 downto 0); + DPair := IR(5 downto 4); + IRB := to_bitvector(IR); + + MCycles <= "001"; + if MCycle = "001" then + TStates <= "100"; + else + TStates <= "011"; + end if; + Prefix <= "00"; + Inc_PC <= '0'; + Inc_WZ <= '0'; + IncDec_16 <= "0000"; + Read_To_Acc <= '0'; + Read_To_Reg <= '0'; + Set_BusB_To <= "0000"; + Set_BusA_To <= "0000"; + ALU_Op <= "0" & IR(5 downto 3); + Save_ALU <= '0'; + PreserveC <= '0'; + Arith16 <= '0'; + IORQ <= '0'; + Set_Addr_To <= aNone; + Jump <= '0'; + JumpE <= '0'; + JumpXY <= '0'; + Call <= '0'; + RstP <= '0'; + LDZ <= '0'; + LDW <= '0'; + LDSPHL <= '0'; + Special_LD <= "000"; + ExchangeDH <= '0'; + ExchangeRp <= '0'; + ExchangeAF <= '0'; + ExchangeRS <= '0'; + I_DJNZ <= '0'; + I_CPL <= '0'; + I_CCF <= '0'; + I_SCF <= '0'; + I_RETN <= '0'; + I_BT <= '0'; + I_BC <= '0'; + I_BTR <= '0'; + I_RLD <= '0'; + I_RRD <= '0'; + I_INRC <= '0'; + SetDI <= '0'; + SetEI <= '0'; + IMode <= "11"; + Halt <= '0'; + NoRead <= '0'; + Write <= '0'; + + case ISet is + when "00" => + +------------------------------------------------------------------------------ +-- +-- Unprefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is +-- 8 BIT LOAD GROUP + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- LD r,r' + Set_BusB_To(2 downto 0) <= SSS; + ExchangeRp <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" => + -- LD r,n + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" => + -- LD r,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + when others => null; + end case; + when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" => + -- LD (HL),r + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110110" => + -- LD (HL),n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aXY; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00001010" => + -- LD A,(BC) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00011010" => + -- LD A,(DE) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + when 2 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "00111010" => + if Mode = 3 then + -- LDD A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end if; + when "00000010" => + -- LD (BC),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00010010" => + -- LD (DE),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aDE; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + when others => null; + end case; + when "00110010" => + if Mode = 3 then + -- LDD (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "1110"; + when others => null; + end case; + else + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + end if; + +-- 16 BIT LOAD GROUP + when "00000001"|"00010001"|"00100001"|"00110001" => + -- LD dd,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1000"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + Inc_PC <= '1'; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1001"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "00101010" => + if Mode = 3 then + -- LDI A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Acc <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD HL,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end if; + when "00100010" => + if Mode = 3 then + -- LDI (HL),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IncDec_16 <= "0110"; + when others => null; + end case; + else + -- LD (nn),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "0101"; -- L + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "0100"; -- H + when 5 => + Write <= '1'; + when others => null; + end case; + end if; + when "11111001" => + -- LD SP,HL + TStates <= "110"; + LDSPHL <= '1'; + when "11000101"|"11010101"|"11100101"|"11110101" => + -- PUSH qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "0111"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 2 => + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + if DPAIR = "11" then + Set_BusB_To <= "1011"; + else + Set_BusB_To(2 downto 1) <= DPAIR; + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + Write <= '1'; + when 3 => + Write <= '1'; + when others => null; + end case; + when "11000001"|"11010001"|"11100001"|"11110001" => + -- POP qq + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "1011"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '1'; + end if; + when 3 => + IncDec_16 <= "0111"; + Read_To_Reg <= '1'; + if DPAIR = "11" then + Set_BusA_To(3 downto 0) <= "0111"; + else + Set_BusA_To(2 downto 1) <= DPAIR; + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + +-- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP + when "11101011" => + if Mode /= 3 then + -- EX DE,HL + ExchangeDH <= '1'; + end if; + when "00001000" => + if Mode = 3 then + -- LD (nn),SP + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + Set_BusB_To <= "1000"; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + Set_BusB_To <= "1001"; + when 5 => + Write <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EX AF,AF' + ExchangeAF <= '1'; + end if; + when "11011001" => + if Mode = 3 then + -- RETI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + SetEI <= '1'; + when others => null; + end case; + elsif Mode < 2 then + -- EXX + ExchangeRS <= '1'; + end if; + when "11100011" => + if Mode /= 3 then + -- EX (SP),HL + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aSP; + when 2 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0101"; + Set_BusB_To <= "0101"; + Set_Addr_To <= aSP; + when 3 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + TStates <= "100"; + Write <= '1'; + when 4 => + Read_To_Reg <= '1'; + Set_BusA_To <= "0100"; + Set_BusB_To <= "0100"; + Set_Addr_To <= aSP; + when 5 => + IncDec_16 <= "1111"; + TStates <= "101"; + Write <= '1'; + when others => null; + end case; + end if; + +-- 8 BIT ARITHMETIC AND LOGICAL GROUP + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- ADD A,r + -- ADC A,r + -- SUB A,r + -- SBC A,r + -- AND A,r + -- OR A,r + -- XOR A,r + -- CP A,r + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- ADD A,(HL) + -- ADC A,(HL) + -- SUB A,(HL) + -- SBC A,(HL) + -- AND A,(HL) + -- OR A,(HL) + -- XOR A,(HL) + -- CP A,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + when others => null; + end case; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- ADD A,n + -- ADC A,n + -- SUB A,n + -- SBC A,n + -- AND A,n + -- OR A,n + -- XOR A,n + -- CP A,n + MCycles <= "010"; + if MCycle = "010" then + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusA_To(2 downto 0) <= "111"; + end if; + when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" => + -- INC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + when "00110100" => + -- INC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0000"; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" => + -- DEC r + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + ALU_Op <= "0010"; + when "00110101" => + -- DEC (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + when 2 => + TStates <= "100"; + Set_Addr_To <= aXY; + ALU_Op <= "0010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + PreserveC <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= DDD; + when 3 => + Write <= '1'; + when others => null; + end case; + +-- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS + when "00100111" => + -- DAA + Set_BusA_To(2 downto 0) <= "111"; + Read_To_Reg <= '1'; + ALU_Op <= "1100"; + Save_ALU <= '1'; + when "00101111" => + -- CPL + I_CPL <= '1'; + when "00111111" => + -- CCF + I_CCF <= '1'; + when "00110111" => + -- SCF + I_SCF <= '1'; + when "00000000" => + if NMICycle = '1' then + -- NMI + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when others => null; + end case; + elsif IntCycle = '1' then + -- INT (IM 2) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 1 => + LDZ <= '1'; + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + TStates <= "100"; + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + TStates <= "100"; + Write <= '1'; + when 4 => + Inc_PC <= '1'; + LDZ <= '1'; + when 5 => + Jump <= '1'; + when others => null; + end case; + else + -- NOP + end if; + when "01110110" => + -- HALT + Halt <= '1'; + when "11110011" => + -- DI + SetDI <= '1'; + when "11111011" => + -- EI + SetEI <= '1'; + +-- 16 BIT ARITHMETIC GROUP + when "00001001"|"00011001"|"00101001"|"00111001" => + -- ADD HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + Arith16 <= '1'; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + Arith16 <= '1'; + when others => + end case; + when "00000011"|"00010011"|"00100011"|"00110011" => + -- INC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "01"; + IncDec_16(1 downto 0) <= DPair; + when "00001011"|"00011011"|"00101011"|"00111011" => + -- DEC ss + TStates <= "110"; + IncDec_16(3 downto 2) <= "11"; + IncDec_16(1 downto 0) <= DPair; + +-- ROTATE AND SHIFT GROUP + when "00000111" + -- RLCA + |"00010111" + -- RLA + |"00001111" + -- RRCA + |"00011111" => + -- RRA + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + +-- JUMP GROUP + when "11000011" => + -- JP nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + Jump <= '1'; + when others => null; + end case; + when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+C),A + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "0111"; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "01" => + -- LD (nn),A + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + Set_BusB_To <= "0111"; + when 4 => + Write <= '1'; + when others => null; + end case; + when "10" => + -- LD A,($FF00+C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => + end case; + when "11" => + -- LD A,(nn) + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + when 4 => + Read_To_Acc <= '1'; + when others => null; + end case; + end case; + else + -- JP cc,nn + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Jump <= '1'; + end if; + when others => null; + end case; + end if; + when "00011000" => + if Mode /= 2 then + -- JR e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00111000" => + if Mode /= 2 then + -- JR C,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00110000" => + if Mode /= 2 then + -- JR NC,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_C) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00101000" => + if Mode /= 2 then + -- JR Z,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '0' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "00100000" => + if Mode /= 2 then + -- JR NZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + if F(Flag_Z) = '1' then + MCycles <= "010"; + end if; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + when "11101001" => + -- JP (HL) + JumpXY <= '1'; + when "00010000" => + if Mode = 3 then + I_DJNZ <= '1'; + elsif Mode < 2 then + -- DJNZ,e + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + I_DJNZ <= '1'; + Set_BusB_To <= "1010"; + Set_BusA_To(2 downto 0) <= "000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + I_DJNZ <= '1'; + Inc_PC <= '1'; + when 3 => + NoRead <= '1'; + JumpE <= '1'; + TStates <= "101"; + when others => null; + end case; + end if; + +-- CALL AND RETURN GROUP + when "11001101" => + -- CALL nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + IncDec_16 <= "1111"; + Inc_PC <= '1'; + TStates <= "100"; + Set_Addr_To <= aSP; + LDW <= '1'; + Set_BusB_To <= "1101"; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" => + if IR(5) = '0' or Mode /= 3 then + -- CALL cc,nn + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Inc_PC <= '1'; + LDW <= '1'; + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + IncDec_16 <= "1111"; + Set_Addr_TO <= aSP; + TStates <= "100"; + Set_BusB_To <= "1101"; + else + MCycles <= "011"; + end if; + when 4 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 5 => + Write <= '1'; + Call <= '1'; + when others => null; + end case; + end if; + when "11001001" => + -- RET + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" => + if IR(5) = '1' and Mode = 3 then + case IRB(4 downto 3) is + when "00" => + -- LD ($FF00+nn),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + when others => null; + end case; + when "01" => + -- ADD SP,n + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + ALU_Op <= "0000"; + Inc_PC <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To <= "1000"; + Set_BusB_To <= "0110"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To <= "1001"; + Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!! + when others => + end case; + when "10" => + -- LD A,($FF00+nn) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + when others => null; + end case; + when "11" => + -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!! + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Set_BusA_To(2 downto 0) <= "101"; -- L + Read_To_Reg <= '1'; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Set_BusA_To(2 downto 0) <= "100"; -- H + Read_To_Reg <= '1'; + when others => null; + end case; + end case; + else + -- RET cc + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + if is_cc_true(F, to_bitvector(IR(5 downto 3))) then + Set_Addr_TO <= aSP; + else + MCycles <= "001"; + end if; + TStates <= "101"; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + when others => null; + end case; + end if; + when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" => + -- RST p + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1101"; + when 2 => + Write <= '1'; + IncDec_16 <= "1111"; + Set_Addr_To <= aSP; + Set_BusB_To <= "1100"; + when 3 => + Write <= '1'; + RstP <= '1'; + when others => null; + end case; + +-- INPUT AND OUTPUT GROUP + when "11011011" => + if Mode /= 3 then + -- IN A,(n) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + when 3 => + Read_To_Acc <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + when "11010011" => + if Mode /= 3 then + -- OUT (n),A + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + Set_Addr_To <= aIOA; + Set_BusB_To <= "0111"; + when 3 => + Write <= '1'; + IORQ <= '1'; + when others => null; + end case; + end if; + +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ +-- MULTIBYTE INSTRUCTIONS +------------------------------------------------------------------------------ +------------------------------------------------------------------------------ + + when "11001011" => + if Mode /= 2 then + Prefix <= "01"; + end if; + + when "11101101" => + if Mode < 2 then + Prefix <= "10"; + end if; + + when "11011101"|"11111101" => + if Mode < 2 then + Prefix <= "11"; + end if; + + end case; + + when "01" => + +------------------------------------------------------------------------------ +-- +-- CB prefixed instructions +-- +------------------------------------------------------------------------------ + + Set_BusA_To(2 downto 0) <= IR(2 downto 0); + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" => + -- RLC r + -- RL r + -- RRC r + -- RR r + -- SLA r + -- SRA r + -- SRL r + -- SLL r (Undocumented) / SWAP r + if MCycle = "001" then + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" => + -- RLC (HL) + -- RL (HL) + -- RRC (HL) + -- RR (HL) + -- SRA (HL) + -- SRL (HL) + -- SLA (HL) + -- SLL (HL) (Undocumented) / SWAP (HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111" + |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111" + |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111" + |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111" + |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111" + |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111" + |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" + |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" => + -- BIT b,r + if MCycle = "001" then + Set_BusB_To(2 downto 0) <= IR(2 downto 0); + ALU_Op <= "1001"; + end if; + when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" => + -- BIT b,(HL) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1001"; + TStates <= "100"; + when others => + end case; + when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" => + -- SET b,r + if MCycle = "001" then + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" => + -- SET b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1010"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111" + |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111" + |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111" + |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111" + |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" => + -- RES b,r + if MCycle = "001" then + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + end if; + when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" => + -- RES b,(HL) + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 | 7 => + Set_Addr_To <= aXY; + when 2 => + ALU_Op <= "1011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_Addr_To <= aXY; + TStates <= "100"; + when 3 => + Write <= '1'; + when others => + end case; + end case; + + when others => + +------------------------------------------------------------------------------ +-- +-- ED prefixed instructions +-- +------------------------------------------------------------------------------ + + case IRB is + when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111" + |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111" + |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111" + |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111" + |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111" + |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111" + |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111" + |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111" + + + |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111" + |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111" + |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111" + |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111" + | "10100100"|"10100101"|"10100110"|"10100111" + | "10101100"|"10101101"|"10101110"|"10101111" + | "10110100"|"10110101"|"10110110"|"10110111" + | "10111100"|"10111101"|"10111110"|"10111111" + |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111" + |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111" + |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111" + |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111" + |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111" + |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111" + |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111" + |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" => + null; -- NOP, undocumented + when "01111110"|"01111111" => + -- NOP, undocumented + null; +-- 8 BIT LOAD GROUP + when "01010111" => + -- LD A,I + Special_LD <= "100"; + TStates <= "101"; + when "01011111" => + -- LD A,R + Special_LD <= "101"; + TStates <= "101"; + when "01000111" => + -- LD I,A + Special_LD <= "110"; + TStates <= "101"; + when "01001111" => + -- LD R,A + Special_LD <= "111"; + TStates <= "101"; +-- 16 BIT LOAD GROUP + when "01001011"|"01011011"|"01101011"|"01111011" => + -- LD dd,(nn) + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + when 4 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1000"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '1'; + end if; + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + when 5 => + Read_To_Reg <= '1'; + if IR(5 downto 4) = "11" then + Set_BusA_To <= "1001"; + else + Set_BusA_To(2 downto 1) <= IR(5 downto 4); + Set_BusA_To(0) <= '0'; + end if; + when others => null; + end case; + when "01000011"|"01010011"|"01100011"|"01110011" => + -- LD (nn),dd + MCycles <= "101"; + case to_integer(unsigned(MCycle)) is + when 2 => + Inc_PC <= '1'; + LDZ <= '1'; + when 3 => + Set_Addr_To <= aZI; + Inc_PC <= '1'; + LDW <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1000"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + Set_BusB_To(3) <= '0'; + end if; + when 4 => + Inc_WZ <= '1'; + Set_Addr_To <= aZI; + Write <= '1'; + if IR(5 downto 4) = "11" then + Set_BusB_To <= "1001"; + else + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + Set_BusB_To(3) <= '0'; + end if; + when 5 => + Write <= '1'; + when others => null; + end case; + when "10100000" | "10101000" | "10110000" | "10111000" => + -- LDI, LDD, LDIR, LDDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0000"; + Set_Addr_To <= aDE; + if IR(3) = '0' then + IncDec_16 <= "0110"; -- IX + else + IncDec_16 <= "1110"; + end if; + when 3 => + I_BT <= '1'; + TStates <= "101"; + Write <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0101"; -- DE + else + IncDec_16 <= "1101"; + end if; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100001" | "10101001" | "10110001" | "10111001" => + -- CPI, CPD, CPIR, CPDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aXY; + IncDec_16 <= "1100"; -- BC + when 2 => + Set_BusB_To <= "0110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "0111"; + Save_ALU <= '1'; + PreserveC <= '1'; + if IR(3) = '0' then + IncDec_16 <= "0110"; + else + IncDec_16 <= "1110"; + end if; + when 3 => + NoRead <= '1'; + I_BC <= '1'; + TStates <= "101"; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" => + -- NEG + Alu_OP <= "0010"; + Set_BusB_To <= "0111"; + Set_BusA_To <= "1010"; + Read_To_Acc <= '1'; + Save_ALU <= '1'; + when "01000110"|"01001110"|"01100110"|"01101110" => + -- IM 0 + IMode <= "00"; + when "01010110"|"01110110" => + -- IM 1 + IMode <= "01"; + when "01011110"|"01110111" => + -- IM 2 + IMode <= "10"; +-- 16 bit arithmetic + when "01001010"|"01011010"|"01101010"|"01111010" => + -- ADC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0001"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0001"; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '0'; + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01000010"|"01010010"|"01100010"|"01110010" => + -- SBC HL,ss + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "101"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + Set_BusB_To(0) <= '1'; + when others => + Set_BusB_To <= "1000"; + end case; + TStates <= "100"; + when 3 => + NoRead <= '1'; + ALU_Op <= "0011"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + Set_BusA_To(2 downto 0) <= "100"; + case to_integer(unsigned(IR(5 downto 4))) is + when 0|1|2 => + Set_BusB_To(2 downto 1) <= IR(5 downto 4); + when others => + Set_BusB_To <= "1001"; + end case; + when others => + end case; + when "01101111" => + -- RLD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + NoRead <= '1'; + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1101"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RLD <= '1'; + Write <= '1'; + when others => + end case; + when "01100111" => + -- RRD + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 2 => + Set_Addr_To <= aXY; + when 3 => + Read_To_Reg <= '1'; + Set_BusB_To(2 downto 0) <= "110"; + Set_BusA_To(2 downto 0) <= "111"; + ALU_Op <= "1110"; + TStates <= "100"; + Set_Addr_To <= aXY; + Save_ALU <= '1'; + when 4 => + I_RRD <= '1'; + Write <= '1'; + when others => + end case; + when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" => + -- RETI, RETN + MCycles <= "011"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_TO <= aSP; + when 2 => + IncDec_16 <= "0111"; + Set_Addr_To <= aSP; + LDZ <= '1'; + when 3 => + Jump <= '1'; + IncDec_16 <= "0111"; + I_RETN <= '1'; + when others => null; + end case; + when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" => + -- IN r,(C) + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + when 2 => + IORQ <= '1'; + if IR(5 downto 3) /= "110" then + Read_To_Reg <= '1'; + Set_BusA_To(2 downto 0) <= IR(5 downto 3); + end if; + I_INRC <= '1'; + when others => + end case; + when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" => + -- OUT (C),r + -- OUT (C),0 + MCycles <= "010"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To(2 downto 0) <= IR(5 downto 3); + if IR(5 downto 3) = "110" then + Set_BusB_To(3) <= '1'; + end if; + when 2 => + Write <= '1'; + IORQ <= '1'; + when others => + end case; + when "10100010" | "10101010" | "10110010" | "10111010" => + -- INI, IND, INIR, INDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + Set_Addr_To <= aBC; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + IORQ <= '1'; + Set_BusB_To <= "0110"; + Set_Addr_To <= aXY; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + TStates <= "100"; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + when "10100011" | "10101011" | "10110011" | "10111011" => + -- OUTI, OUTD, OTIR, OTDR + MCycles <= "100"; + case to_integer(unsigned(MCycle)) is + when 1 => + TStates <= "101"; + Set_Addr_To <= aXY; + Set_BusB_To <= "1010"; + Set_BusA_To <= "0000"; + Read_To_Reg <= '1'; + Save_ALU <= '1'; + ALU_Op <= "0010"; + when 2 => + Set_BusB_To <= "0110"; + Set_Addr_To <= aBC; + when 3 => + if IR(3) = '0' then + IncDec_16 <= "0010"; + else + IncDec_16 <= "1010"; + end if; + IORQ <= '1'; + Write <= '1'; + I_BTR <= '1'; + when 4 => + NoRead <= '1'; + TStates <= "101"; + when others => null; + end case; + end case; + + end case; + + if Mode = 1 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "011"; + end if; + end if; + + if Mode = 3 then + if MCycle = "001" then +-- TStates <= "100"; + else + TStates <= "100"; + end if; + end if; + + if Mode < 2 then + if MCycle = "110" then + Inc_PC <= '1'; + if Mode = 1 then + Set_Addr_To <= aXY; + TStates <= "100"; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + end if; + if IRB = "00110110" or IRB = "11001011" then + Set_Addr_To <= aNone; + end if; + end if; + if MCycle = "111" then + if Mode = 0 then + TStates <= "101"; + end if; + if ISet /= "01" then + Set_Addr_To <= aXY; + end if; + Set_BusB_To(2 downto 0) <= SSS; + Set_BusB_To(3) <= '0'; + if IRB = "00110110" or ISet = "01" then + -- LD (HL),n + Inc_PC <= '1'; + else + NoRead <= '1'; + end if; + end if; + end if; + + end process; + +end; diff --git a/modules/cpu-t80/T80_Pack.vhd b/modules/cpu-t80/T80_Pack.vhd new file mode 100644 index 0000000..ac7d34d --- /dev/null +++ b/modules/cpu-t80/T80_Pack.vhd @@ -0,0 +1,208 @@ +-- +-- Z80 compatible microprocessor core +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package T80_Pack is + + component T80 + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + IORQ : out std_logic; + NoRead : out std_logic; + Write : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DInst : in std_logic_vector(7 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0); + MC : out std_logic_vector(2 downto 0); + TS : out std_logic_vector(2 downto 0); + IntCycle_n : out std_logic; + IntE : out std_logic; + Stop : out std_logic + ); + end component; + + component T80_Reg + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); + end component; + + component T80_MCode + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + IR : in std_logic_vector(7 downto 0); + ISet : in std_logic_vector(1 downto 0); + MCycle : in std_logic_vector(2 downto 0); + F : in std_logic_vector(7 downto 0); + NMICycle : in std_logic; + IntCycle : in std_logic; + MCycles : out std_logic_vector(2 downto 0); + TStates : out std_logic_vector(2 downto 0); + Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD + Inc_PC : out std_logic; + Inc_WZ : out std_logic; + IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc + Read_To_Reg : out std_logic; + Read_To_Acc : out std_logic; + Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F + Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0 + ALU_Op : out std_logic_vector(3 downto 0); + -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None + Save_ALU : out std_logic; + PreserveC : out std_logic; + Arith16 : out std_logic; + Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI + IORQ : out std_logic; + Jump : out std_logic; + JumpE : out std_logic; + JumpXY : out std_logic; + Call : out std_logic; + RstP : out std_logic; + LDZ : out std_logic; + LDW : out std_logic; + LDSPHL : out std_logic; + Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None + ExchangeDH : out std_logic; + ExchangeRp : out std_logic; + ExchangeAF : out std_logic; + ExchangeRS : out std_logic; + I_DJNZ : out std_logic; + I_CPL : out std_logic; + I_CCF : out std_logic; + I_SCF : out std_logic; + I_RETN : out std_logic; + I_BT : out std_logic; + I_BC : out std_logic; + I_BTR : out std_logic; + I_RLD : out std_logic; + I_RRD : out std_logic; + I_INRC : out std_logic; + SetDI : out std_logic; + SetEI : out std_logic; + IMode : out std_logic_vector(1 downto 0); + Halt : out std_logic; + NoRead : out std_logic; + Write : out std_logic + ); + end component; + + component T80_ALU + generic( + Mode : integer := 0; + Flag_C : integer := 0; + Flag_N : integer := 1; + Flag_P : integer := 2; + Flag_X : integer := 3; + Flag_H : integer := 4; + Flag_Y : integer := 5; + Flag_Z : integer := 6; + Flag_S : integer := 7 + ); + port( + Arith16 : in std_logic; + Z16 : in std_logic; + ALU_Op : in std_logic_vector(3 downto 0); + IR : in std_logic_vector(5 downto 0); + ISet : in std_logic_vector(1 downto 0); + BusA : in std_logic_vector(7 downto 0); + BusB : in std_logic_vector(7 downto 0); + F_In : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(7 downto 0); + F_Out : out std_logic_vector(7 downto 0) + ); + end component; + +end; diff --git a/modules/cpu-t80/T80_Reg.vhd b/modules/cpu-t80/T80_Reg.vhd new file mode 100644 index 0000000..828485f --- /dev/null +++ b/modules/cpu-t80/T80_Reg.vhd @@ -0,0 +1,105 @@ +-- +-- T80 Registers, technology independent +-- +-- Version : 0244 +-- +-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t51/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0242 : Initial release +-- +-- 0244 : Changed to single register file +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +entity T80_Reg is + port( + Clk : in std_logic; + CEN : in std_logic; + WEH : in std_logic; + WEL : in std_logic; + AddrA : in std_logic_vector(2 downto 0); + AddrB : in std_logic_vector(2 downto 0); + AddrC : in std_logic_vector(2 downto 0); + DIH : in std_logic_vector(7 downto 0); + DIL : in std_logic_vector(7 downto 0); + DOAH : out std_logic_vector(7 downto 0); + DOAL : out std_logic_vector(7 downto 0); + DOBH : out std_logic_vector(7 downto 0); + DOBL : out std_logic_vector(7 downto 0); + DOCH : out std_logic_vector(7 downto 0); + DOCL : out std_logic_vector(7 downto 0) + ); +end T80_Reg; + +architecture rtl of T80_Reg is + + type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0); + signal RegsH : Register_Image(0 to 7); + signal RegsL : Register_Image(0 to 7); + +begin + + process (Clk) + begin + if Clk'event and Clk = '1' then + if CEN = '1' then + if WEH = '1' then + RegsH(to_integer(unsigned(AddrA))) <= DIH; + end if; + if WEL = '1' then + RegsL(to_integer(unsigned(AddrA))) <= DIL; + end if; + end if; + end if; + end process; + + DOAH <= RegsH(to_integer(unsigned(AddrA))); + DOAL <= RegsL(to_integer(unsigned(AddrA))); + DOBH <= RegsH(to_integer(unsigned(AddrB))); + DOBL <= RegsL(to_integer(unsigned(AddrB))); + DOCH <= RegsH(to_integer(unsigned(AddrC))); + DOCL <= RegsL(to_integer(unsigned(AddrC))); + +end; diff --git a/modules/cpu-t80/T80se.vhd b/modules/cpu-t80/T80se.vhd new file mode 100644 index 0000000..ac8886a --- /dev/null +++ b/modules/cpu-t80/T80se.vhd @@ -0,0 +1,184 @@ +-- +-- Z80 compatible microprocessor core, synchronous top level with clock enable +-- Different timing than the original z80 +-- Inputs needs to be synchronous and outputs may glitch +-- +-- Version : 0242 +-- +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- Please report bugs to the author, but before you do so, please +-- make sure that this is not a derivative work and that +-- you have the latest version of this file. +-- +-- The latest version of this file can be found at: +-- http://www.opencores.org/cvsweb.shtml/t80/ +-- +-- Limitations : +-- +-- File history : +-- +-- 0235 : First release +-- +-- 0236 : Added T2Write generic +-- +-- 0237 : Fixed T2Write with wait state +-- +-- 0238 : Updated for T80 interface change +-- +-- 0240 : Updated for T80 interface change +-- +-- 0242 : Updated for T80 interface change +-- + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.T80_Pack.all; + +entity T80se is + generic( + Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB + T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2 + IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle + ); + port( + RESET_n : in std_logic; + CLK_n : in std_logic; + CLKEN : in std_logic; + WAIT_n : in std_logic; + INT_n : in std_logic; + NMI_n : in std_logic; + BUSRQ_n : in std_logic; + M1_n : out std_logic; + MREQ_n : out std_logic; + IORQ_n : out std_logic; + RD_n : out std_logic; + WR_n : out std_logic; + RFSH_n : out std_logic; + HALT_n : out std_logic; + BUSAK_n : out std_logic; + A : out std_logic_vector(15 downto 0); + DI : in std_logic_vector(7 downto 0); + DO : out std_logic_vector(7 downto 0) + ); +end T80se; + +architecture rtl of T80se is + + signal IntCycle_n : std_logic; + signal NoRead : std_logic; + signal Write : std_logic; + signal IORQ : std_logic; + signal DI_Reg : std_logic_vector(7 downto 0); + signal MCycle : std_logic_vector(2 downto 0); + signal TState : std_logic_vector(2 downto 0); + +begin + + u0 : T80 + generic map( + Mode => Mode, + IOWait => IOWait) + port map( + CEN => CLKEN, + M1_n => M1_n, + IORQ => IORQ, + NoRead => NoRead, + Write => Write, + RFSH_n => RFSH_n, + HALT_n => HALT_n, + WAIT_n => Wait_n, + INT_n => INT_n, + NMI_n => NMI_n, + RESET_n => RESET_n, + BUSRQ_n => BUSRQ_n, + BUSAK_n => BUSAK_n, + CLK_n => CLK_n, + A => A, + DInst => DI, + DI => DI_Reg, + DO => DO, + MC => MCycle, + TS => TState, + IntCycle_n => IntCycle_n); + + process (RESET_n, CLK_n) + begin + if RESET_n = '0' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + DI_Reg <= "00000000"; + elsif CLK_n'event and CLK_n = '1' then + if CLKEN = '1' then + RD_n <= '1'; + WR_n <= '1'; + IORQ_n <= '1'; + MREQ_n <= '1'; + if MCycle = "001" then + if TState = "001" or (TState = "010" and Wait_n = '0') then + RD_n <= not IntCycle_n; + MREQ_n <= not IntCycle_n; + IORQ_n <= IntCycle_n; + end if; + if TState = "011" then + MREQ_n <= '0'; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then + RD_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + if T2Write = 0 then + if TState = "010" and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + else + if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then + WR_n <= '0'; + IORQ_n <= not IORQ; + MREQ_n <= IORQ; + end if; + end if; + end if; + if TState = "010" and Wait_n = '1' then + DI_Reg <= DI; + end if; + end if; + end if; + end process; + +end; diff --git a/modules/cpu-t80/index.qip b/modules/cpu-t80/index.qip new file mode 100644 index 0000000..5bc6a7b --- /dev/null +++ b/modules/cpu-t80/index.qip @@ -0,0 +1,6 @@ +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80_ALU.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80_MCode.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80_Pack.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80_Reg.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "T80se.vhd"] \ No newline at end of file diff --git a/modules/pocket-dataloader/data_loader.sv b/modules/pocket-dataloader/data_loader.sv new file mode 100644 index 0000000..ea181fa --- /dev/null +++ b/modules/pocket-dataloader/data_loader.sv @@ -0,0 +1,223 @@ +// MIT License + +// Copyright (c) 2022 Adam Gastineau + +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: + +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. + +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +// +//////////////////////////////////////////////////////////////////////////////// + +// A data loader for consuming APF bridge writes and directing them to some storage medium +// +// This takes the 32 bit words from APF, and splits it into four / OUTPUT_WORD_SIZE words (4 separate bytes, or 2 16-bit words). +// You can configure the cycle delay by setting WRITE_MEM_CLOCK_DELAY +module data_loader #( + // Upper 4 bits of address + parameter ADDRESS_MASK_UPPER_4 = 0, + parameter ADDRESS_SIZE = 14, + + // Number of clk_memory cycles to delay each write output + // Min 4. Component will assert this value is within the valid range + // Be aware that APF sends data every ~75 74MHz cycles, so you cannot send data slower than this + parameter WRITE_MEM_CLOCK_DELAY = 4, + + // Number of clk_memory cycles to hold the write_en signal high + // Min 1. Component will assert this value is within the valid range + parameter WRITE_MEM_EN_CYCLE_LENGTH = 1, + + // Word size in number of bytes. Can either be 1 (output 8 bits), or 2 (output 16 bits) + // Component will assert this value is within the valid range + parameter OUTPUT_WORD_SIZE = 1 +) ( + input wire clk_74a, + input wire clk_memory, + + input wire bridge_wr, + input wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire [31:0] bridge_wr_data, + + // These outputs are synced to the memory clock + output reg write_en = 0, + output reg [ADDRESS_SIZE:0] write_addr = 0, + output reg [8 * OUTPUT_WORD_SIZE - 1:0] write_data = 0 +); + + `define MAX(x, y) ((x > y) ? x : y) + + localparam WORD_SIZE = 8 * OUTPUT_WORD_SIZE; + + // Only use the lower 28 bits of the address + localparam FIFO_SIZE = WORD_SIZE + 28; + + wire mem_empty; + + wire [FIFO_SIZE - 1:0] fifo_out; + + reg read_req = 0; + reg write_req = 0; + reg [31:0] shift_data; + reg [27:0] buff_bridge_addr; + + wire [FIFO_SIZE - 1:0] fifo_in = {shift_data[WORD_SIZE-1:0], buff_bridge_addr[27:0]}; + + dcfifo dcfifo_component ( + .data(fifo_in), + .rdclk(clk_memory), + .rdreq(read_req), + .wrclk(clk_74a), + .wrreq(write_req), + .q(fifo_out), + .rdempty(mem_empty) + // .wrempty(), + // .aclr(), + // .eccstatus(), + // .rdfull(), + // .rdusedw(), + // .wrfull(), + // .wrusedw() + ); + defparam dcfifo_component.clocks_are_synchronized = "FALSE", + dcfifo_component.intended_device_family = "Cyclone V", dcfifo_component.lpm_numwords = 4, + dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", + dcfifo_component.lpm_width = FIFO_SIZE, dcfifo_component.lpm_widthu = 2, + dcfifo_component.overflow_checking = "OFF", dcfifo_component.rdsync_delaypipe = 5, + dcfifo_component.underflow_checking = "OFF", dcfifo_component.use_eab = "OFF", + dcfifo_component.wrsync_delaypipe = 5; + + /// APF to Mem clock + + reg prev_bridge_wr = 0; + reg [2:0] write_count = 0; + reg [2:0] write_state = 0; + + localparam WRITE_START = 1; + localparam WRITE_REQ_SHIFT = 2; + + // Receive APF writes and buffer them into the memory clock domain + always @(posedge clk_74a) begin + prev_bridge_wr <= bridge_wr; + + if (~prev_bridge_wr && bridge_wr && bridge_addr[31:28] == ADDRESS_MASK_UPPER_4) begin + // Beginning APF write to core + write_state <= WRITE_REQ_SHIFT; + write_req <= 1; + write_count <= 0; + + shift_data <= bridge_endian_little ? bridge_wr_data : { + bridge_wr_data[7:0], bridge_wr_data[15:8], bridge_wr_data[23:16], bridge_wr_data[31:24] + }; + + buff_bridge_addr <= bridge_addr[27:0]; + end + + case (write_state) + WRITE_START: begin + write_req <= 1; + + write_state <= WRITE_REQ_SHIFT; + end + WRITE_REQ_SHIFT: begin + write_req <= 0; + + // We will be writing again in the next cycle + shift_data <= {8'h0, shift_data[31:WORD_SIZE]}; + buff_bridge_addr <= buff_bridge_addr + OUTPUT_WORD_SIZE; + + write_count <= write_count + 1; + + if (write_count == (4 / OUTPUT_WORD_SIZE) - 1) begin + // Finished write + write_state <= 0; + end else begin + write_state <= WRITE_START; + end + end + endcase + end + + /// Mem clock to core + + reg [5:0] read_state = 0; + + localparam READ_DELAY = 1; + localparam READ_WRITE = 2; + localparam READ_WRITE_EN_CYCLE_OFF = READ_WRITE + WRITE_MEM_EN_CYCLE_LENGTH; + localparam READ_WRITE_END_DEFAULT = WRITE_MEM_CLOCK_DELAY - 1; + // Must use max to prevent READ_WRITE_END from being the same as READ_WRITE_EN_CYCLE_OFF + localparam READ_WRITE_END = + `MAX(READ_WRITE_END_DEFAULT, READ_WRITE_EN_CYCLE_OFF + 1); + localparam HAS_DELAY = READ_WRITE_END_DEFAULT > READ_WRITE_EN_CYCLE_OFF; + + always @(posedge clk_memory) begin + if (read_state != 0) begin + read_state <= read_state + 1; + end else if (~mem_empty) begin + // Start read + read_state <= READ_DELAY; + read_req <= 1; + end + + case (read_state) + READ_DELAY: begin + read_req <= 0; + write_en <= 0; + end + READ_WRITE: begin + // Read data is available + write_en <= 1; + + // Lowest 28 bits are the address + write_addr <= fifo_out[27:0]; + + write_data <= fifo_out[WORD_SIZE+27:28]; + + read_req <= 0; + end + READ_WRITE_EN_CYCLE_OFF: begin + write_en <= 0; + + if (!HAS_DELAY) begin + // No extra delay, immediately go back to start + read_state <= 0; + end + end + READ_WRITE_END: begin + read_state <= 0; + end + endcase + end + + initial begin + // Verify parameters + if (WRITE_MEM_CLOCK_DELAY < 4) begin + $error("WRITE_MEM_CLOCK_DELAY has a minimum value of 4. Received %d", WRITE_MEM_CLOCK_DELAY); + end + + if (WRITE_MEM_EN_CYCLE_LENGTH < 1 || WRITE_MEM_EN_CYCLE_LENGTH >= WRITE_MEM_CLOCK_DELAY - 2) begin + $error( + "WRITE_MEM_EN_CYCLE_LENGTH must be between 1 and %d (inclusive, based off of WRITE_MEM_CLOCK_DELAY). Received %d", + WRITE_MEM_CLOCK_DELAY - 2 - 1, WRITE_MEM_EN_CYCLE_LENGTH); + end + + if (OUTPUT_WORD_SIZE < 1 || OUTPUT_WORD_SIZE > 2) begin + $error("OUTPUT_WORD_SIZE must be 1 or 2. Received %d", OUTPUT_WORD_SIZE); + end + end + +endmodule \ No newline at end of file diff --git a/modules/pocket-dataloader/index.qip b/modules/pocket-dataloader/index.qip new file mode 100644 index 0000000..9f277f4 --- /dev/null +++ b/modules/pocket-dataloader/index.qip @@ -0,0 +1 @@ +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "data_loader.sv"] diff --git a/modules/pocket-i2s/index.qip b/modules/pocket-i2s/index.qip new file mode 100644 index 0000000..f99c1f8 --- /dev/null +++ b/modules/pocket-i2s/index.qip @@ -0,0 +1 @@ +set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "pocket_i2s.sv"] diff --git a/modules/pocket-i2s/pocket_i2s.sv b/modules/pocket-i2s/pocket_i2s.sv new file mode 100644 index 0000000..1fd3603 --- /dev/null +++ b/modules/pocket-i2s/pocket_i2s.sv @@ -0,0 +1,77 @@ +//------------------------------------------------------------------------------ +// Generic I2S audio interface for the Analogue Pocket +//------------------------------------------------------------------------------ +module pocket_i2s + ( + input iCLK_74, + input [BITS-1:0] AUDIO_L, + input [BITS-1:0] AUDIO_R, + + output wire I2S_MCLK, + output wire I2S_DAC, + output wire I2S_LRCK + ); + + parameter BITS = 16; + parameter STEREO = 0; + parameter SIGNED = 0; + + localparam [20:0] CYCLE_48KHZ = 21'd122880 * 2; + + wire [BITS-1:0] audio_left = ~SIGNED ? AUDIO_L : {~AUDIO_L[BITS-1],AUDIO_L[BITS-2:0]}; + wire [BITS-1:0] audio_right = STEREO ? ~SIGNED ? AUDIO_R : {~AUDIO_R[BITS-1],AUDIO_R[BITS-2:0]} : audio_left; + + assign I2S_MCLK = audio_mclk; + assign I2S_DAC = audio_dac; + assign I2S_LRCK = audio_lrck; + + // Generate MCLK = 12.288mhz with fractional accumulator + reg [21:0] audio_accum; + reg audio_mclk; + always @(posedge iCLK_74) begin + audio_accum <= audio_accum + CYCLE_48KHZ; + if(audio_accum >= 21'd742500) begin + audio_mclk <= ~audio_mclk; + audio_accum <= audio_accum - 21'd742500 + CYCLE_48KHZ; + end + end + + // Generate SCLK = 3.072mhz by dividing MCLK by 4 + reg [1:0] aud_mclk_divider; + wire audio_sclk = aud_mclk_divider[1] /* synthesis keep*/; + reg audio_lrck_1; + always @(posedge audio_mclk) begin + aud_mclk_divider <= aud_mclk_divider + 1'b1; + end + + // Synchronize audio samples coming from the core + wire [31:0] audio_sampledata_s; + synch_3 #(.WIDTH(32)) sync_snd({audio_left, audio_right} ,audio_sampledata_s, audio_sclk); + + reg [31:0] audio_sampshift; + reg [4:0] audio_lrck_cnt; + reg audio_lrck; + reg audio_dac; + reg audio_nextsamp; + always @(negedge audio_sclk) begin + audio_nextsamp <= 0; + // Output the next bit + audio_dac <= audio_sampshift[31]; + // 48khz * 64 + audio_lrck_cnt <= audio_lrck_cnt + 1'b1; + if (audio_lrck_cnt == 31) begin + // switch channels + audio_lrck <= ~audio_lrck; + + // Reload sample shifter + if (~audio_lrck) begin + audio_sampshift <= audio_sampledata_s; + end + end + else if (audio_lrck_cnt < 16) begin + // only shift for 16 clocks per channel + audio_sampshift <= {audio_sampshift[30:0], 1'b0}; + end + end + +endmodule diff --git a/modules/pocket-joypad/index.qip b/modules/pocket-joypad/index.qip new file mode 100644 index 0000000..05c286c --- /dev/null +++ b/modules/pocket-joypad/index.qip @@ -0,0 +1 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "joypad.v"] diff --git a/modules/pocket-joypad/joypad.v b/modules/pocket-joypad/joypad.v new file mode 100644 index 0000000..0986441 --- /dev/null +++ b/modules/pocket-joypad/joypad.v @@ -0,0 +1,66 @@ +//------------------------------------------------------------------------------ +// SPDX-License-Identifier: MPL-2.0 +// SPDX-FileType: SOURCE +// SPDX-FileCopyrightText: (c) 2022 Marcus Andrade +//------------------------------------------------------------------------------ +// Generic Gamepad interface for the Analogue Pocket +//------------------------------------------------------------------------------ + +module pocket_gamepad + ( + input iCLK, + input [15:0] iJOY, + + output wire PAD_U, + output wire PAD_D, + output wire PAD_L, + output wire PAD_R, + + output wire BTN_A, + output wire BTN_B, + output wire BTN_X, + output wire BTN_Y, + + output wire BTN_L1, + output wire BTN_R1, + + output wire BTN_L2, + output wire BTN_R2, + + output wire BTN_L3, + output wire BTN_R3, + + output wire BTN_SE, + output wire BTN_ST + ); + + assign PAD_U = joy_keys_s[0]; + assign PAD_D = joy_keys_s[1]; + assign PAD_L = joy_keys_s[2]; + assign PAD_R = joy_keys_s[3]; + + assign BTN_A = joy_keys_s[4]; + assign BTN_B = joy_keys_s[5]; + assign BTN_X = joy_keys_s[6]; + assign BTN_Y = joy_keys_s[7]; + + assign BTN_L1 = joy_keys_s[8]; + assign BTN_R1 = joy_keys_s[9]; + + assign BTN_L2 = joy_keys_s[10]; + assign BTN_R2 = joy_keys_s[11]; + + assign BTN_L3 = joy_keys_s[12]; + assign BTN_R3 = joy_keys_s[13]; + + assign BTN_SE = joy_keys_s[14]; + assign BTN_ST = joy_keys_s[15]; + + reg [15:0] joy_keys_s; + + // Sync Joystick to Core Clock + always @ (posedge iCLK) begin + joy_keys_s <= iJOY; + end + +endmodule diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Battles.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Battles.json new file mode 100644 index 0000000..980226c --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Battles.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "battles2.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Xevios.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Xevios.json new file mode 100644 index 0000000..c41db43 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Bootleg/Xevios.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevios.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Gaous.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Gaous.json new file mode 100644 index 0000000..6e129ee --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Gaous.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "gaous.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2002.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2002.json new file mode 100644 index 0000000..8c130de --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2002.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevioush.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2003.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2003.json new file mode 100644 index 0000000..84cab79 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2003.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevious3.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2004.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2004.json new file mode 100644 index 0000000..3ff0a32 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2004.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevious4.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2005.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2005.json new file mode 100644 index 0000000..8b3f639 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious 2005.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevious5.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious Black.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious Black.json new file mode 100644 index 0000000..621e6b7 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Homebrew/Xevious Black.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xeviblk.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": 0 + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Super Xevious.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Super Xevious.json new file mode 100644 index 0000000..4b07353 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Super Xevious.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "sxevious.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": "0x8000" + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/boogermann.xevious/Xevious.json b/pkg/pocket/Assets/xevious/boogermann.xevious/Xevious.json new file mode 100644 index 0000000..b3e21f3 --- /dev/null +++ b/pkg/pocket/Assets/xevious/boogermann.xevious/Xevious.json @@ -0,0 +1,25 @@ +{ + "instance": { + "magic": "APF_VER_1", + "variant_select": { + "id": 777, + "select": false + }, + "data_slots": [ + { + "id": 1, + "filename": "xevious.rom" + } + ], + "memory_writes": [ + { + "address": "0xf9000000", + "data": "0x1d00" + }, + { + "address": "0xf9000004", + "data": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Assets/xevious/common/.gitkeep b/pkg/pocket/Assets/xevious/common/.gitkeep new file mode 100644 index 0000000..40068e6 --- /dev/null +++ b/pkg/pocket/Assets/xevious/common/.gitkeep @@ -0,0 +1,2 @@ +9d0a5b6f076a2451245ef89a5f4a81db sxevious.rom +1b707668eb52408088e47c0f823f9fed xevious.rom diff --git a/pkg/pocket/Cores/boogermann.xevious/audio.json b/pkg/pocket/Cores/boogermann.xevious/audio.json new file mode 100644 index 0000000..ea8e2f4 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/audio.json @@ -0,0 +1,5 @@ +{ + "audio": { + "magic": "APF_VER_1" + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/core.json b/pkg/pocket/Cores/boogermann.xevious/core.json new file mode 100644 index 0000000..bc617bd --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/core.json @@ -0,0 +1,36 @@ +{ + "core": { + "magic": "APF_VER_1", + "metadata": { + "platform_ids": [ + "xevious" + ], + "shortname": "xevious", + "description": "Xevious is a shoot 'em up video game franchise published by Bandai Namco Entertainment", + "author": "boogermann", + "url": "https://github.com/opengateware/arcade-xevious", + "version": "0.1.0", + "date_release": "2022-09-10" + }, + "framework": { + "target_product": "Analogue Pocket", + "version_required": "1.1", + "sleep_supported": false, + "dock": { + "supported": true, + "analog_output": false + }, + "hardware": { + "link_port": false, + "cartridge_adapter": -1 + } + }, + "cores": [ + { + "name": "default", + "id": 0, + "filename": "bitstream.rbf_r" + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/data.json b/pkg/pocket/Cores/boogermann.xevious/data.json new file mode 100644 index 0000000..54b0079 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/data.json @@ -0,0 +1,26 @@ +{ + "data": { + "magic": "APF_VER_1", + "data_slots": [ + { + "name": "Arcade Game", + "id": 0, + "required": true, + "parameters": "0x113", + "extensions": [ + "json" + ] + }, + { + "name": "ROM", + "id": 1, + "required": true, + "parameters": 0, + "extensions": [ + "rom" + ], + "address": "0x00000000" + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/icon.bin b/pkg/pocket/Cores/boogermann.xevious/icon.bin new file mode 100644 index 0000000..cb4e46d Binary files /dev/null and b/pkg/pocket/Cores/boogermann.xevious/icon.bin differ diff --git a/pkg/pocket/Cores/boogermann.xevious/icon.png b/pkg/pocket/Cores/boogermann.xevious/icon.png new file mode 100644 index 0000000..255e6ec Binary files /dev/null and b/pkg/pocket/Cores/boogermann.xevious/icon.png differ diff --git a/pkg/pocket/Cores/boogermann.xevious/info.txt b/pkg/pocket/Cores/boogermann.xevious/info.txt new file mode 100644 index 0000000..7f146ad --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/info.txt @@ -0,0 +1 @@ +Xevious (pronounced 'zeevious') is a vertically-scrolling shoot-em-up in which the player pilots the heavily-armed 'Solvalou' combat ship and must destroy the evil Xevious forces trying to take over the planet. The Solvalou is equipped with two weapon systems; the forwards-firing "air zapper" for shooting air-based enemies and 'blaster bombs', for destroying ground-based enemies. To enable accurate targetting of the air-to-ground blaster bombs, a white and blue targeting indicator is situated in front of the Solvalou. This flashes when an enemy is in its sights. diff --git a/pkg/pocket/Cores/boogermann.xevious/input.json b/pkg/pocket/Cores/boogermann.xevious/input.json new file mode 100644 index 0000000..e17d441 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/input.json @@ -0,0 +1,5 @@ +{ + "input": { + "magic": "APF_VER_1" + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/interact.json b/pkg/pocket/Cores/boogermann.xevious/interact.json new file mode 100644 index 0000000..f061588 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/interact.json @@ -0,0 +1,7 @@ +{ + "interact": { + "magic": "APF_VER_1", + "variables": [], + "messages": [] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/variants.json b/pkg/pocket/Cores/boogermann.xevious/variants.json new file mode 100644 index 0000000..c2dbd41 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/variants.json @@ -0,0 +1,6 @@ +{ + "variants": { + "magic": "APF_VER_1", + "variant_list": [] + } +} \ No newline at end of file diff --git a/pkg/pocket/Cores/boogermann.xevious/video.json b/pkg/pocket/Cores/boogermann.xevious/video.json new file mode 100644 index 0000000..0b18170 --- /dev/null +++ b/pkg/pocket/Cores/boogermann.xevious/video.json @@ -0,0 +1,15 @@ +{ + "video": { + "magic": "APF_VER_1", + "scaler_modes": [ + { + "width": 288, + "height": 224, + "aspect_w": 9, + "aspect_h": 7, + "rotation": 90, + "mirror": 0 + } + ] + } +} \ No newline at end of file diff --git a/pkg/pocket/Platforms/_images/xevious.bin b/pkg/pocket/Platforms/_images/xevious.bin new file mode 100644 index 0000000..f8765f8 Binary files /dev/null and b/pkg/pocket/Platforms/_images/xevious.bin differ diff --git a/pkg/pocket/Platforms/_images/xevious.png b/pkg/pocket/Platforms/_images/xevious.png new file mode 100644 index 0000000..dc4c431 Binary files /dev/null and b/pkg/pocket/Platforms/_images/xevious.png differ diff --git a/pkg/pocket/Platforms/xevious.json b/pkg/pocket/Platforms/xevious.json new file mode 100644 index 0000000..e41d2f7 --- /dev/null +++ b/pkg/pocket/Platforms/xevious.json @@ -0,0 +1,8 @@ +{ + "platform": { + "category": "Arcade", + "name": "Xevious", + "manufacturer": "Namco", + "year": 1983 + } +} \ No newline at end of file diff --git a/pkg/rom-recipes/Assets/xevious/common/checklist.md5 b/pkg/rom-recipes/Assets/xevious/common/checklist.md5 new file mode 100644 index 0000000..093b9d8 --- /dev/null +++ b/pkg/rom-recipes/Assets/xevious/common/checklist.md5 @@ -0,0 +1,10 @@ +5de9f3130b7686c85b60bac3310ffd05 battles2.rom +93ea876a4f88e6ef65535a9136de262b gaous.rom +9d0a5b6f076a2451245ef89a5f4a81db sxevious.rom +1b707668eb52408088e47c0f823f9fed xeviblk.rom +72677feef0d6f73b430ee6d196e3a8e9 xevios.rom +1b707668eb52408088e47c0f823f9fed xevious.rom +52f7011a54a658518b5e0c3c1555f307 xevious3.rom +875553add70eb03707ed3337a6f7e3d2 xevious4.rom +8a193b74526cf07912481e45622d1294 xevious5.rom +2b866069ba0ae5c6793f2bd318abbf75 xevioush.rom diff --git a/pkg/rom-recipes/roms/_PUT_YOUR_ROMS_HERE b/pkg/rom-recipes/roms/_PUT_YOUR_ROMS_HERE new file mode 100644 index 0000000..e69de29 diff --git a/pkg/rom-recipes/tools/make_roms.ps1 b/pkg/rom-recipes/tools/make_roms.ps1 new file mode 100644 index 0000000..1434093 --- /dev/null +++ b/pkg/rom-recipes/tools/make_roms.ps1 @@ -0,0 +1,23 @@ +#!/usr/bin/pwsh -Command + +$coreName = "xevious" +$currentPath = $(Get-Item $($MyInvocation.MyCommand.Path)).DirectoryName +$fileNames = Get-ChildItem -Path "$currentPath\..\xml" -Recurse -Include *.mra + +try { + foreach ($f in $fileNames){ + $outfile = $f.FullName + Write-Host "Converting $outfile ..." + orca.exe -z ..\roms -O ..\Assets\$coreName\common $outfile + } +} catch { + Write-Host "Error: $($_.Exception.Message)" + exit 1 +} finally { + Write-Host "Done." + Write-Host "Copy your rom files to Assets/$coreName/common" + Write-Host "Enjoy!" + timeout /t 10 +} + +exit 0 diff --git a/pkg/rom-recipes/tools/make_roms.sh b/pkg/rom-recipes/tools/make_roms.sh new file mode 100644 index 0000000..056027a --- /dev/null +++ b/pkg/rom-recipes/tools/make_roms.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash + +CORE=xevious +PARENT=$(dirname $PWD) +XML=$PARENT/xml +ROMS=$PARENT/roms +ASSETS=$PARENT/Assets/$CORE/common + +find ${XML} -name '*.mra' | while read line; do + echo "Processing file '$line'" + orca -z ${ROMS} -O ${ASSETS} "$line" +done + +exit 0 \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Bootleg/Battles (set 2).mra b/pkg/rom-recipes/xml/Bootleg/Battles (set 2).mra new file mode 100644 index 0000000..94c59e9 --- /dev/null +++ b/pkg/rom-recipes/xml/Bootleg/Battles (set 2).mra @@ -0,0 +1,28 @@ + + battles2 + no + yes + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Bootleg/Xevios.mra b/pkg/rom-recipes/xml/Bootleg/Xevios.mra new file mode 100644 index 0000000..e3f610a --- /dev/null +++ b/pkg/rom-recipes/xml/Bootleg/Xevios.mra @@ -0,0 +1,28 @@ + + xevios + no + yes + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Gaous - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Gaous - HBMame.mra new file mode 100644 index 0000000..983846b --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Gaous - HBMame.mra @@ -0,0 +1,28 @@ + + gaous + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Xevious 2002 - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Xevious 2002 - HBMame.mra new file mode 100644 index 0000000..40256bf --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Xevious 2002 - HBMame.mra @@ -0,0 +1,28 @@ + + xevioush + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Xevious 2003 - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Xevious 2003 - HBMame.mra new file mode 100644 index 0000000..d5563d5 --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Xevious 2003 - HBMame.mra @@ -0,0 +1,28 @@ + + xevious3 + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Xevious 2004 - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Xevious 2004 - HBMame.mra new file mode 100644 index 0000000..56f2471 --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Xevious 2004 - HBMame.mra @@ -0,0 +1,28 @@ + + xevious4 + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Xevious 2005 - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Xevious 2005 - HBMame.mra new file mode 100644 index 0000000..60c86a7 --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Xevious 2005 - HBMame.mra @@ -0,0 +1,28 @@ + + xevious5 + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Homebrew/Xevious Black - HBMame.mra b/pkg/rom-recipes/xml/Homebrew/Xevious Black - HBMame.mra new file mode 100644 index 0000000..9e8ca1e --- /dev/null +++ b/pkg/rom-recipes/xml/Homebrew/Xevious Black - HBMame.mra @@ -0,0 +1,28 @@ + + xeviblk + yes + no + 0240 + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Super Xevious.mra b/pkg/rom-recipes/xml/Super Xevious.mra new file mode 100644 index 0000000..f2ffc96 --- /dev/null +++ b/pkg/rom-recipes/xml/Super Xevious.mra @@ -0,0 +1,62 @@ + + no + no + sxevious + 0240 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 00008510 004d 00 24 + 00008024 0003 00 00 + 00008025 0001 40 40 + + + + + \ No newline at end of file diff --git a/pkg/rom-recipes/xml/Xevious.mra b/pkg/rom-recipes/xml/Xevious.mra new file mode 100644 index 0000000..2c62b15 --- /dev/null +++ b/pkg/rom-recipes/xml/Xevious.mra @@ -0,0 +1,63 @@ + + no + no + xevious + 0240 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 00 FF FF FF 00 FF 00 02 00 02 00 01 00 FF 02 00 + 00 00 85 10 00 4D 00 24 + 00 00 80 24 00 03 00 00 + 00 00 80 25 00 01 40 40 + + + + + \ No newline at end of file diff --git a/platform/pocket/apf.qip b/platform/pocket/apf.qip new file mode 100644 index 0000000..2fd9aea --- /dev/null +++ b/platform/pocket/apf.qip @@ -0,0 +1,7 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "apf_top.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "common.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_bridge_peripheral.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "io_pad_controller.v"] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "apf_constraints.sdc"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_datatable.qip"] diff --git a/platform/pocket/apf_constraints.sdc b/platform/pocket/apf_constraints.sdc new file mode 100644 index 0000000..b168b55 --- /dev/null +++ b/platform/pocket/apf_constraints.sdc @@ -0,0 +1,12 @@ +# +# APF constraints +# Do not edit this file. +# +# Add your own constraints in the \core_constraints.sdc in the core directory, which will also be loaded. + +create_clock -name clk_74a -period 13.468 [get_ports clk_74a] +create_clock -name clk_74b -period 13.468 [get_ports clk_74b] +create_clock -name bridge_spiclk -period 13.468 [get_ports bridge_spiclk] + +# autogenerate PLL clock names for use down below +derive_pll_clocks diff --git a/platform/pocket/apf_top.v b/platform/pocket/apf_top.v new file mode 100644 index 0000000..43f9021 --- /dev/null +++ b/platform/pocket/apf_top.v @@ -0,0 +1,471 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 6515C - Analogue Pocket main unit +// SOCRATES FPGA +// +// 2022-06-28 Analogue + +`default_nettype none + +module apf_top ( +/////////////////////////////////////////////////// +// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + +input wire clk_74a, // mainclk1 +input wire clk_74b, // mainclk1 + +/////////////////////////////////////////////////// +// cartridge interface +// switches between 3.3v and 5v mechanically +// output enable for multibit translators controlled by PIC32 + +// GBA AD[15:8] +inout wire [7:0] cart_tran_bank2, +output wire cart_tran_bank2_dir, + +// GBA AD[7:0] +inout wire [7:0] cart_tran_bank3, +output wire cart_tran_bank3_dir, + +// GBA A[23:16] +inout wire [7:0] cart_tran_bank1, +output wire cart_tran_bank1_dir, + +// GBA [7] PHI# +// GBA [6] WR# +// GBA [5] RD# +// GBA [4] CS1#/CS# +// [3:0] unwired +inout wire [7:4] cart_tran_bank0, +output wire cart_tran_bank0_dir, + +// GBA CS2#/RES# +inout wire cart_tran_pin30, +output wire cart_tran_pin30_dir, +// when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit +// the goal is that when unconfigured, the FPGA weak pullups won't interfere. +// thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators +// and general IO drive this pin. +output wire cart_pin30_pwroff_reset, + +// GBA IRQ/DRQ +inout wire cart_tran_pin31, +output wire cart_tran_pin31_dir, + +// infrared +// avoid driving the TX LED with DC or leaving it stuck on. pulsed usage is fine +input wire port_ir_rx, +output wire port_ir_tx, +output wire port_ir_rx_disable, + +// GBA link port +inout wire port_tran_si, +output wire port_tran_si_dir, +inout wire port_tran_so, +output wire port_tran_so_dir, +inout wire port_tran_sck, +output wire port_tran_sck_dir, +inout wire port_tran_sd, +output wire port_tran_sd_dir, + +/////////////////////////////////////////////////// +// video output to the scaler + +inout wire [11:0] scal_vid, +inout wire scal_clk, +inout wire scal_de, +inout wire scal_skip, +inout wire scal_vs, +inout wire scal_hs, + +output wire scal_audmclk, +input wire scal_audadc, +output wire scal_auddac, +output wire scal_audlrck, + +/////////////////////////////////////////////////// +// communication between main and scaler (aristotle) fpga. +// spi bus with aristotle as controller. + +inout wire bridge_spimosi, +inout wire bridge_spimiso, +inout wire bridge_spiclk, +input wire bridge_spiss, +inout wire bridge_1wire, + +/////////////////////////////////////////////////// +// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + +output wire [21:16] cram0_a, +inout wire [15:0] cram0_dq, +input wire cram0_wait, +output wire cram0_clk, +output wire cram0_adv_n, +output wire cram0_cre, +output wire cram0_ce0_n, +output wire cram0_ce1_n, +output wire cram0_oe_n, +output wire cram0_we_n, +output wire cram0_ub_n, +output wire cram0_lb_n, + +output wire [21:16] cram1_a, +inout wire [15:0] cram1_dq, +input wire cram1_wait, +output wire cram1_clk, +output wire cram1_adv_n, +output wire cram1_cre, +output wire cram1_ce0_n, +output wire cram1_ce1_n, +output wire cram1_oe_n, +output wire cram1_we_n, +output wire cram1_ub_n, +output wire cram1_lb_n, + +/////////////////////////////////////////////////// +// sdram, 512mbit x16 + +output wire [12:0] dram_a, +output wire [1:0] dram_ba, +inout wire [15:0] dram_dq, +output wire [1:0] dram_dqm, +output wire dram_clk, +output wire dram_cke, +output wire dram_ras_n, +output wire dram_cas_n, +output wire dram_we_n, + +/////////////////////////////////////////////////// +// sram, 1mbit x16 + +output wire [16:0] sram_a, +inout wire [15:0] sram_dq, +output wire sram_oe_n, +output wire sram_we_n, +output wire sram_ub_n, +output wire sram_lb_n, + +/////////////////////////////////////////////////// +// vblank output to scaler + +input wire vblank, + +/////////////////////////////////////////////////// +// i/o to 6515D breakout usb uart + +output wire dbg_tx, +input wire dbg_rx, + +/////////////////////////////////////////////////// +// i/o pads near jtag connector user can solder to + +output wire user1, +input wire user2, + +/////////////////////////////////////////////////// +// powerup self test, do not use + +inout wire bist, +output wire vpll_feed, + +/////////////////////////////////////////////////// +// RFU internal i2c bus (DNU) + +inout wire aux_sda, +output wire aux_scl + +); + +assign bist = 1'bZ; + +// reset generation + + reg [24:0] count; + reg reset_n; + +initial begin + count <= 0; + reset_n <= 0; +end +always @(posedge clk_74a) begin + count <= count + 1'b1; + + if(count[15]) begin + // exit reset + reset_n <= 1; + end + +end + + + + +// convert 24-bit rgb data to 12-bit DDR for ARISTOTLE + + wire [23:0] video_rgb; + wire video_rgb_clock; + wire video_rgb_clock_90; + wire video_de; + wire video_skip; + wire video_vs; + wire video_hs; + +mf_ddio_bidir_12 isco ( + .oe ( 1'b1 ), + .datain_h ( video_rgb[23:12] ), + .datain_l ( video_rgb[11: 0] ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_12 ) +); + +wire [11:0] scal_ddio_12; +assign scal_vid = scal_ddio_12; + +mf_ddio_bidir_12 iscc ( + .oe ( 1'b1 ), + .datain_h ( {video_vs, video_hs, video_de, video_skip} ), + .datain_l ( {video_vs, video_hs, video_de, video_skip} ), + .outclock ( video_rgb_clock ), + .padio ( scal_ddio_ctrl ) +); + +wire [3:0] scal_ddio_ctrl; +assign scal_vs = scal_ddio_ctrl[3]; +assign scal_hs = scal_ddio_ctrl[2]; +assign scal_de = scal_ddio_ctrl[1]; +assign scal_skip = scal_ddio_ctrl[0]; + +mf_ddio_bidir_12 isclk( + .oe ( 1'b1 ), + .datain_h ( 1'b1 ), + .datain_l ( 1'b0 ), + .outclock ( video_rgb_clock_90 ), + .padio ( scal_clk ) +); + + + +// controller data (pad) controller. + wire [15:0] cont1_key; + wire [15:0] cont2_key; + wire [15:0] cont3_key; + wire [15:0] cont4_key; + wire [31:0] cont1_joy; + wire [31:0] cont2_joy; + wire [31:0] cont3_joy; + wire [31:0] cont4_joy; + wire [15:0] cont1_trig; + wire [15:0] cont2_trig; + wire [15:0] cont3_trig; + wire [15:0] cont4_trig; + +io_pad_controller ipm ( + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .pad_1wire ( bridge_1wire ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) +); + + +// virtual pmp bridge + wire bridge_endian_little; + wire [31:0] bridge_addr; + wire bridge_rd; + wire [31:0] bridge_rd_data; + wire bridge_wr; + wire [31:0] bridge_wr_data; + +io_bridge_peripheral ibs ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .endian_little ( bridge_endian_little ), + + .pmp_addr ( bridge_addr ), + .pmp_rd ( bridge_rd ), + .pmp_rd_data ( bridge_rd_data ), + .pmp_wr ( bridge_wr ), + .pmp_wr_data ( bridge_wr_data ), + + .phy_spimosi ( bridge_spimosi ), + .phy_spimiso ( bridge_spimiso ), + .phy_spiclk ( bridge_spiclk ), + .phy_spiss ( bridge_spiss ) + +); + + +/////////////////////////////////////////////////// +// instantiate the user core top-level + +core_top ic ( + + // physical connections + // + .clk_74a ( clk_74a ), + .clk_74b ( clk_74b ), + + .cart_tran_bank2 ( cart_tran_bank2 ), + .cart_tran_bank2_dir ( cart_tran_bank2_dir ), + .cart_tran_bank3 ( cart_tran_bank3 ), + .cart_tran_bank3_dir ( cart_tran_bank3_dir ), + .cart_tran_bank1 ( cart_tran_bank1 ), + .cart_tran_bank1_dir ( cart_tran_bank1_dir ), + .cart_tran_bank0 ( cart_tran_bank0 ), + .cart_tran_bank0_dir ( cart_tran_bank0_dir ), + .cart_tran_pin30 ( cart_tran_pin30 ), + .cart_tran_pin30_dir ( cart_tran_pin30_dir ), + .cart_pin30_pwroff_reset ( cart_pin30_pwroff_reset ), + .cart_tran_pin31 ( cart_tran_pin31 ), + .cart_tran_pin31_dir ( cart_tran_pin31_dir ), + + .port_ir_rx ( port_ir_rx ), + .port_ir_tx ( port_ir_tx ), + .port_ir_rx_disable ( port_ir_rx_disable ), + + .port_tran_si ( port_tran_si ), + .port_tran_si_dir ( port_tran_si_dir ), + .port_tran_so ( port_tran_so ), + .port_tran_so_dir ( port_tran_so_dir ), + .port_tran_sck ( port_tran_sck ), + .port_tran_sck_dir ( port_tran_sck_dir ), + .port_tran_sd ( port_tran_sd ), + .port_tran_sd_dir ( port_tran_sd_dir ), + + .cram0_a ( cram0_a ), + .cram0_dq ( cram0_dq ), + .cram0_wait ( cram0_wait ), + .cram0_clk ( cram0_clk ), + .cram0_adv_n ( cram0_adv_n ), + .cram0_cre ( cram0_cre ), + .cram0_ce0_n ( cram0_ce0_n ), + .cram0_ce1_n ( cram0_ce1_n ), + .cram0_oe_n ( cram0_oe_n ), + .cram0_we_n ( cram0_we_n ), + .cram0_ub_n ( cram0_ub_n ), + .cram0_lb_n ( cram0_lb_n ), + .cram1_a ( cram1_a ), + .cram1_dq ( cram1_dq ), + .cram1_wait ( cram1_wait ), + .cram1_clk ( cram1_clk ), + .cram1_adv_n ( cram1_adv_n ), + .cram1_cre ( cram1_cre ), + .cram1_ce0_n ( cram1_ce0_n ), + .cram1_ce1_n ( cram1_ce1_n ), + .cram1_oe_n ( cram1_oe_n ), + .cram1_we_n ( cram1_we_n ), + .cram1_ub_n ( cram1_ub_n ), + .cram1_lb_n ( cram1_lb_n ), + + .dram_a ( dram_a ), + .dram_ba ( dram_ba ), + .dram_dq ( dram_dq ), + .dram_dqm ( dram_dqm ), + .dram_clk ( dram_clk ), + .dram_cke ( dram_cke ), + .dram_ras_n ( dram_ras_n ), + .dram_cas_n ( dram_cas_n ), + .dram_we_n ( dram_we_n ), + + .sram_a ( sram_a ), + .sram_dq ( sram_dq ), + .sram_oe_n ( sram_oe_n ), + .sram_we_n ( sram_we_n ), + .sram_ub_n ( sram_ub_n ), + .sram_lb_n ( sram_lb_n ), + + .vblank ( vblank ), + .vpll_feed ( vpll_feed ), + + .dbg_tx ( dbg_tx ), + .dbg_rx ( dbg_rx ), + .user1 ( user1 ), + .user2 ( user2 ), + + .aux_sda ( aux_sda ), + .aux_scl ( aux_scl ), + + + // logical connections with user core + // + .video_rgb ( video_rgb ), + .video_rgb_clock ( video_rgb_clock ), + .video_rgb_clock_90 ( video_rgb_clock_90 ), + .video_de ( video_de ), + .video_skip ( video_skip ), + .video_vs ( video_vs ), + .video_hs ( video_hs ), + + .audio_mclk ( scal_audmclk ), + .audio_adc ( scal_audadc ), + .audio_dac ( scal_auddac ), + .audio_lrck ( scal_audlrck ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .cont1_key ( cont1_key ), + .cont2_key ( cont2_key ), + .cont3_key ( cont3_key ), + .cont4_key ( cont4_key ), + .cont1_joy ( cont1_joy ), + .cont2_joy ( cont2_joy ), + .cont3_joy ( cont3_joy ), + .cont4_joy ( cont4_joy ), + .cont1_trig ( cont1_trig ), + .cont2_trig ( cont2_trig ), + .cont3_trig ( cont3_trig ), + .cont4_trig ( cont4_trig ) + +); + +endmodule + diff --git a/platform/pocket/build_cdf.tcl b/platform/pocket/build_cdf.tcl new file mode 100644 index 0000000..ec99b5d --- /dev/null +++ b/platform/pocket/build_cdf.tcl @@ -0,0 +1,48 @@ +# ============================================================================== +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: SOURCE +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +# ============================================================================== +# @file: build_cd.h +# @brief: Generate a JTAG Chain Description File. +# Create a .cdf file to be used with Quartus Prime Programmer +# ============================================================================== +proc createChainDescriptionFile {revision device outpath project_name} { + set outputFileName "$project_name.cdf" + set outputFile [open $outputFileName "w"] + + puts $outputFile "JedecChain;" + puts $outputFile " FileRevision(JESD32A);" + puts $outputFile " DefaultMfr(6E);" + puts $outputFile "" + puts $outputFile " P ActionCode(Cfg)" + puts $outputFile " Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));" + puts $outputFile "ChainEnd;" + puts $outputFile "" + puts $outputFile "AlteraBegin;" + puts $outputFile " ChainType(JTAG);" + puts $outputFile "AlteraEnd;" +} + +set project_name [lindex $quartus(args) 1] +set revision [lindex $quartus(args) 2] + +if {[project_exists $project_name]} { + if {[string equal "" $revision]} { + project_open $project_name -revision [get_current_revision $project_name] + } else { + project_open $project_name -revision $revision + } +} else { + post_message -type error "Project $project_name does not exist" + exit +} + +set device [get_global_assignment -name DEVICE] +set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY] + +if [is_project_open] { + project_close +} + +createChainDescriptionFile $revision $device $outpath $project_name diff --git a/platform/pocket/build_id_gen.tcl b/platform/pocket/build_id_gen.tcl new file mode 100644 index 0000000..91b0627 --- /dev/null +++ b/platform/pocket/build_id_gen.tcl @@ -0,0 +1,171 @@ +# ================================================================================ +# (c) 2011 Altera Corporation. All rights reserved. +# Altera products are protected under numerous U.S. and foreign patents, maskwork +# rights, copyrights and other intellectual property laws. +# +# This reference design file, and your use thereof, is subject to and governed +# by the terms and conditions of the applicable Altera Reference Design License +# Agreement (either as signed by you, agreed by you upon download or as a +# "click-through" agreement upon installation andor found at www.altera.com). +# By using this reference design file, you indicate your acceptance of such terms +# and conditions between you and Altera Corporation. In the event that you do +# not agree with such terms and conditions, you may not use the reference design +# file and please promptly destroy any copies you have made. +# +# This reference design file is being provided on an "as-is" basis and as an +# accommodation and therefore all warranties, representations or guarantees of +# any kind (whether express, implied or statutory) including, without limitation, +# warranties of merchantability, non-infringement, or fitness for a particular +# purpose, are specifically disclaimed. By making this reference design file +# available, Altera expressly does not recommend, suggest or require that this +# reference design file be used in combination with any other product not +# provided by Altera. +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, physical address, and host name +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# The format for each value is as follows: +# Date - 32-bit decimal number of the format mmddyyyy +# Time - 32-bit decimal number of the format hhmmss +# Phyiscal Address - 48-bit hexadecimal number +# Host name - 120-bit hexadecimal number with pairs of digits equal to the +# hexadecimal code for the first 15 ASCII characters of the host +# name. For added clarity, host names that have fewer than 30 +# hexadecimal digits (15 characters) are padded on the left with +# zeros. +# +# Usage: +# +# To manually execute this script, source this file using the following Tcl commands: +# source build_id_verilog.tcl +# +# To have this script automatically execute each time your project is built, use the +# following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): +# set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id_verilog.tcl +# +# Comment out the last line to prevent the process from automatically executing when +# the file is sourced. The process can then be executed with the following command: +# generateBuildID_Verilog +# +# +# For more information, see "build_identification.pdf" +# +# ================================================================================ +# +# 2021-01-21 Analogue +# +# Only care about generating build date/time, so the rest was removed. +# The original can be downloaded from the Intel resource page +# + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "../platform/pocket/build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "// Build ID Verilog Module" + puts $outputFile "//" + puts $outputFile "// Note - these are stored as binary coded decimal" + puts $outputFile "// Date: $buildDate" + puts $outputFile "// Time: $buildTime" + puts $outputFile "" + puts $outputFile "module build_id" + puts $outputFile "(" + puts $outputFile " output \[31:0\] build_date," + puts $outputFile " output \[31:0\] build_time" + puts $outputFile ");" + puts $outputFile "" + puts $outputFile " assign build_date = 32'h$buildDate;" + puts $outputFile " assign build_time = 32'h$buildTime;" + puts $outputFile "" + puts $outputFile "endmodule" + close $outputFile + + + + # Send confirmation message to the Messages window + #post_message "APF core build date/time generated: [pwd]/$outputFileName" + #post_message "Date: $buildDate" + #post_message "Time: $buildTime" +} + + +proc generateBuildID_MIF {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %Y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + set buildUnique [expr {int(rand()*(4294967295))}] + + set buildDateNoLeadingZeros [string trimleft $buildDate "0"] + set buildTimeNoLeadingZeros [string trimleft $buildTime "0"] + set buildDate4Byte [format "%08d" $buildDateNoLeadingZeros] + set buildTime4Byte [format "%08d" $buildTimeNoLeadingZeros] + set buildUnique4Byte [format "%08x" $buildUnique] + + #set buildDate4Byte \ + [concat [string range $buildDate 0 1] \ + [string range $buildDate 2 3] \ + [string range $buildDate 4 5] \ + [string range $buildDate 6 7] ] + + + set buildDateNumBytes 4 + set buildTimeNumBytes 4 + + # Calculate depth of the memory (8-bit) words + set memoryDepth [expr $buildDateNumBytes + $buildTimeNumBytes] + + # Create a Memory Initialization File for output + set outputFileName "../platform/pocket/build_id.mif" + set outputFile [open $outputFileName "w"] + + # Output the MIF header (see: http://quartushelp.altera.com/current/mergedProjects/reference/glossary/def_mif.htm) + puts $outputFile "-- Build ID Memory Initialization File" + puts $outputFile "--" + puts $outputFile "" + puts $outputFile "DEPTH = 256;" + puts $outputFile "WIDTH = 32;" + puts $outputFile "ADDRESS_RADIX = HEX;" + puts $outputFile "DATA_RADIX = HEX;" + puts $outputFile "" + puts $outputFile "CONTENT" + puts $outputFile "BEGIN" + puts $outputFile "" + puts $outputFile " 0E0 : $buildDate4Byte;" + puts $outputFile " 0E1 : $buildTime4Byte;" + puts $outputFile " 0E2 : $buildUnique4Byte;" + puts $outputFile "" + puts $outputFile "END;" + + # Close file to complete write + close $outputFile + + # Send confirmation message to the Messages window + post_message "APF core build date/time generated: [pwd]/$outputFileName" +} + +generateBuildID_MIF + +# 2021-01-21 Analogue +# +# There are some circumstances where you want all parts of a FPGA flow to be deterministic, especially +# when trying to hash out timing issues. +# You should comment this line out and temporarily bypass buildid generation so that synthesis/par +# have consistent working input. MIF bram contents like above won't affect the random seed or trigger +# recompilation. +# Don't forget to re-enable before you release. +# +# generateBuildID_Verilog diff --git a/platform/pocket/common.v b/platform/pocket/common.v new file mode 100644 index 0000000..6c8c0f2 --- /dev/null +++ b/platform/pocket/common.v @@ -0,0 +1,152 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// 2-stage synchronizer +// +module synch_2 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_2) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_2) : 1'b0; +always @(posedge clk) + {stage_2, o, stage_1} <= {o, stage_1, i}; + +endmodule + + +// +// 3-stage synchronizer +// +module synch_3 #(parameter WIDTH = 1) ( + input wire [WIDTH-1:0] i, // input signal + output reg [WIDTH-1:0] o, // synchronized output + input wire clk, // clock to synchronize on + output wire rise, // one-cycle rising edge pulse + output wire fall // one-cycle falling edge pulse +); + +reg [WIDTH-1:0] stage_1; +reg [WIDTH-1:0] stage_2; +reg [WIDTH-1:0] stage_3; + +assign rise = (WIDTH == 1) ? (o & ~stage_3) : 1'b0; +assign fall = (WIDTH == 1) ? (~o & stage_3) : 1'b0; +always @(posedge clk) + {stage_3, o, stage_2, stage_1} <= {o, stage_2, stage_1, i}; + +endmodule + + +module bram_block_dp #( + parameter DATA = 32, + parameter ADDR = 7 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [(2**ADDR)-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule + + +module bram_block_dp_nonstd #( + parameter DATA = 32, + parameter ADDR = 7, + parameter DEPTH = 128 +) ( + input wire a_clk, + input wire a_wr, + input wire [ADDR-1:0] a_addr, + input wire [DATA-1:0] a_din, + output reg [DATA-1:0] a_dout, + + input wire b_clk, + input wire b_wr, + input wire [ADDR-1:0] b_addr, + input wire [DATA-1:0] b_din, + output reg [DATA-1:0] b_dout +); + +reg [DATA-1:0] mem [DEPTH-1:0]; + +always @(posedge a_clk) begin + if(a_wr) begin + a_dout <= a_din; + mem[a_addr] <= a_din; + end else + a_dout <= mem[a_addr]; +end + +always @(posedge b_clk) begin + if(b_wr) begin + b_dout <= b_din; + mem[b_addr] <= b_din; + end else + b_dout <= mem[b_addr]; +end + +endmodule diff --git a/platform/pocket/io_bridge_peripheral.v b/platform/pocket/io_bridge_peripheral.v new file mode 100644 index 0000000..7e0467c --- /dev/null +++ b/platform/pocket/io_bridge_peripheral.v @@ -0,0 +1,331 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// bridge peripheral for socrates PMP bridge to heraclitus+aristotle +// 2020-2022 Analogue +// +// please note that while writes are immediate, +// reads are buffered by 1 word. this is necessary to maintain +// data throughput while reading from slower data sources like +// sdram. +// reads should always return the current bus value, and kickstart +// into the next read immediately. this way, you have the entire +// next word time to retrieve the data, instead of just a few +// cycles. +// +// the worst-case read/write timing is every 88 cycles @ 74.25mhz +// which is about 1180ns. + +module io_bridge_peripheral ( + +input wire clk, +input wire reset_n, + +input wire endian_little, + +output reg [31:0] pmp_addr, +output reg pmp_addr_valid, +output reg pmp_rd, +input wire [31:0] pmp_rd_data, +output reg pmp_wr, +output reg [31:0] pmp_wr_data, + +inout reg phy_spimosi, +inout reg phy_spimiso, +inout reg phy_spiclk, +input wire phy_spiss + +); + +// +// clock domain: clk (74.25mhz) rising edge +// + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire endian_little_s; +synch_3 s01(endian_little, endian_little_s, clk); + + wire phy_spiss_s, phy_spiss_r, phy_spiss_f; +synch_3 s02(phy_spiss, phy_spiss_s, clk, phy_spiss_r, phy_spiss_f); + + + reg [4:0] state; + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_READ_0 = 'd2; + localparam ST_READ_1 = 'd3; + localparam ST_READ_2 = 'd4; + localparam ST_READ_3 = 'd5; + localparam ST_WRITE_0 = 'd6; + localparam ST_WRITE_1 = 'd7; + localparam ST_WRITE_2 = 'd8; + localparam ST_ADDR_0 = 'd9; + + reg [1:0] addr_cnt; + reg [1:0] data_cnt; + reg [6:0] read_cnt; + + // synchronize rd byte flag's rising edge into clk + wire rx_byte_done_s, rx_byte_done_r; +synch_3 s03(rx_byte_done, rx_byte_done_s, clk, rx_byte_done_r); + + + reg [4:0] spis; + localparam ST_SIDLE = 'd1; + localparam ST_SEND_N = 'd6; + localparam ST_SEND_0 = 'd2; + localparam ST_SEND_1 = 'd3; + localparam ST_SEND_2 = 'd4; + localparam ST_SEND_3 = 'd5; + reg spis_tx; + reg [31:0] spis_word_tx; + reg [31:0] spis_word; + reg [4:0] spis_count; + reg spis_done; + + reg rx_byte_done_r_1, rx_byte_done_r_2; + reg [7:0] rx_byte_1, rx_byte_2; + + // handle reversing endianness on both ports + reg [31:0] pmp_wr_data_latch; + reg [31:0] pmp_rd_data_e; // asynchronous + reg [31:0] pmp_rd_data_buf; // buffer the last word for immediate response +always @(*) begin + pmp_wr_data <= endian_little_s ? { pmp_wr_data_latch[7:0], + pmp_wr_data_latch[15:8], + pmp_wr_data_latch[23:16], + pmp_wr_data_latch[31:24] + } : pmp_wr_data_latch; + + pmp_rd_data_e <= endian_little_s ? {pmp_rd_data[7:0], + pmp_rd_data[15:8], + pmp_rd_data[23:16], + pmp_rd_data[31:24] + } : pmp_rd_data; +end + +always @(posedge clk) begin + + rx_byte_2 <= rx_byte_1; + rx_byte_1 <= rx_byte; + + rx_byte_done_r_1 <= rx_byte_done_r; + rx_byte_done_r_2 <= rx_byte_done_r_1; + + case(state) + ST_RESET: begin + addr_cnt <= 0; + data_cnt <= 0; + pmp_wr <= 0; + pmp_rd <= 0; + pmp_addr_valid <= 0; + spis_tx <= 0; + + state <= ST_ADDR_0; + end + ST_ADDR_0: begin + // transaction has started + + if(rx_byte_done_r_2) begin + case(addr_cnt) + 0: pmp_addr[31:24] <= rx_byte_2; + 1: pmp_addr[23:16] <= rx_byte_2; + 2: pmp_addr[15: 8] <= rx_byte_2; + 3: begin + pmp_addr[ 7: 0] <= {rx_byte_2[7:2], 2'b00}; + // address is latched + if( rx_byte_2[0] ) begin + data_cnt <= 0; + state <= ST_WRITE_0; + end else begin + data_cnt <= 0; + read_cnt <= 0; + state <= ST_READ_0; + end + end + endcase + + addr_cnt <= addr_cnt + 1'b1; + end + end + ST_WRITE_0: begin + // give notice, address has become valid + pmp_addr_valid <= 1; + + if(rx_byte_done_r_2) begin + case(data_cnt) + 0: pmp_wr_data_latch[31:24] <= rx_byte_2; + 1: pmp_wr_data_latch[23:16] <= rx_byte_2; + 2: pmp_wr_data_latch[15: 8] <= rx_byte_2; + 3: begin + pmp_wr_data_latch[ 7: 0] <= rx_byte_2; + state <= ST_WRITE_1; + end + endcase + data_cnt <= data_cnt + 1'b1; + end + end + ST_WRITE_1: begin + pmp_wr <= 1; + state <= ST_WRITE_2; + end + ST_WRITE_2: begin + // exited upon new transaction + pmp_wr <= 0; + end + ST_READ_0: begin + pmp_addr_valid <= 1; + + // delay a few cycles + read_cnt <= read_cnt + 1'b1; + if(read_cnt == 4-1) begin + // load the buffer with the current data + // and give the current buffer contents to bridge + spis_word_tx <= pmp_rd_data_e; + spis_tx <= 1; + + state <= ST_READ_1; + end + end + ST_READ_1: begin + pmp_rd <= 1; + state <= ST_READ_2; + end + ST_READ_2: begin + pmp_rd <= 0; + if(spis_done) begin + spis_tx <= 0; + state <= ST_READ_3; + end + end + ST_READ_3: begin + // exited upon new transaction + end + endcase + + + + + // + // word transmit + // + spis_done <= 0; + case(spis) + ST_SIDLE: begin + spis_count <= 0; + + phy_spiclk <= 1'bZ; + phy_spimosi <= 1'bZ; + phy_spimiso <= 1'bZ; + + if(spis_tx) begin + spis_word <= spis_word_tx; + spis <= ST_SEND_N; + end + end + // drive high first + ST_SEND_N: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_0; + end + // tx, shift out bits + ST_SEND_0: begin + phy_spiclk <= 0; + spis <= ST_SEND_1; + phy_spimosi <= spis_word[31]; + phy_spimiso <= spis_word[30]; + spis_word <= {spis_word[29:0], 2'b00}; + end + ST_SEND_1: begin + phy_spiclk <= 1; + spis <= ST_SEND_0; + spis_count <= spis_count + 1'b1; + if(spis_count == 15) spis <= ST_SEND_2; + end + ST_SEND_2: begin + phy_spiclk <= 1'b1; + phy_spimosi <= 1'b1; + phy_spimiso <= 1'b1; + spis <= ST_SEND_3; + spis_done <= 1; + end + ST_SEND_3: begin + spis <= ST_SIDLE; + end + endcase + + if(phy_spiss_s) begin + // select is high, go back to reset + state <= ST_RESET; + spis <= ST_SIDLE; + end + +end + + +// +// clock domain: phy_spiclk rising edge +// + reg [1:0] rx_latch_idx; + reg [7:0] rx_dat; + reg [7:0] rx_byte; // latched by clk, but upon a synchronized trigger + reg rx_byte_done; + +always @(posedge phy_spiclk or posedge phy_spiss) begin + + if(phy_spiss) begin + // reset + rx_byte_done <= 0; + rx_latch_idx <= 0; + + end else begin + // spiclk rising edge, latch data + rx_byte_done <= 0; + + case(rx_latch_idx) + 0: begin rx_dat[7:6] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 1; end + 1: begin rx_dat[5:4] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 2; end + 2: begin rx_dat[3:2] <= {phy_spimosi, phy_spimiso}; rx_latch_idx <= 3; end + 3: begin + // last bit of the byte + rx_byte <= {rx_dat[7:2], phy_spimosi, phy_spimiso}; + rx_latch_idx <= 0; + rx_byte_done <= 1; + end + endcase + end +end + +endmodule diff --git a/platform/pocket/io_pad_controller.v b/platform/pocket/io_pad_controller.v new file mode 100644 index 0000000..26e4c2e --- /dev/null +++ b/platform/pocket/io_pad_controller.v @@ -0,0 +1,324 @@ +// Software License Agreement + +// The software supplied herewith by Analogue Enterprises Limited (the "Company”), +// the Analogue Pocket Framework (“APF”), is provided and licensed to you, the +// Company's customer, solely for use in designing, testing and creating +// applications for use with Company's Products or Services. The software is +// owned by the Company and/or its licensors, and is protected under applicable +// laws, including, but not limited to, U.S. copyright law. All rights are +// reserved. By using the APF code you are agreeing to the terms of the End User +// License Agreement (“EULA”) located at [https://www.analogue.link/pocket-eula] +// and incorporated herein by reference. + +// THE SOFTWARE IS PROVIDED "AS-IS" AND WE EXPRESSLY DISCLAIM ANY IMPLIED +// WARRANTIES TO THE FULLEST EXTENT PROVIDED BY LAW, INCLUDING BUT NOT LIMITED TO, +// ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE OR +// NON-INFRINGEMENT. TO THE EXTENT APPLICABLE LAWS PROHIBIT TERMS OF USE FROM +// DISCLAIMING ANY IMPLIED WARRANTY, SUCH IMPLIED WARRANTY SHALL BE LIMITED TO THE +// MINIMUM WARRANTY PERIOD REQUIRED BY LAW, AND IF NO SUCH PERIOD IS REQUIRED, +// THEN THIRTY (30) DAYS FROM FIRST USE OF THE SOFTWARE. WE CANNOT GUARANTEE AND +// DO NOT PROMISE ANY SPECIFIC RESULTS FROM USE OF THE SOFTWARE. WITHOUT LIMITING +// THE FOREGOING, WE DO NOT WARRANT THAT THE SOFTWARE WILL BE UNINTERRUPTED OR +// ERROR-FREE. IN NO EVENT WILL WE BE LIABLE TO YOU OR ANY OTHER PERSON FOR ANY +// INDIRECT, CONSEQUENTIAL, EXEMPLARY, INCIDENTAL, SPECIAL OR PUNITIVE DAMAGES, +// INCLUDING BUT NOT LIMITED TO, LOST PROFITS ARISING OUT OF YOUR USE, OR +// INABILITY TO USE, THE SOFTWARE, EVEN IF WE HAVE BEEN ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGES. UNDER NO CIRCUMSTANCES SHALL OUR LIABILITY TO YOU FOR ANY +// CLAIM OR CAUSE OF ACTION WHATSOEVER, AND REGARDLESS OF THE FORM OF THE ACTION, +// WHETHER ARISING IN CONTRACT, TORT OR OTHERWISE, EXCEED THE AMOUNT PAID BY YOU +// TO US, IF ANY, DURING THE 90 DAY PERIOD IMMEDIATELY PRECEDING THE DATE ON WHICH +// YOU FIRST ASSERT ANY SUCH CLAIM. THE FOREGOING LIMITATIONS SHALL APPLY TO THE +// FULLEST EXTENT PERMITTED BY APPLICABLE LAW. +// +// pad controller +// 2020-08-10 Analogue - started +// + +module io_pad_controller ( + +input wire clk, +input wire reset_n, + +inout reg pad_1wire, + +output reg [15:0] cont1_key, +output reg [15:0] cont2_key, +output reg [15:0] cont3_key, +output reg [15:0] cont4_key, +output reg [31:0] cont1_joy, +output reg [31:0] cont2_joy, +output reg [31:0] cont3_joy, +output reg [31:0] cont4_joy, +output reg [15:0] cont1_trig, +output reg [15:0] cont2_trig, +output reg [15:0] cont3_trig, +output reg [15:0] cont4_trig, + +output reg rx_timed_out +); + + wire reset_n_s; +synch_3 s00(reset_n, reset_n_s, clk); + + wire pad_1wire_s, pad_1wire_r, pad_1wire_f; +synch_3 s01(pad_1wire, pad_1wire_s, clk, pad_1wire_r, pad_1wire_f); + + +// +// protocol fsm +// + + reg [20:0] rx_timeout; // ~28ms + + reg [15:0] auto_poll_cnt; // 882us + reg auto_poll_queue; + + reg [18:0] heartbeat_cnt; // 7ms + reg heartbeat_queue; + + + localparam ST_RESET = 'd0; + localparam ST_IDLE = 'd1; + localparam ST_RX_BUTTON_1 = 'd2; + localparam ST_RX_BUTTON_2 = 'd3; + localparam ST_TX_SCALER = 'd4; + localparam ST_END_TX = 'd5; + + reg [3:0] state; + reg [3:0] cnt; + +always @(posedge clk) begin + tx_word_start <= 0; + + auto_poll_cnt <= auto_poll_cnt + 1'b1; + heartbeat_cnt <= heartbeat_cnt + 1'b1; + + // increment rx timeout, override and reset when idle below + rx_timeout <= rx_timeout + 1'b1; + + case(state) + ST_RESET: begin + reset_tr_n <= 0; + rx_timed_out <= 0; + + if(&rx_timeout[19:0]) begin + state <= ST_IDLE; + end + end + ST_IDLE: begin + // idle state + reset_tr_n <= 1; + rx_timeout <= 0; + cnt <= 0; + if(auto_poll_queue) begin + auto_poll_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4A10000C; + + state <= ST_RX_BUTTON_1; + end else if(heartbeat_queue) begin + heartbeat_queue <= 0; + + tx_word_start <= 1; + tx_word <= 32'h4AFE0000; + + state <= ST_END_TX; + end + end + // receive button words + ST_RX_BUTTON_1: begin + if(tx_word_done) begin + state <= ST_RX_BUTTON_2; + end + end + ST_RX_BUTTON_2: begin + if(rx_word_done) begin + cnt <= cnt + 1'b1; + case(cnt) + 0: cont1_key <= rx_word; + 1: cont1_joy <= rx_word; + 2: cont1_trig <= rx_word; + + 3: cont2_key <= rx_word; + 4: cont2_joy <= rx_word; + 5: cont2_trig <= rx_word; + + 6: cont3_key <= rx_word; + 7: cont3_joy <= rx_word; + 8: cont3_trig <= rx_word; + + 9: cont4_key <= rx_word; + 10: cont4_joy <= rx_word; + 11: begin + cont4_trig <= rx_word; + state <= ST_IDLE; + end + endcase + end + end + // do nothing + ST_END_TX: begin + // done sending, idle again + if(tx_word_done) begin + state <= ST_IDLE; + end + end + endcase + + + if(&auto_poll_cnt) begin + auto_poll_queue <= 1; + end + if(&heartbeat_cnt) begin + heartbeat_queue <= 1; + end + + if(&rx_timeout) begin + // reset protocol FSM which will also reset t/r engine + rx_timed_out <= 1; + rx_timeout <= 0; + state <= ST_RESET; + end + + if(~reset_n_s) begin + state <= ST_RESET; + end +end + + + + + +// +// word receive/transmit engine +// + reg reset_tr_n; + localparam BITLEN = 60; + + reg rx_word_done; + reg [31:0] rx_word_shift; + reg [31:0] rx_word; + + reg tx_word_start, tx_word_start_1; + reg tx_word_done; + reg [31:0] tx_word; + reg [31:0] tx_word_shift; + + reg [7:0] tr_cnt; + reg [5:0] tr_bit; + + localparam TR_IDLE = 'd1; + localparam TR_TX_START = 'd2; + localparam TR_TX_CONTINUE = 'd3; + localparam TR_TX_DONE = 'd4; + localparam TR_RX_START = 'd5; + localparam TR_RX_WAITEDGE = 'd6; + localparam TR_RX_DONE = 'd7; + + reg [3:0] tr_state; + +always @(posedge clk) begin + + rx_word_done <= 0; + tx_word_done <= 0; + + tx_word_start_1 <= tx_word_start; + + case(tr_state) + TR_IDLE: begin + tr_bit <= 0; + tr_cnt <= 0; + + pad_1wire <= 1'bZ; + + if(tx_word_start & ~tx_word_start_1) begin + // transmit word + tx_word_shift <= tx_word; + tr_state <= TR_TX_START; + end + + if(pad_1wire_f) begin + // receive word + tr_state <= TR_RX_START; + end + end + + // transmit 32bit + TR_TX_START: begin + // insert delay + tr_cnt <= tr_cnt + 1'b1; + if(&tr_cnt) begin + // drive from tristate(high) to explicitly high to prevent glitching + pad_1wire <= 1'b1; + tr_state <= TR_TX_CONTINUE; + end + end + TR_TX_CONTINUE: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + 0: begin + pad_1wire <= 1'b0; + end + (BITLEN/3): begin + pad_1wire <= tx_word_shift[31]; + end + (BITLEN*2/3): begin + pad_1wire <= 1'b1; + end + (BITLEN-1): begin + tr_cnt <= 0; + tx_word_shift <= {tx_word_shift[30:0], 1'b1}; + + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + tr_state <= TR_TX_DONE; + end + end + endcase + end + TR_TX_DONE: begin + tx_word_done <= 1; + tr_state <= TR_IDLE; + end + + // receive 32bit + TR_RX_START: begin + tr_cnt <= tr_cnt + 1'b1; + case(tr_cnt) + (BITLEN/2-4): begin + rx_word_shift <= {rx_word_shift[30:0], pad_1wire_s}; + end + (BITLEN*5/6): begin + tr_cnt <= 0; + + // wait for next falling edge + tr_state <= TR_RX_WAITEDGE; + tr_bit <= tr_bit + 1'b1; + if(tr_bit == 31) begin + // if this is bit32, don't wait and finish + tr_state <= TR_RX_DONE; + end + end + endcase + end + TR_RX_WAITEDGE: begin + if(pad_1wire_f) begin + tr_state <= TR_RX_START; + end + end + TR_RX_DONE: begin + rx_word <= rx_word_shift; + rx_word_done <= 1; + tr_state <= TR_IDLE; + end + + default: begin + tr_state <= TR_IDLE; + end + endcase + + if(~reset_n_s | ~reset_tr_n) tr_state <= TR_IDLE; +end + +endmodule diff --git a/platform/pocket/mf_datatable.qip b/platform/pocket/mf_datatable.qip new file mode 100644 index 0000000..9c3a0f7 --- /dev/null +++ b/platform/pocket/mf_datatable.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_datatable.v"] diff --git a/platform/pocket/mf_datatable.v b/platform/pocket/mf_datatable.v new file mode 100644 index 0000000..33c26be --- /dev/null +++ b/platform/pocket/mf_datatable.v @@ -0,0 +1,247 @@ +// megafunction wizard: %RAM: 2-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: mf_datatable.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_datatable ( + address_a, + address_b, + clock_a, + clock_b, + data_a, + data_b, + wren_a, + wren_b, + q_a, + q_b); + + input [7:0] address_a; + input [7:0] address_b; + input clock_a; + input clock_b; + input [31:0] data_a; + input [31:0] data_b; + input wren_a; + input wren_b; + output [31:0] q_a; + output [31:0] q_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock_a; + tri0 wren_a; + tri0 wren_b; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [31:0] sub_wire0; + wire [31:0] sub_wire1; + wire [31:0] q_a = sub_wire0[31:0]; + wire [31:0] q_b = sub_wire1[31:0]; + + altsyncram altsyncram_component ( + .address_a (address_a), + .address_b (address_b), + .clock0 (clock_a), + .clock1 (clock_b), + .data_a (data_a), + .data_b (data_b), + .wren_a (wren_a), + .wren_b (wren_b), + .q_a (sub_wire0), + .q_b (sub_wire1), + .aclr0 (1'b0), + .aclr1 (1'b0), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .eccstatus (), + .rden_a (1'b1), + .rden_b (1'b1)); + defparam + altsyncram_component.address_reg_b = "CLOCK1", + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_input_b = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.clock_enable_output_b = "BYPASS", + altsyncram_component.indata_reg_b = "CLOCK1", + altsyncram_component.init_file = "./apf/build_id.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.numwords_b = 256, + altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_aclr_b = "NONE", + altsyncram_component.outdata_reg_a = "CLOCK0", + altsyncram_component.outdata_reg_b = "CLOCK1", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.widthad_b = 8, + altsyncram_component.width_a = 32, + altsyncram_component.width_b = 32, + altsyncram_component.width_byteena_a = 1, + altsyncram_component.width_byteena_b = 1, + altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1"; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +// Retrieval info: PRIVATE: CLRdata NUMERIC "0" +// Retrieval info: PRIVATE: CLRq NUMERIC "0" +// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRrren NUMERIC "0" +// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +// Retrieval info: PRIVATE: CLRwren NUMERIC "0" +// Retrieval info: PRIVATE: Clock NUMERIC "5" +// Retrieval info: PRIVATE: Clock_A NUMERIC "0" +// Retrieval info: PRIVATE: Clock_B NUMERIC "0" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" +// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./apf/build_id.mif" +// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +// Retrieval info: PRIVATE: REGdata NUMERIC "1" +// Retrieval info: PRIVATE: REGq NUMERIC "1" +// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +// Retrieval info: PRIVATE: REGrren NUMERIC "0" +// Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +// Retrieval info: PRIVATE: REGwren NUMERIC "1" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +// Retrieval info: PRIVATE: VarWidth NUMERIC "0" +// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" +// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" +// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +// Retrieval info: PRIVATE: enable NUMERIC "0" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: INIT_FILE STRING "./apf/build_id.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]" +// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]" +// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" +// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" +// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" +// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" +// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 +// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 +// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_datatable_bb.v FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/platform/pocket/mf_ddio_bidir_12.qip b/platform/pocket/mf_ddio_bidir_12.qip new file mode 100644 index 0000000..40c4266 --- /dev/null +++ b/platform/pocket/mf_ddio_bidir_12.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mf_ddio_bidir_12.ppf"] diff --git a/platform/pocket/mf_ddio_bidir_12.v b/platform/pocket/mf_ddio_bidir_12.v new file mode 100644 index 0000000..6bac1ab --- /dev/null +++ b/platform/pocket/mf_ddio_bidir_12.v @@ -0,0 +1,134 @@ +// megafunction wizard: %ALTDDIO_BIDIR% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_BIDIR + +// ============================================================ +// File Name: mf_ddio_bidir_12.v +// Megafunction Name(s): +// ALTDDIO_BIDIR +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mf_ddio_bidir_12 ( + datain_h, + datain_l, + inclock, + oe, + outclock, + dataout_h, + dataout_l, + padio); + + input [11:0] datain_h; + input [11:0] datain_l; + input inclock; + input oe; + input outclock; + output [11:0] dataout_h; + output [11:0] dataout_l; + inout [11:0] padio; + + wire [11:0] sub_wire0; + wire [11:0] sub_wire1; + wire [11:0] dataout_h = sub_wire0[11:0]; + wire [11:0] dataout_l = sub_wire1[11:0]; + + altddio_bidir ALTDDIO_BIDIR_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .inclock (inclock), + .oe (oe), + .outclock (outclock), + .padio (padio), + .dataout_h (sub_wire0), + .dataout_l (sub_wire1), + .aclr (1'b0), + .aset (1'b0), + .combout (), + .dqsundelayedout (), + .inclocken (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_BIDIR_component.extend_oe_disable = "OFF", + ALTDDIO_BIDIR_component.implement_input_in_lcell = "OFF", + ALTDDIO_BIDIR_component.intended_device_family = "Cyclone V", + ALTDDIO_BIDIR_component.invert_output = "OFF", + ALTDDIO_BIDIR_component.lpm_hint = "UNUSED", + ALTDDIO_BIDIR_component.lpm_type = "altddio_bidir", + ALTDDIO_BIDIR_component.oe_reg = "UNREGISTERED", + ALTDDIO_BIDIR_component.power_up_high = "OFF", + ALTDDIO_BIDIR_component.width = 12; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "12" +// Retrieval info: USED_PORT: datain_h 0 0 12 0 INPUT NODEFVAL "datain_h[11..0]" +// Retrieval info: CONNECT: @datain_h 0 0 12 0 datain_h 0 0 12 0 +// Retrieval info: USED_PORT: datain_l 0 0 12 0 INPUT NODEFVAL "datain_l[11..0]" +// Retrieval info: CONNECT: @datain_l 0 0 12 0 datain_l 0 0 12 0 +// Retrieval info: USED_PORT: dataout_h 0 0 12 0 OUTPUT NODEFVAL "dataout_h[11..0]" +// Retrieval info: CONNECT: dataout_h 0 0 12 0 @dataout_h 0 0 12 0 +// Retrieval info: USED_PORT: dataout_l 0 0 12 0 OUTPUT NODEFVAL "dataout_l[11..0]" +// Retrieval info: CONNECT: dataout_l 0 0 12 0 @dataout_l 0 0 12 0 +// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "inclock" +// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe" +// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: USED_PORT: padio 0 0 12 0 BIDIR NODEFVAL "padio[11..0]" +// Retrieval info: CONNECT: padio 0 0 12 0 @padio 0 0 12 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mf_ddio_bidir_12.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/platform/pocket/pocket.tcl b/platform/pocket/pocket.tcl new file mode 100644 index 0000000..ec49478 --- /dev/null +++ b/platform/pocket/pocket.tcl @@ -0,0 +1,714 @@ +# ============================================================================== +# SPDX-License-Identifier: CC0-1.0 +# SPDX-FileType: SOURCE +# SPDX-FileCopyrightText: (c) 2022, OpenGateware authors and contributors +# ============================================================================== +# +# Platform Global/Location/Instance Assignments +# +# ============================================================================== +# Hardware Information +# ============================================================================== +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CEBA4F23C8 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 + +# ============================================================================== +# Classic Timing Assignments +# ============================================================================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON + +# ============================================================================== +# Assembler Assignments +# ============================================================================== +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name GENERATE_RBF_FILE ON + +# ============================================================================== +# Power Estimation Assignments +# ============================================================================== +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" + +# ============================================================================== +# Signal Tap Assignments +# ============================================================================== +set_global_assignment -name ENABLE_SIGNALTAP ON + +# ============================================================================== +# Pin & Location Assignments +# ============================================================================== +set_location_assignment PIN_V15 -to clk_74a +set_location_assignment PIN_H16 -to clk_74b +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk_74a +set_instance_assignment -name IO_STANDARD "1.8 V" -to clk_74b + +# ============================================================================== +# SPI bus with Aristotle +# ============================================================================== +set_location_assignment PIN_T17 -to bridge_spiclk +set_location_assignment PIN_M21 -to bridge_spimiso +set_location_assignment PIN_M20 -to bridge_spimosi +set_location_assignment PIN_L19 -to bridge_1wire +set_location_assignment PIN_H14 -to bridge_spiss +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimiso +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spimosi +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_1wire +set_instance_assignment -name IO_STANDARD "1.8 V" -to bridge_spiss +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spiclk +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimiso +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_spimosi +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to bridge_1wire + +# ============================================================================== +# Cartridge interface +# ============================================================================== +set_location_assignment PIN_AA9 -to cart_tran_bank0[7] +set_location_assignment PIN_AB8 -to cart_tran_bank0[6] +set_location_assignment PIN_AA8 -to cart_tran_bank0[5] +set_location_assignment PIN_AB7 -to cart_tran_bank0[4] +set_location_assignment PIN_AB6 -to cart_tran_bank0_dir +set_location_assignment PIN_AA10 -to cart_tran_bank1[7] +set_location_assignment PIN_AB10 -to cart_tran_bank1[6] +set_location_assignment PIN_Y10 -to cart_tran_bank1[5] +set_location_assignment PIN_AB11 -to cart_tran_bank1[4] +set_location_assignment PIN_Y11 -to cart_tran_bank1[3] +set_location_assignment PIN_AB12 -to cart_tran_bank1[2] +set_location_assignment PIN_AA12 -to cart_tran_bank1[1] +set_location_assignment PIN_AB13 -to cart_tran_bank1[0] +set_location_assignment PIN_AA13 -to cart_tran_bank1_dir +set_location_assignment PIN_AB15 -to cart_tran_bank2[7] +set_location_assignment PIN_AA15 -to cart_tran_bank2[6] +set_location_assignment PIN_AB17 -to cart_tran_bank2[5] +set_location_assignment PIN_AA17 -to cart_tran_bank2[4] +set_location_assignment PIN_AB18 -to cart_tran_bank2[3] +set_location_assignment PIN_AB20 -to cart_tran_bank2[0] +set_location_assignment PIN_AA19 -to cart_tran_bank2[1] +set_location_assignment PIN_AA18 -to cart_tran_bank2[2] +set_location_assignment PIN_AA14 -to cart_tran_bank2_dir +set_location_assignment PIN_AA20 -to cart_tran_bank3[7] +set_location_assignment PIN_AB21 -to cart_tran_bank3[6] +set_location_assignment PIN_AB22 -to cart_tran_bank3[5] +set_location_assignment PIN_AA22 -to cart_tran_bank3[4] +set_location_assignment PIN_Y21 -to cart_tran_bank3[3] +set_location_assignment PIN_Y22 -to cart_tran_bank3[2] +set_location_assignment PIN_W21 -to cart_tran_bank3[1] +set_location_assignment PIN_W22 -to cart_tran_bank3[0] +set_location_assignment PIN_V21 -to cart_tran_bank3_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank0_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank1_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank2_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_bank3_dir + +# ============================================================================== +# GBA CS2#/RES# +# ============================================================================== +set_location_assignment PIN_AB5 -to cart_tran_pin30_dir +set_location_assignment PIN_L8 -to cart_tran_pin30 +set_location_assignment PIN_L17 -to cart_pin30_pwroff_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_pin30_pwroff_reset +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin30 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin30_dir +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_pin30_pwroff_reset +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin30 + +# ============================================================================== +# GBA IRQ/DRQ +# ============================================================================== +set_location_assignment PIN_K9 -to cart_tran_pin31 +set_location_assignment PIN_U22 -to cart_tran_pin31_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to cart_tran_pin31 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to cart_tran_pin31_dir +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cart_tran_pin31 + +# ============================================================================== +# GBA link port +# ============================================================================== +set_location_assignment PIN_V10 -to port_tran_si +set_location_assignment PIN_V9 -to port_tran_si_dir +set_location_assignment PIN_J11 -to port_tran_so +set_location_assignment PIN_T13 -to port_tran_so_dir +set_location_assignment PIN_AA7 -to port_tran_sck +set_location_assignment PIN_Y9 -to port_tran_sck_dir +set_location_assignment PIN_R9 -to port_tran_sd +set_location_assignment PIN_T9 -to port_tran_sd_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_si_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_so_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sck_dir +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to port_tran_sd_dir +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_tran_so +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_tran_so + +# ============================================================================== +# I/O to 6515D Breakout USB UART +# ============================================================================== +set_location_assignment PIN_K21 -to dbg_tx +set_location_assignment PIN_K22 -to dbg_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to dbg_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to dbg_tx + +# ============================================================================== +# Infrared +# ============================================================================== +set_location_assignment PIN_H10 -to port_ir_rx +set_location_assignment PIN_H11 -to port_ir_tx +set_location_assignment PIN_L18 -to port_ir_rx_disable +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_tx +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx +set_instance_assignment -name IO_STANDARD "1.8 V" -to port_ir_rx_disable +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_tx +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx_disable +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to port_ir_rx + +# ============================================================================== +# RFU internal I2C bus (DNU) +# ============================================================================== +set_location_assignment PIN_M16 -to aux_scl +set_location_assignment PIN_M18 -to aux_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_sda +set_instance_assignment -name IO_STANDARD "1.8 V" -to aux_scl +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_sda +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to aux_scl + +# ============================================================================== +# I/O pads near jtag connector user can solder to +# ============================================================================== +set_location_assignment PIN_M22 -to user1 +set_location_assignment PIN_L22 -to user2 +set_instance_assignment -name IO_STANDARD "1.8 V" -to user1 +set_instance_assignment -name IO_STANDARD "1.8 V" -to user2 + +# ============================================================================== +# VBlank output to scaler +# ============================================================================== +set_location_assignment PIN_N19 -to vblank +set_instance_assignment -name IO_STANDARD "1.8 V" -to vblank + +# ============================================================================== +# Video output to the scaler +# ============================================================================== +set_location_assignment PIN_H15 -to scal_audadc +set_location_assignment PIN_K19 -to scal_auddac +set_location_assignment PIN_K17 -to scal_audlrck +set_location_assignment PIN_K16 -to scal_audmclk +set_location_assignment PIN_R17 -to scal_clk +set_location_assignment PIN_N20 -to scal_de +set_location_assignment PIN_P17 -to scal_hs +set_location_assignment PIN_N21 -to scal_skip +set_location_assignment PIN_T15 -to scal_vs +set_location_assignment PIN_R16 -to scal_vid[11] +set_location_assignment PIN_R15 -to scal_vid[10] +set_location_assignment PIN_R22 -to scal_vid[9] +set_location_assignment PIN_T22 -to scal_vid[8] +set_location_assignment PIN_T18 -to scal_vid[7] +set_location_assignment PIN_T19 -to scal_vid[6] +set_location_assignment PIN_T20 -to scal_vid[5] +set_location_assignment PIN_P19 -to scal_vid[4] +set_location_assignment PIN_P18 -to scal_vid[3] +set_location_assignment PIN_N16 -to scal_vid[2] +set_location_assignment PIN_P22 -to scal_vid[1] +set_location_assignment PIN_R21 -to scal_vid[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audadc +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_auddac +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audlrck +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_audmclk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_de +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_hs +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_skip +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vid[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to scal_vs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_auddac +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audlrck +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_audmclk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_clk +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_de +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_hs +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_skip +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[0] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[10] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[11] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[1] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[2] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[3] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[4] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[5] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[6] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[7] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[8] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vid[9] +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to scal_vs + +# ============================================================================== +# SDRAM, 512mbit x16 +# ============================================================================== +set_location_assignment PIN_J17 -to dram_a[12] +set_location_assignment PIN_F15 -to dram_a[11] +set_location_assignment PIN_C13 -to dram_a[10] +set_location_assignment PIN_G17 -to dram_a[9] +set_location_assignment PIN_J18 -to dram_a[8] +set_location_assignment PIN_F14 -to dram_a[7] +set_location_assignment PIN_E15 -to dram_a[6] +set_location_assignment PIN_E16 -to dram_a[5] +set_location_assignment PIN_F13 -to dram_a[4] +set_location_assignment PIN_E14 -to dram_a[3] +set_location_assignment PIN_F12 -to dram_a[2] +set_location_assignment PIN_D12 -to dram_a[1] +set_location_assignment PIN_D17 -to dram_a[0] +set_location_assignment PIN_E12 -to dram_ba[1] +set_location_assignment PIN_C16 -to dram_ba[0] +set_location_assignment PIN_K20 -to dram_dq[15] +set_location_assignment PIN_G11 -to dram_dq[14] +set_location_assignment PIN_J19 -to dram_dq[13] +set_location_assignment PIN_H13 -to dram_dq[12] +set_location_assignment PIN_G13 -to dram_dq[11] +set_location_assignment PIN_G16 -to dram_dq[10] +set_location_assignment PIN_G15 -to dram_dq[9] +set_location_assignment PIN_J13 -to dram_dq[8] +set_location_assignment PIN_A12 -to dram_dq[7] +set_location_assignment PIN_A13 -to dram_dq[6] +set_location_assignment PIN_B12 -to dram_dq[5] +set_location_assignment PIN_A14 -to dram_dq[4] +set_location_assignment PIN_B13 -to dram_dq[3] +set_location_assignment PIN_A15 -to dram_dq[2] +set_location_assignment PIN_B15 -to dram_dq[1] +set_location_assignment PIN_C15 -to dram_dq[0] +set_location_assignment PIN_D13 -to dram_dqm[0] +set_location_assignment PIN_H18 -to dram_dqm[1] +set_location_assignment PIN_B16 -to dram_cas_n +set_location_assignment PIN_G18 -to dram_cke +set_location_assignment PIN_G12 -to dram_clk +set_location_assignment PIN_B11 -to dram_ras_n +set_location_assignment PIN_C11 -to dram_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_a[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ba[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cas_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_cke +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_dqm[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_ras_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to dram_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_a[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ba[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cas_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_cke +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_dqm[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_ras_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to dram_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to dram_clk + +# ============================================================================== +# Cellular PSRAM 0 - 64mbit x2 dual die per chip +# ============================================================================== +set_location_assignment PIN_H8 -to cram0_a[21] +set_location_assignment PIN_H9 -to cram0_a[20] +set_location_assignment PIN_B7 -to cram0_a[19] +set_location_assignment PIN_B6 -to cram0_a[18] +set_location_assignment PIN_C6 -to cram0_a[17] +set_location_assignment PIN_H6 -to cram0_a[16] +set_location_assignment PIN_J9 -to cram0_dq[15] +set_location_assignment PIN_L7 -to cram0_dq[14] +set_location_assignment PIN_F9 -to cram0_dq[13] +set_location_assignment PIN_E7 -to cram0_dq[12] +set_location_assignment PIN_A8 -to cram0_dq[11] +set_location_assignment PIN_D9 -to cram0_dq[10] +set_location_assignment PIN_A10 -to cram0_dq[9] +set_location_assignment PIN_C9 -to cram0_dq[8] +set_location_assignment PIN_J7 -to cram0_dq[7] +set_location_assignment PIN_G6 -to cram0_dq[6] +set_location_assignment PIN_F10 -to cram0_dq[5] +set_location_assignment PIN_E9 -to cram0_dq[4] +set_location_assignment PIN_D7 -to cram0_dq[3] +set_location_assignment PIN_A9 -to cram0_dq[2] +set_location_assignment PIN_C8 -to cram0_dq[1] +set_location_assignment PIN_B10 -to cram0_dq[0] +set_location_assignment PIN_J8 -to cram0_adv_n +set_location_assignment PIN_B5 -to cram0_ce0_n +set_location_assignment PIN_E10 -to cram0_ce1_n +set_location_assignment PIN_G10 -to cram0_clk +set_location_assignment PIN_F7 -to cram0_cre +set_location_assignment PIN_A5 -to cram0_lb_n +set_location_assignment PIN_D6 -to cram0_oe_n +set_location_assignment PIN_A7 -to cram0_ub_n +set_location_assignment PIN_K7 -to cram0_wait +set_location_assignment PIN_G8 -to cram0_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram0_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram0_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram0_clk + +# ============================================================================== +# Cellular PSRAM 1 - 64mbit x2 dual die per chip +# ============================================================================== +set_location_assignment PIN_Y3 -to cram1_a[21] +set_location_assignment PIN_AA2 -to cram1_a[20] +set_location_assignment PIN_L2 -to cram1_a[19] +set_location_assignment PIN_N1 -to cram1_a[18] +set_location_assignment PIN_U1 -to cram1_a[17] +set_location_assignment PIN_U2 -to cram1_a[16] +set_location_assignment PIN_W8 -to cram1_dq[15] +set_location_assignment PIN_U6 -to cram1_dq[14] +set_location_assignment PIN_R7 -to cram1_dq[13] +set_location_assignment PIN_R6 -to cram1_dq[12] +set_location_assignment PIN_P7 -to cram1_dq[11] +set_location_assignment PIN_N6 -to cram1_dq[10] +set_location_assignment PIN_C2 -to cram1_dq[9] +set_location_assignment PIN_D3 -to cram1_dq[8] +set_location_assignment PIN_V6 -to cram1_dq[7] +set_location_assignment PIN_U7 -to cram1_dq[6] +set_location_assignment PIN_M6 -to cram1_dq[5] +set_location_assignment PIN_R5 -to cram1_dq[4] +set_location_assignment PIN_P6 -to cram1_dq[3] +set_location_assignment PIN_E2 -to cram1_dq[2] +set_location_assignment PIN_G2 -to cram1_dq[1] +set_location_assignment PIN_C1 -to cram1_dq[0] +set_location_assignment PIN_U8 -to cram1_adv_n +set_location_assignment PIN_N2 -to cram1_ce0_n +set_location_assignment PIN_T8 -to cram1_ce1_n +set_location_assignment PIN_W2 -to cram1_clk +set_location_assignment PIN_T7 -to cram1_cre +set_location_assignment PIN_L1 -to cram1_lb_n +set_location_assignment PIN_M7 -to cram1_oe_n +set_location_assignment PIN_G1 -to cram1_ub_n +set_location_assignment PIN_W9 -to cram1_wait +set_location_assignment PIN_AA1 -to cram1_we_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[2] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[3] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[4] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[5] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[6] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[7] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[8] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[9] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[10] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[11] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[12] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[13] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[14] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_dq[15] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[16] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[17] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[18] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[19] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[20] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_a[21] +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_adv_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce0_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ce1_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_cre +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_lb_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_oe_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_ub_n +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_wait +set_instance_assignment -name IO_STANDARD "1.8 V" -to cram1_we_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_dq[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[16] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[17] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[18] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[19] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[20] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_a[21] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_adv_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce0_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ce1_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_cre +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_lb_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_oe_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_ub_n +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_wait +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to cram1_we_n +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to cram1_clk + +# ============================================================================== +# SRAM, 1mbit x16 +# ============================================================================== +set_location_assignment PIN_V16 -to sram_a[16] +set_location_assignment PIN_U12 -to sram_a[15] +set_location_assignment PIN_U15 -to sram_a[14] +set_location_assignment PIN_R10 -to sram_a[13] +set_location_assignment PIN_V14 -to sram_a[12] +set_location_assignment PIN_T10 -to sram_a[11] +set_location_assignment PIN_U11 -to sram_a[10] +set_location_assignment PIN_Y14 -to sram_a[9] +set_location_assignment PIN_U13 -to sram_a[8] +set_location_assignment PIN_Y19 -to sram_a[7] +set_location_assignment PIN_P8 -to sram_a[6] +set_location_assignment PIN_V19 -to sram_a[5] +set_location_assignment PIN_N9 -to sram_a[4] +set_location_assignment PIN_U21 -to sram_a[3] +set_location_assignment PIN_M8 -to sram_a[2] +set_location_assignment PIN_M9 -to sram_a[1] +set_location_assignment PIN_T14 -to sram_a[0] +set_location_assignment PIN_Y15 -to sram_dq[15] +set_location_assignment PIN_W16 -to sram_dq[14] +set_location_assignment PIN_Y16 -to sram_dq[13] +set_location_assignment PIN_Y17 -to sram_dq[12] +set_location_assignment PIN_V20 -to sram_dq[11] +set_location_assignment PIN_V18 -to sram_dq[10] +set_location_assignment PIN_U20 -to sram_dq[9] +set_location_assignment PIN_U16 -to sram_dq[8] +set_location_assignment PIN_R12 -to sram_dq[7] +set_location_assignment PIN_V13 -to sram_dq[6] +set_location_assignment PIN_T12 -to sram_dq[5] +set_location_assignment PIN_W19 -to sram_dq[4] +set_location_assignment PIN_Y20 -to sram_dq[3] +set_location_assignment PIN_P14 -to sram_dq[2] +set_location_assignment PIN_P9 -to sram_dq[1] +set_location_assignment PIN_N8 -to sram_dq[0] +set_location_assignment PIN_U17 -to sram_ub_n +set_location_assignment PIN_R11 -to sram_we_n +set_location_assignment PIN_R14 -to sram_oe_n +set_location_assignment PIN_P12 -to sram_lb_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_a[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_dq[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_lb_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_oe_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_ub_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sram_we_n + +# ============================================================================== +# Powerup self test (DO NOT USE) +# ============================================================================== +set_location_assignment PIN_P16 -to vpll_feed +set_location_assignment PIN_U10 -to bist +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to bist +set_instance_assignment -name IO_STANDARD "1.8 V" -to vpll_feed +set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to vpll_feed + +# ============================================================================== +# Advanced I/O Timing Assignments +# ============================================================================== +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +# ============================================================================== +# Scripts +# ============================================================================== +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:../platform/pocket/build_id_gen.tcl" +set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:../platform/pocket/build_cdf.tcl" + +# ============================================================================== +# Framework Files +# ============================================================================== +set_global_assignment -name QIP_FILE ../platform/pocket/apf.qip +set_global_assignment -name QIP_FILE ../target/pocket/core.qip diff --git a/projects/xevious_pocket.qpf b/projects/xevious_pocket.qpf new file mode 100644 index 0000000..03da6e7 --- /dev/null +++ b/projects/xevious_pocket.qpf @@ -0,0 +1,11 @@ +# ============================================================================== +# Quartus Prime Project File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== + +QUARTUS_VERSION = "18.1" +DATE = "13:58:43 September 10, 2022" + +# Revisions + +PROJECT_REVISION = "xevious_pocket" diff --git a/projects/xevious_pocket.qsf b/projects/xevious_pocket.qsf new file mode 100644 index 0000000..f2f9134 --- /dev/null +++ b/projects/xevious_pocket.qsf @@ -0,0 +1,57 @@ +# ============================================================================== +# Quartus Prime Settings File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== +# WARNING: DO NOT ADD FILES TO THE PROJECT VIA THE QUARTUS IDE! +# Add them manually to xevious_pocket.qip or Quartus will overwrite this file. +# ============================================================================== +# Project Assignments +# ============================================================================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.1 +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" +set_global_assignment -name TOP_LEVEL_ENTITY apf_top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT" +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SEED 1 +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON +set_global_assignment -name MUX_RESTRUCTURE OFF +set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" + +# ============================================================================== +# Platform Specific Modules +# ============================================================================== +set_global_assignment -name QIP_FILE "../modules/pocket-i2s/index.qip" +set_global_assignment -name QIP_FILE "../modules/pocket-joypad/index.qip" +set_global_assignment -name QIP_FILE "../modules/pocket-dataloader/index.qip" + +# ============================================================================== +# File Assignments +# ============================================================================== +source ../platform/pocket/pocket.tcl +set_global_assignment -name QIP_FILE ../rtl/xevious.qip +set_global_assignment -name SDC_FILE xevious_pocket.sdc + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/projects/xevious_pocket.sdc b/projects/xevious_pocket.sdc new file mode 100644 index 0000000..4b5d796 --- /dev/null +++ b/projects/xevious_pocket.sdc @@ -0,0 +1,61 @@ +# ============================================================================== +# Quartus Prime Synopsys Design Constraint File +# Generated by OpenGateware - Gateman CLI v0.1.0 +# ============================================================================== +# pocket SDC settings +# Users are recommended to modify this file to match users logic. +# Put your clock groups in here as well as any net assignments. +# ============================================================================== + +# ============================================================================== +# Time Information +# ============================================================================== + +# ============================================================================== +# Create Clock +# ============================================================================== + +# ============================================================================== +# Create Generated Clock +# ============================================================================== + +# ============================================================================== +# Set Clock Latency +# ============================================================================== + +# ============================================================================== +# Set Clock Uncertainty +# ============================================================================== + +# ============================================================================== +# Set Input Delay +# ============================================================================== + +# ============================================================================== +# Set Output Delay +# ============================================================================== + +# ============================================================================== +# Set Clock Groups +# ============================================================================== + +# ============================================================================== +# Set False Path +# ============================================================================== + +# ============================================================================== +# Set Multicycle Path +# ============================================================================== + +# ============================================================================== +# Set Maximum Delay +# ============================================================================== + +# ============================================================================== +# Set Minimum Delay +# ============================================================================== + +# ============================================================================== +# Set Input Transition +# ============================================================================== + diff --git a/rtl/dpram.vhd b/rtl/dpram.vhd new file mode 100644 index 0000000..d78b851 --- /dev/null +++ b/rtl/dpram.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; + +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity dpram is + generic ( + addr_width_g : integer := 8; + data_width_g : integer := 8 + ); + port ( + address_a : in std_logic_vector (addr_width_g - 1 downto 0); + address_b : in std_logic_vector (addr_width_g - 1 downto 0); + clock_a : in std_logic := '1'; + clock_b : in std_logic; + data_a : in std_logic_vector (data_width_g - 1 downto 0); + data_b : in std_logic_vector (data_width_g - 1 downto 0) := (others => '0'); + enable_a : in std_logic := '1'; + enable_b : in std_logic := '1'; + wren_a : in std_logic := '0'; + wren_b : in std_logic := '0'; + q_a : out std_logic_vector (data_width_g - 1 downto 0); + q_b : out std_logic_vector (data_width_g - 1 downto 0) + ); +end dpram; +architecture SYN of dpram is +begin + altsyncram_component : altsyncram + generic map( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone V", + lpm_type => "altsyncram", + numwords_a => 2 ** addr_width_g, + numwords_b => 2 ** addr_width_g, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => addr_width_g, + widthad_b => addr_width_g, + width_a => data_width_g, + width_b => data_width_g, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + port map( + address_a => address_a, + address_b => address_b, + clock0 => clock_a, + clock1 => clock_b, + clocken0 => enable_a, + clocken1 => enable_b, + data_a => data_a, + data_b => data_b, + wren_a => wren_a, + wren_b => wren_b, + q_a => q_a, + q_b => q_b + ); + +end SYN; diff --git a/rtl/gen_ram.vhd b/rtl/gen_ram.vhd new file mode 100644 index 0000000..f1a9560 --- /dev/null +++ b/rtl/gen_ram.vhd @@ -0,0 +1,84 @@ +-- ----------------------------------------------------------------------- +-- +-- Syntiac's generic VHDL support files. +-- +-- ----------------------------------------------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +-- +-- Modified April 2016 by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +-- Remove address register when writing +-- +-- ----------------------------------------------------------------------- +-- +-- gen_rwram.vhd +-- +-- ----------------------------------------------------------------------- +-- +-- generic ram. +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.ALL; + +-- ----------------------------------------------------------------------- + +entity gen_ram is + generic ( + dWidth : integer := 8; + aWidth : integer := 10 + ); + port ( + clk : in std_logic; + we : in std_logic; + addr : in std_logic_vector((aWidth-1) downto 0); + d : in std_logic_vector((dWidth-1) downto 0); + q : out std_logic_vector((dWidth-1) downto 0) + ); +end entity; + +-- ----------------------------------------------------------------------- + +architecture rtl of gen_ram is + subtype addressRange is integer range 0 to ((2**aWidth)-1); + type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0); + signal ram: ramDef; + + signal rAddrReg : std_logic_vector((aWidth-1) downto 0); + signal qReg : std_logic_vector((dWidth-1) downto 0); +begin +-- ----------------------------------------------------------------------- +-- Signals to entity interface +-- ----------------------------------------------------------------------- +-- q <= qReg; + +-- ----------------------------------------------------------------------- +-- Memory write +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if we = '1' then + ram(to_integer(unsigned(addr))) <= d; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Memory read +-- ----------------------------------------------------------------------- +process(clk) + begin + if rising_edge(clk) then +-- qReg <= ram(to_integer(unsigned(rAddrReg))); +-- rAddrReg <= addr; +---- qReg <= ram(to_integer(unsigned(addr))); + q <= ram(to_integer(unsigned(addr))); + end if; + end process; +--q <= ram(to_integer(unsigned(addr))); +end architecture; + diff --git a/rtl/gen_video.vhd b/rtl/gen_video.vhd new file mode 100644 index 0000000..a0126f5 --- /dev/null +++ b/rtl/gen_video.vhd @@ -0,0 +1,125 @@ +--------------------------------------------------------------------------------- +-- Xevious video horizontal/vertical and sync generator by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all, + ieee.std_logic_1164.all, + ieee.std_logic_unsigned.all, + ieee.numeric_std.all; + + +entity gen_video is +port( + clk : in std_logic; + enable : in std_logic; + hcnt : out std_logic_vector(8 downto 0); + vcnt : out std_logic_vector(8 downto 0); + hsync : out std_logic; + vsync : out std_logic; + csync : out std_logic; -- composite sync for TV + blank_h : out std_logic; + blank_v : out std_logic; + blankn : out std_logic; + h_offset: in signed(3 downto 0); + v_offset: in signed(3 downto 0) +); +end gen_video; + +architecture struct of gen_video is +signal hclkReg : unsigned (1 DOWNTO 0); +signal hblank : std_logic; +signal vblank : std_logic; +signal hcntReg : unsigned (8 DOWNTO 0) := to_unsigned( 0, 9); +signal vcntReg : unsigned (8 DOWNTO 0) := to_unsigned(15, 9); + +signal hsync0 : std_logic; +signal hsync1 : std_logic; +signal hsync2 : std_logic; + +signal hsync_base : integer; +signal vsync_base : integer; +begin + +blank_h <= hblank; +blank_v <= vblank; + +hcnt <= std_logic_vector(hcntReg); +vcnt <= std_logic_vector(vcntReg); +hsync <= not hsync0; + +-- Compteur horizontal : 511-128+1=384 pixels (48 tiles) +-- 128 à 191 : 64 pixels debut de ligne (8 dont 2 dernières tiles affichées) +-- 192 à 447 : 256 pixels centre de ligne (32 tiles affichées) +-- 448 à 511 : 64 pixels fin de ligne (8 dont 2 premières tiles affichées) + +-- Compteur vertical : 263-000+1=264 lignes (33 tiles) +-- 000 à 015 : 16 lignes debut de trame (2 tiles) +-- 016 à 239 : 224 lignes centrales (28 tiles affichées) +-- 240 à 263 : 24 lignes fin de trame (3 tiles) + +--- Synchro horizontale : hcnt=[495-511/128-140] (29 pixels) +--- Synchro verticale : vcnt=[260-263/000-003] ( 8 lignes) + +process(clk) +begin + if rising_edge(clk) then + if enable = '1' then -- clk & ena at 6MHz + + if hcntReg = 511 then + hcntReg <= to_unsigned (128,9); + if vcntReg = 263 then + vcntReg <= to_unsigned(0,9); + else + vcntReg <= vcntReg + 1; + end if; + else + hcntReg <= hcntReg + 1; + end if; + + hsync_base <= 495 + to_integer(resize(h_offset, 9)); + if hcntReg = (hsync_base) then hsync0 <= '0'; -- 1 + elsif hcntReg = (hsync_base+29-384) then hsync0 <= '1'; + end if; + + if hcntReg = (hsync_base) then hsync1 <= '0'; + elsif hcntReg = (hsync_base+13) then hsync1 <= '1'; -- 11 + elsif hcntReg = (hsync_base +192-384) then hsync1 <= '0'; + elsif hcntReg = (hsync_base+13+192-384) then hsync1 <= '1'; -- 11 + end if; + + if hcntReg = (hsync_base) then hsync2 <= '0'; + elsif hcntReg = (hsync_base-28) then hsync2 <= '1'; + end if; + + vsync_base <= 250+to_integer(resize(v_offset, 9)); + if vcntReg = (vsync_base+ 2-1+2) mod 264 then csync <= hsync1; + elsif vcntReg = (vsync_base+ 3-1+2) mod 264 then csync <= hsync1; + elsif vcntReg = (vsync_base+ 4-1+2) mod 264 then csync <= hsync1; -- and hsync2; + elsif vcntReg = (vsync_base+ 5-1+2) mod 264 then csync <= hsync2; -- not(hsync1); + elsif vcntReg = (vsync_base+ 6-1+2) mod 264 then csync <= hsync2; -- not(hsync1); + elsif vcntReg = (vsync_base+ 7-1+2) mod 264 then csync <= hsync2; -- not(hsync1) or not(hsync2); + elsif vcntReg = (vsync_base+ 8-1+2) mod 264 then csync <= hsync1; + elsif vcntReg = (vsync_base+ 9-1+2) mod 264 then csync <= hsync1; + elsif vcntReg = (vsync_base+10-1+2) mod 264 then csync <= hsync1; + else csync <= hsync0; + end if; + + if vcntReg = (vsync_base+10) mod 264 then vsync <= '1'; + elsif vcntReg = (vsync_base+17) mod 264 then vsync <= '0'; + end if; + + if hcntReg = (448+16+8+1) then hblank <= '1'; + elsif hcntReg = (192-16+8+1) then hblank <= '0'; + end if; + + if vcntReg = (240+2) then vblank <= '1'; + elsif vcntReg = (016+2) then vblank <= '0'; + end if; + + blankn <= not (hblank or vblank); + end if; + end if; +end process; + +end architecture; diff --git a/rtl/prom/bg_palette_lsb.vhd b/rtl/prom/bg_palette_lsb.vhd new file mode 100644 index 0000000..95df556 --- /dev/null +++ b/rtl/prom/bg_palette_lsb.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity bg_palette_lsb is + port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of bg_palette_lsb is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"0A", X"0B", X"0D", X"0E", X"0C", X"09", X"06", X"0A", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"0C", X"00", X"0B", X"0A", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"0C", X"0B", X"0A", X"0A", + X"0A", X"08", X"09", X"06", X"00", X"00", X"00", X"00", X"0A", X"02", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"0A", X"08", X"09", X"0B", X"06", X"09", X"05", X"07", X"0A", X"00", X"05", X"09", X"06", X"02", X"0C", X"00", + X"05", X"0D", X"0C", X"00", X"06", X"08", X"09", X"0B", X"00", X"0D", X"03", X"0F", X"09", X"09", X"0A", X"0B", + X"0C", X"0A", X"0B", X"09", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"04", X"08", X"0B", X"0A", + X"0C", X"0D", X"04", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"02", X"00", + X"00", X"0D", X"02", X"0C", X"0C", X"0D", X"02", X"00", X"00", X"0D", X"03", X"0F", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"0F", X"0D", X"01", X"04", X"00", X"00", X"09", X"04", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"0A", X"00", X"04", X"08", X"06", X"0C", X"05", X"05", X"00", X"00", X"05", X"00", X"06", X"09", X"04", X"00", + X"00", X"0D", X"05", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"03", X"00", + X"00", X"0D", X"03", X"0C", X"0C", X"0D", X"03", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/bg_palette_msb.vhd b/rtl/prom/bg_palette_msb.vhd new file mode 100644 index 0000000..6b482c4 --- /dev/null +++ b/rtl/prom/bg_palette_msb.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity bg_palette_msb is + port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of bg_palette_msb is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"01", X"01", X"00", + X"00", X"02", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"02", X"01", X"02", X"02", X"02", X"02", X"02", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"01", X"01", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"01", X"00", X"01", X"00", X"00", + X"00", X"01", X"00", X"00", X"00", X"01", X"01", X"01", X"00", X"03", X"00", X"00", X"01", X"01", X"01", X"01", + X"00", X"00", X"01", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"02", X"01", X"01", X"00", + X"00", X"01", X"02", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"02", X"02", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"02", X"02", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"03", X"00", X"00", + X"00", X"03", X"00", X"03", X"03", X"03", X"00", X"00", X"00", X"03", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"02", X"00", X"00", X"00", X"02", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"02", X"01", X"00", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"02", X"00", + X"00", X"01", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"03", X"00", X"00", + X"00", X"03", X"00", X"03", X"03", X"03", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/blue.vhd b/rtl/prom/blue.vhd new file mode 100644 index 0000000..1ba6272 --- /dev/null +++ b/rtl/prom/blue.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity blue is + port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of blue is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"06", X"0F", X"0C", X"02", X"0A", X"0F", X"0F", X"00", X"0C", X"02", X"00", X"04", X"02", X"02", X"05", + X"03", X"03", X"09", X"00", X"00", X"00", X"00", X"02", X"00", X"00", X"00", X"01", X"0C", X"07", X"02", X"02", + X"04", X"02", X"00", X"00", X"07", X"08", X"00", X"07", X"0B", X"0C", X"06", X"08", X"0C", X"0A", X"00", X"00", + X"06", X"0B", X"00", X"00", X"06", X"04", X"00", X"00", X"00", X"0A", X"00", X"00", X"0F", X"0F", X"0E", X"02", + X"00", X"00", X"00", X"00", X"04", X"0F", X"0F", X"00", X"00", X"00", X"06", X"06", X"08", X"0A", X"09", X"08", + X"08", X"02", X"0B", X"00", X"02", X"0F", X"04", X"0F", X"00", X"00", X"00", X"0A", X"06", X"04", X"04", X"0C", + X"06", X"04", X"02", X"03", X"00", X"0C", X"02", X"04", X"08", X"0A", X"04", X"02", X"00", X"0F", X"0F", X"00", + X"00", X"00", X"00", X"00", X"08", X"04", X"08", X"04", X"08", X"04", X"08", X"04", X"0C", X"0A", X"06", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/green.vhd b/rtl/prom/green.vhd new file mode 100644 index 0000000..aa671f0 --- /dev/null +++ b/rtl/prom/green.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity green is + port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of green is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"06", X"08", X"0C", X"02", X"0A", X"07", X"04", X"09", X"0C", X"08", X"06", X"09", X"03", X"05", X"05", + X"08", X"08", X"08", X"06", X"0B", X"06", X"04", X"03", X"02", X"04", X"06", X"07", X"09", X"09", X"08", X"08", + X"08", X"06", X"06", X"05", X"07", X"08", X"00", X"08", X"07", X"08", X"0B", X"06", X"0B", X"05", X"0C", X"00", + X"04", X"08", X"05", X"0A", X"08", X"04", X"0F", X"0A", X"06", X"06", X"0A", X"00", X"00", X"0F", X"0E", X"02", + X"06", X"0B", X"05", X"08", X"04", X"0F", X"08", X"00", X"00", X"03", X"04", X"04", X"05", X"08", X"07", X"06", + X"02", X"06", X"05", X"04", X"07", X"08", X"04", X"0C", X"06", X"00", X"0E", X"0C", X"0C", X"0C", X"08", X"0C", + X"0F", X"0B", X"07", X"03", X"08", X"04", X"04", X"06", X"0A", X"0C", X"08", X"04", X"0F", X"00", X"00", X"04", + X"02", X"08", X"04", X"04", X"08", X"04", X"00", X"00", X"00", X"00", X"00", X"00", X"0F", X"0F", X"0A", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/red.vhd b/rtl/prom/red.vhd new file mode 100644 index 0000000..f7d583d --- /dev/null +++ b/rtl/prom/red.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity red is + port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of red is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"06", X"03", X"00", X"05", X"0A", X"02", X"05", X"09", X"0C", X"04", X"04", X"09", X"06", X"05", X"05", + X"07", X"05", X"05", X"08", X"0D", X"0C", X"07", X"04", X"02", X"02", X"02", X"03", X"05", X"09", X"07", X"08", + X"0A", X"08", X"07", X"06", X"07", X"08", X"0F", X"04", X"03", X"00", X"0D", X"00", X"0A", X"02", X"00", X"0A", + X"02", X"04", X"05", X"0A", X"08", X"08", X"0F", X"0F", X"0F", X"02", X"0E", X"0C", X"00", X"0F", X"0E", X"02", + X"0C", X"0D", X"00", X"00", X"04", X"00", X"00", X"08", X"06", X"00", X"0C", X"04", X"05", X"08", X"07", X"06", + X"02", X"08", X"02", X"05", X"0B", X"0F", X"0C", X"00", X"0A", X"04", X"0E", X"0F", X"0F", X"0F", X"0C", X"0C", + X"0F", X"0B", X"07", X"03", X"0F", X"04", X"04", X"06", X"0A", X"0C", X"0A", X"08", X"00", X"08", X"0F", X"08", + X"04", X"08", X"04", X"00", X"00", X"00", X"00", X"00", X"04", X"02", X"08", X"04", X"0F", X"0F", X"0F", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/sound_samples.vhd b/rtl/prom/sound_samples.vhd new file mode 100644 index 0000000..c5ccfaa --- /dev/null +++ b/rtl/prom/sound_samples.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity sound_samples is + port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of sound_samples is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"09", X"0A", X"0B", X"0C", X"0D", X"0D", X"0E", X"0E", X"0E", X"0D", X"0D", X"0C", X"0B", X"0A", X"09", X"07", + X"05", X"04", X"03", X"02", X"01", X"01", X"00", X"00", X"00", X"01", X"01", X"02", X"03", X"04", X"05", X"07", + X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"07", X"0A", X"0C", X"0D", X"0E", X"0D", X"0C", X"0A", X"07", X"04", X"02", X"01", X"00", X"01", X"02", X"04", + X"07", X"0B", X"0D", X"0E", X"0D", X"0B", X"07", X"03", X"01", X"00", X"01", X"03", X"07", X"0E", X"07", X"00", + X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"0E", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"0E", X"0E", X"0E", X"00", X"00", X"00", X"0E", X"0E", X"0E", X"0E", X"0E", X"00", X"00", X"00", X"00", X"00", + X"0E", X"0E", X"00", X"00", X"0C", X"0C", X"0D", X"03", X"0E", X"0E", X"0C", X"0C", X"0C", X"0C", X"0D", X"07", + X"01", X"02", X"02", X"02", X"02", X"00", X"00", X"0B", X"01", X"02", X"02", X"0E", X"0E", X"00", X"00", X"07", + X"0E", X"0C", X"07", X"0A", X"0C", X"07", X"05", X"0C", X"0E", X"0D", X"08", X"0A", X"0B", X"06", X"02", X"07", + X"0C", X"08", X"03", X"04", X"06", X"01", X"00", X"03", X"09", X"07", X"02", X"04", X"07", X"02", X"00", X"07", + X"0C", X"0E", X"0E", X"0E", X"0E", X"0C", X"0B", X"09", X"07", X"06", X"05", X"05", X"05", X"06", X"08", X"0A", + X"0B", X"0B", X"09", X"06", X"04", X"02", X"02", X"02", X"03", X"05", X"04", X"03", X"02", X"01", X"03", X"07", + X"08", X"0B", X"0E", X"0D", X"07", X"0D", X"0E", X"0D", X"0C", X"0B", X"03", X"02", X"01", X"00", X"01", X"07", + X"01", X"00", X"03", X"06", X"08", X"0E", X"0D", X"0C", X"0E", X"08", X"03", X"00", X"02", X"01", X"00", X"06"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/sound_seq.vhd b/rtl/prom/sound_seq.vhd new file mode 100644 index 0000000..6161ec4 --- /dev/null +++ b/rtl/prom/sound_seq.vhd @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity sound_seq is + port ( + clk : in std_logic; + addr : in std_logic_vector(7 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of sound_seq is + type rom is array(0 to 255) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", + X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", + X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", + X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", X"0F", X"0D", X"0F", X"0F", + X"07", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", + X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0F", X"0B", X"07", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", + X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0F", X"0B", X"07", X"0F", X"0E", X"0D", + X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0E", X"0D", X"0F", X"0F", X"0F", X"0B", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/sp_palette_lsb.vhd b/rtl/prom/sp_palette_lsb.vhd new file mode 100644 index 0000000..6af95e4 --- /dev/null +++ b/rtl/prom/sp_palette_lsb.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity sp_palette_lsb is + port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of sp_palette_lsb is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"09", X"05", X"05", X"01", X"04", X"06", X"05", + X"00", X"06", X"00", X"06", X"07", X"04", X"08", X"09", X"00", X"0F", X"00", X"06", X"07", X"04", X"08", X"09", + X"00", X"07", X"00", X"06", X"07", X"04", X"08", X"09", X"00", X"08", X"00", X"06", X"07", X"04", X"08", X"09", + X"00", X"00", X"00", X"06", X"07", X"04", X"08", X"09", X"00", X"0D", X"05", X"05", X"01", X"04", X"00", X"06", + X"00", X"0D", X"05", X"05", X"01", X"04", X"00", X"0F", X"00", X"0D", X"05", X"05", X"01", X"04", X"00", X"07", + X"00", X"0D", X"05", X"05", X"01", X"04", X"00", X"09", X"00", X"0D", X"05", X"05", X"01", X"04", X"00", X"00", + X"00", X"05", X"01", X"0D", X"06", X"04", X"06", X"07", X"00", X"09", X"0A", X"0B", X"0D", X"09", X"00", X"06", + X"00", X"06", X"06", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"06", X"00", X"0D", X"00", X"00", X"00", X"00", X"00", X"0F", X"00", X"0D", X"00", X"00", X"00", X"00", + X"00", X"07", X"00", X"0D", X"00", X"00", X"00", X"00", X"00", X"08", X"00", X"0D", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"0D", X"00", X"00", X"00", X"00", X"00", X"06", X"07", X"07", X"09", X"09", X"00", X"06", + X"00", X"04", X"0F", X"0F", X"00", X"00", X"00", X"04", X"00", X"06", X"01", X"01", X"02", X"02", X"00", X"06", + X"00", X"0C", X"03", X"03", X"03", X"03", X"00", X"0C", X"00", X"05", X"04", X"04", X"05", X"05", X"00", X"05", + X"00", X"0C", X"06", X"06", X"07", X"07", X"00", X"0C", X"00", X"0D", X"08", X"08", X"09", X"09", X"00", X"0D", + X"00", X"0E", X"0A", X"0A", X"0B", X"0B", X"00", X"0E", X"00", X"0D", X"00", X"06", X"07", X"04", X"08", X"09", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"09", X"06", X"09", X"00", X"00", X"00", X"00", X"00", X"09", X"00", X"09", X"00", X"00", X"00", X"00", + X"00", X"04", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"06", X"06", X"00", X"00", X"00", X"00", + X"00", X"05", X"06", X"06", X"00", X"00", X"00", X"00", X"00", X"0D", X"06", X"00", X"00", X"00", X"00", X"00", + X"00", X"06", X"0D", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"06", X"00", X"00", X"00", X"00", X"00", + X"00", X"06", X"0D", X"00", X"00", X"00", X"00", X"00", X"00", X"09", X"06", X"06", X"00", X"00", X"00", X"00", + X"00", X"09", X"00", X"06", X"00", X"00", X"00", X"00", X"00", X"05", X"01", X"03", X"00", X"00", X"00", X"00", + X"00", X"05", X"04", X"00", X"00", X"00", X"00", X"00", X"00", X"0D", X"09", X"05", X"05", X"01", X"04", X"09", + X"00", X"0D", X"09", X"05", X"0C", X"0D", X"09", X"00", X"00", X"0D", X"0C", X"0D", X"0B", X"0C", X"0E", X"06", + X"00", X"0D", X"06", X"0F", X"05", X"05", X"01", X"04", X"00", X"08", X"0C", X"0F", X"04", X"0E", X"01", X"00", + X"00", X"0F", X"0F", X"00", X"0C", X"08", X"01", X"00", X"00", X"0D", X"0F", X"08", X"0F", X"05", X"05", X"01", + X"00", X"0F", X"07", X"08", X"0D", X"0F", X"05", X"05", X"00", X"0D", X"0F", X"05", X"05", X"04", X"06", X"0F", + X"00", X"0F", X"05", X"05", X"01", X"04", X"06", X"0F", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/prom/sp_palette_msb.vhd b/rtl/prom/sp_palette_msb.vhd new file mode 100644 index 0000000..bb45aee --- /dev/null +++ b/rtl/prom/sp_palette_msb.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all, ieee.numeric_std.all; + +entity sp_palette_msb is + port ( + clk : in std_logic; + addr : in std_logic_vector(8 downto 0); + data : out std_logic_vector(7 downto 0) + ); +end entity; + +architecture prom of sp_palette_msb is + type rom is array(0 to 511) of std_logic_vector(7 downto 0); + signal rom_data : rom := ( + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"08", X"08", X"0A", X"08", X"0C", X"0A", X"0E", + X"00", X"0A", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", X"00", X"0A", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", + X"00", X"0C", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", X"00", X"0C", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", + X"00", X"08", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", X"00", X"0B", X"08", X"0A", X"08", X"0C", X"08", X"0A", + X"00", X"0B", X"08", X"0A", X"08", X"0C", X"08", X"0A", X"00", X"0B", X"08", X"0A", X"08", X"0C", X"08", X"0C", + X"00", X"0B", X"08", X"0A", X"08", X"0C", X"08", X"0D", X"00", X"0B", X"08", X"0A", X"08", X"0C", X"08", X"08", + X"00", X"08", X"08", X"0B", X"0B", X"0E", X"0A", X"0C", X"00", X"0E", X"0E", X"0E", X"08", X"0D", X"08", X"0A", + X"00", X"0A", X"0B", X"00", X"00", X"00", X"00", X"00", X"00", X"0B", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"0A", X"08", X"0B", X"00", X"00", X"00", X"00", X"00", X"0A", X"08", X"0B", X"00", X"00", X"00", X"00", + X"00", X"0C", X"08", X"0B", X"00", X"00", X"00", X"00", X"00", X"0C", X"08", X"0B", X"00", X"00", X"00", X"00", + X"00", X"08", X"08", X"0B", X"00", X"00", X"00", X"00", X"00", X"0A", X"0C", X"0C", X"0D", X"0D", X"08", X"0A", + X"00", X"0E", X"0E", X"0E", X"0F", X"0F", X"08", X"0E", X"00", X"0B", X"0F", X"0F", X"0F", X"0F", X"00", X"0B", + X"00", X"0E", X"0C", X"0C", X"0F", X"0F", X"08", X"0E", X"00", X"0C", X"0F", X"0F", X"0F", X"0F", X"08", X"0C", + X"00", X"0B", X"0F", X"0F", X"0F", X"0F", X"00", X"0B", X"00", X"0E", X"0F", X"0F", X"0F", X"0F", X"00", X"0E", + X"00", X"0E", X"0F", X"0F", X"0F", X"0F", X"08", X"0E", X"00", X"0B", X"08", X"0E", X"0E", X"0B", X"0E", X"0E", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"08", X"0C", X"08", X"00", X"00", X"00", X"00", X"00", X"08", X"00", X"08", X"00", X"00", X"00", X"00", + X"00", X"0E", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"0B", X"0A", X"0C", X"00", X"00", X"00", X"00", + X"00", X"08", X"0A", X"0C", X"00", X"00", X"00", X"00", X"00", X"0B", X"0A", X"00", X"00", X"00", X"00", X"00", + X"00", X"0A", X"0B", X"00", X"00", X"00", X"00", X"00", X"00", X"0B", X"0C", X"00", X"00", X"00", X"00", X"00", + X"00", X"0C", X"0B", X"00", X"00", X"00", X"00", X"00", X"00", X"08", X"0C", X"0A", X"00", X"00", X"00", X"00", + X"00", X"08", X"00", X"0A", X"00", X"00", X"00", X"00", X"00", X"08", X"08", X"0E", X"00", X"00", X"00", X"00", + X"00", X"0A", X"0C", X"08", X"00", X"00", X"00", X"00", X"00", X"0B", X"08", X"08", X"0A", X"08", X"0C", X"0E", + X"00", X"0B", X"08", X"08", X"0F", X"0F", X"0E", X"00", X"00", X"0B", X"0F", X"0F", X"0D", X"0D", X"0F", X"0A", + X"00", X"0D", X"0A", X"0A", X"08", X"0A", X"08", X"0C", X"00", X"0D", X"0D", X"0A", X"0E", X"0D", X"08", X"08", + X"00", X"0A", X"09", X"0E", X"0F", X"0E", X"08", X"08", X"00", X"0B", X"0A", X"0C", X"0D", X"08", X"0A", X"08", + X"00", X"0A", X"0C", X"0C", X"0B", X"0D", X"08", X"0A", X"00", X"0B", X"0D", X"08", X"0A", X"0C", X"0A", X"0A", + X"00", X"0D", X"08", X"0A", X"08", X"0C", X"0A", X"0A", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", + X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"); +begin + process (clk) + begin + if rising_edge(clk) then + data <= rom_data(to_integer(unsigned(addr))); + end if; + end process; +end architecture; diff --git a/rtl/sound_lpf.vhd b/rtl/sound_lpf.vhd new file mode 100644 index 0000000..1f40e82 --- /dev/null +++ b/rtl/sound_lpf.vhd @@ -0,0 +1,160 @@ +--------------------------------------------------------------------------------- +-- Galaga audio lpf filters based on Burnin' Rubber sources +--------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all, + ieee.std_logic_1164.all, + ieee.std_logic_unsigned.all, + ieee.numeric_std.all; + +entity lpf is +port( + clock : in std_logic; + reset : in std_logic; + + div : in integer; + audio_in : in std_logic_vector(9 downto 0); + + gain_in : in integer; + r1 : in integer; + r2 : in integer; + dt_over_c3 : in integer; + dt_over_c4 : in integer; + r5 : in integer; + + audio_out : out std_logic_vector(15 downto 0) +); +end lpf; + +architecture rtl of lpf is +signal clock_div : std_logic_vector(9 downto 0) := (others =>'0'); + +signal uin : integer range -256 to 255; +signal u3 : integer range -32768 to 32767; +signal u4 : integer range -32768 to 32767; +signal du3 : integer range -32768*4096 to 32767*4096; +signal du4 : integer range -32768*4096 to 32767*4096; + +signal uout : integer range -32768 to 32767; +signal uout_lim : integer range -128 to 127; + +-- integer scale for fixed point +constant scale : integer := 8192; +begin + +-- ----------o------------ +-- u4^ | | | +-- | --- C4 | | R5 | +-- | --- | | | +-- | | C3 | | +-- --| R1 |----o----||---o------|\ | +-- ^ | ------> u3 | \__o--- +-- | | | / ^ +-- |uin | | R2 --|/ | +-- | | | | | uout +-- | | | | +-- ------------o--------------o---------- +-- +-- +-- i1 = (sin+u3)/R1 +-- i2 = -u3/R2 +-- i3 = (u4-u3)/R5 +-- i4 = i2-i1-i3 +-- +-- u3(t+dt) = u3(t) + i3(t)*dt/C3; +-- u4(t+dt) = u4(t) + i4(t)*dt/C4; + +-- uout = u4-u3 + +-- dt = 1/f_ech = 1/23437 +-- dt/C3 = dt/C4 = 4267 + +-- LPF 1 calculations +-- +-- R1 = 150000; +-- R2 = 22000; +-- C3 = 0.01e-6; +-- C4 = 0.01e-6; +-- R5 = 470000; +-- +-- (i3(t)*dt/C3)*scale = du3*scale = ((u4-u3)/470000*4267)*scale +-- = (u4-u3)*11 +-- +-- (i4(t)*dt/C4)*scale = du4*scale = (-u3/22000 -(uin+u3)/150000 -(u4-u3)/470000)*4267*scale +-- = -u3*(233+34-11) - uin*34 - u4*11 +-- = -(u4*11 + u3*256 + uin*34) + +-- LPF 2 calculations +-- +-- R1 = 47000; +-- R2 = 10000; +-- C3 = 0.01e-6; +-- C4 = 0.01e-6; +-- R5 = 150000; +-- +-- (i3(t)*dt/C3)*scale = du3*scale = ((u4-u3)/150000*4267)*scale +-- = (u4-u3)*34 +-- +-- (i4(t)*dt/C4)*scale = du4*scale = (-u3/10000 -(uin+u3)/47000 -(u4-u3)/150000)*4267*scale +-- = -u3*(514+109-34) - uin*109 - u4*34 +-- = -(u4*34 + u3*589 + uin*109) + + +uin <= to_integer(unsigned(audio_in)-128)*gain_in; + +process (clock) +begin + if reset = '1' then + clock_div <= (others => '0'); + else + if rising_edge(clock) then + -- divide 18 MHz clock by 768 = 23.437kHz downsampling + --if clock_div = div-1 then -- "1011111111" then + if clock_div = "1011111111" then + clock_div <= "0000000000"; + else + clock_div <= clock_div + '1'; + end if; + + if clock_div = "0000000000" then + du3 <= u4*109 - u3*109; + du4 <= u4*109 + u3*1432 + uin*1027; + -- du3 <= (u4-u3)*scale*dt_over_c3/r5; + -- du4 <= u3*(scale*dt_over_c4/r2+scale*dt_over_c4/r1-scale*dt_over_c4/r5) + -- + u4*scale*dt_over_c4/r5 + -- + uin*scale*dt_over_c4/r1; + + -- du4 <= -u3*scale*dt_over_c4/r2 + -- -(uin+u3)*scale*dt_over_c4/r1 + -- -(u4-u3)*scale*dt_over_c4/r5; + end if; + + if clock_div = "0000000001" then + u3 <= u3 + du3/scale; + u4 <= u4 - du4/scale; + end if; + + if clock_div = "0000000010" then + uout <= (u4 - u3) / 2; -- adjust output gain + end if; + + -- clamp + if clock_div = "0000000011" then + if uout > 127 then + uout_lim <= 127; + elsif uout < -127 then + uout_lim <= -127; + else + uout_lim <= uout; + end if; + end if; + + if clock_div = "0000000100" then + -- audio_out <= std_logic_vector(to_unsigned(uout,10)); + audio_out <= "0"&std_logic_vector(to_unsigned(uout_lim+128,8)) & "0000000"; + end if; + end if; + end if; +end process; + +end architecture; diff --git a/rtl/sound_machine.vhd b/rtl/sound_machine.vhd new file mode 100644 index 0000000..7640aad --- /dev/null +++ b/rtl/sound_machine.vhd @@ -0,0 +1,145 @@ +--------------------------------------------------------------------------------- +-- Xevious sound machine by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- 3 voices frequency/waveform synthetizer +-- +-- Original hardware done with only one 4 bits sequential adder to realise +-- one 20 bits adder and two 16 bits adder. +-- +-- Too nice and clever to be done another way, just doing it the same way! +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity sound_machine is +port( + clock_18 : in std_logic; + hcnt : in std_logic_vector(5 downto 0); + ena : in std_logic; + cpu_addr : in std_logic_vector(3 downto 0); + cpu_do : in std_logic_vector(3 downto 0); + ram_0_we : in std_logic; + ram_1_we : in std_logic; + audio : out std_logic_vector(9 downto 0) +); +end sound_machine; + +architecture struct of sound_machine is + + signal clock_18n : std_logic; + signal snd_ram_addr : std_logic_vector(3 downto 0); + signal snd_ram_di : std_logic_vector(3 downto 0); + signal snd_ram_0_we : std_logic; + signal snd_ram_1_we : std_logic; + signal snd_ram_0_do : std_logic_vector(3 downto 0); + signal snd_ram_1_do : std_logic_vector(3 downto 0); + + signal snd_seq_addr : std_logic_vector(7 downto 0); + signal snd_seq_do : std_logic_vector(7 downto 0); + + signal snd_samples_addr : std_logic_vector(7 downto 0); + signal snd_samples_do : std_logic_vector(7 downto 0); + + signal sum : std_logic_vector(4 downto 0) := (others => '0'); + signal sum_r : std_logic_vector(4 downto 0) := (others => '0'); + signal sum_3_rr : std_logic := '0'; + + signal samples_ch0 : std_logic_vector(3 downto 0); + signal samples_ch1 : std_logic_vector(3 downto 0); + signal samples_ch2 : std_logic_vector(3 downto 0); + signal volume_ch0 : std_logic_vector(3 downto 0); + signal volume_ch1 : std_logic_vector(3 downto 0); + signal volume_ch2 : std_logic_vector(3 downto 0); + +begin + +clock_18n <= not clock_18; + +snd_seq_addr <= '0' & not ram_0_we & hcnt(5 downto 0); + +snd_ram_addr <= cpu_addr when (ram_0_we = '1' or ram_1_we = '1') else hcnt(5 downto 2); +snd_ram_di <= cpu_do when (ram_0_we = '1' or ram_1_we = '1') else sum_r(3 downto 0); + +snd_ram_0_we <= (not snd_seq_do(1) and ena) or ram_0_we ; +snd_ram_1_we <= ram_1_we; + +sum <= ('0' & snd_ram_0_do) + ('0' & snd_ram_1_do) + ("0000" & sum_r(4)); + +process (clock_18) +begin + if rising_edge(clock_18) and ena = '1' then + if snd_seq_do(3) = '0' then + sum_r <= (others => '0'); + sum_3_rr <= '0'; + elsif snd_seq_do(0) = '0' then + sum_r <= sum; + sum_3_rr <= sum_r(3); + end if ; + + snd_samples_addr <= snd_ram_0_do(2 downto 0) & sum_r(3 downto 0) & sum_3_rr; + + if snd_seq_do(2) = '0' then + if hcnt(5 downto 2) = X"5" then + samples_ch0 <= snd_samples_do(3 downto 0); + volume_ch0 <= snd_ram_1_do; + end if; + if hcnt(5 downto 2) = X"A" then + samples_ch1 <= snd_samples_do(3 downto 0); + volume_ch1 <= snd_ram_1_do; + end if; + if hcnt(5 downto 2) = X"F" then + samples_ch2 <= snd_samples_do(3 downto 0); + volume_ch2 <= snd_ram_1_do; + end if; + end if; + + audio <= ("00" & samples_ch0) * volume_ch0 + + ("00" & samples_ch1) * volume_ch1 + + ("00" & samples_ch2) * volume_ch2; + + end if; +end process; + +-- sound register RAM0 +sound_ram_0 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 4) +port map( + clk => clock_18n, + we => snd_ram_0_we, + addr => snd_ram_addr, + d => snd_ram_di, + q => snd_ram_0_do +); + +-- sound register RAM1 +sound_ram_1 : entity work.gen_ram +generic map( dWidth => 4, aWidth => 4) +port map( + clk => clock_18n, + we => snd_ram_1_we, + addr => snd_ram_addr, + d => snd_ram_di, + q => snd_ram_1_do +); + +-- sound samples ROM +sound_samples : entity work.sound_samples +port map( + clk => clock_18n, + addr => snd_samples_addr, + data => snd_samples_do +); + +-- sound compute sequencer ROM +sound_seq : entity work.sound_seq +port map( + clk => clock_18n, + addr => snd_seq_addr, + data => snd_seq_do +); + +end struct; diff --git a/rtl/xevious.qip b/rtl/xevious.qip new file mode 100644 index 0000000..57a4517 --- /dev/null +++ b/rtl/xevious.qip @@ -0,0 +1,28 @@ +# ============================================================================== +# RTL +# ============================================================================== +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "xevious.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dpram.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "gen_ram.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "gen_video.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sound_machine.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "sound_lpf.vhd"] + +# ============================================================================== +# PROM +# ============================================================================== +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/bg_palette_lsb.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/bg_palette_msb.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/blue.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/green.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/red.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/sound_samples.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/sound_seq.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/sp_palette_lsb.vhd"] +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "prom/sp_palette_msb.vhd"] + +# ============================================================================== +# MODULES +# ============================================================================== +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/cpu-t80/index.qip"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "../modules/cpu-mb88xx/index.qip"] diff --git a/rtl/xevious.vhd b/rtl/xevious.vhd new file mode 100644 index 0000000..ab48ba8 --- /dev/null +++ b/rtl/xevious.vhd @@ -0,0 +1,1702 @@ +--------------------------------------------------------------------------------- +-- Xevious by Dar (darfpga@aol.fr) +-- http://darfpga.blogspot.fr +--------------------------------------------------------------------------------- +-- gen_ram.vhd & io_ps2_keyboard +-------------------------------- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) +-- http://www.syntiac.com/fpga64.html +--------------------------------------------------------------------------------- +-- T80/T80se - Version : 0247 +----------------------------- +-- Z80 compatible microprocessor core +-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) +--------------------------------------------------------------------------------- +-- Educational use only +-- Do not redistribute synthetized file with roms +-- Do not redistribute roms whatever the form +-- Use at your own risk +--------------------------------------------------------------------------------- +-- Version 0.4 -- 02/14/2021 by Slingshot +-- Use mb88 for cs51xx - Super Xevious works +-- +-- Version 0.3 -- 28/02/2017 +-- Fixed cs54xx audio 2 (mb88 JMP instruction fixed) +-- +-- Version 0.2 -- 26/02/2017 -- +-- Replace cs50xx rough emulation by mb88 processor +-- mb88.vhd : tstR and tbit fixed +-- +-- Version 0.1 -- 15/02/2017 -- +-- Add ship explosion with mb88 processor +--------------------------------------------------------------------------------- +-- Features : +-- TV 15KHz mode only (atm) +-- Cocktail mode : todo +-- +-- Sound ok, Ship explode ok with true mb88 processor + +-- Use with MAME roms from xevious.zip +-- +-- Use make_xevious_proms.bat to build vhd file and bin from binaries + +-- IMPORTANT -- +-- Use DE2 Control Panel to load xevious_cpu_gfx_16bits.bin to DE2 SRAM +-- +-- 1) Switch ON DE2 +-- 2) Launch QuartusII and program DE2 with "DE2_USB_API.sof" +-- 3) Launch DE2 control panel +-- a) Menu Open -> Open USB port 0 +-- b) (Test connexion) Tab PS2 & 7-SEG : select '3' on HEX7 and click on SET, digit on DE2 should diplay '3' +-- c) Tab SRAM / frame Sequential Write : check box 'File length'. Click on Write a file to SRAM and choose xevious_cpu_gfx_16bits.bin +-- d) wait for compete write +-- e) (check write) frame Random Access : click Read (Adress 0), rData should display '3E3E' +-- f) VERY IMPORTANT : Menu Open -> Close USB port +-- DO NOT SWITCH OFF DE2 or you will need to reload SRAM +-- 4) go back to QuartusII and program DE2 with "xevious_de2.sof" + +-- Explanation : Xevious make use of large amount of data (prom). All these data could not fit into DE2-35 FPGA. +-- I choose to put all 3 CPUs program, foreground graphics, background graphics and sprite graphics data +-- to external memory. This lead to 68Ko of data. As DE2-35 use a 16bits width SRAM since and DE2 control panel doesn't allow +-- to load 8bits width data all data have been duplicated on both 8bits LSB and 8bits MSB. So xevious_cpu_gfx_16bits.bin +-- is 136Ko. + +-- For other boards one have to consider that the external data are accessed with a 18Mhz multiplexed addressing scheme. So +-- external device have to have a 55ns max access time. Of course big enough FPGA may directly implement these data bank without +-- requiring external device. It is to notice that 55ns will be not so easy to reach with Flash or SDRAM memories. + +-- Xevious Hardware characteristics : +-- +-- 3xZ80 CPU accessing each own program rom and shared ram/devices +-- 16Ko program for CPU1 +-- 8Ko program for CPU2 +-- 4Ko program for CPU3 +-- +-- One char tile map 64x28 (called foreground/fg) +-- 1 colors/64sets among 128 colors +-- 4Ko ram (code + attr/color), 4Ko rom graphics, 8pixels of 1bits/byte +-- Horizontal scrolling (horizontal for TV scan = vertical for upright cabinet) +-- full emulation in vhdl + +-- One background tile map 64x28 (called background/bg) +-- 4 colors/128sets among 128 colors +-- 4Ko ram (code + attr/color), 8Ko rom graphics, 8pixels of 2bits/ 2bytes +-- Horizontal/Vertical scrolling +-- full emulation in vhdl +-- +-- 64 sprites with priorities, flip H/V, 2x size H/V, +-- 8 colors/64sets among 128 colors. +-- 24Ko rom graphics, 4pixels of 3bits / 1.5byte +-- 4 colors/64sets among 128 colors. +-- 8Ko rom graphics, 4pixels of 2bits / byte +-- full emulation in vhdl (improved capabilities : more sprites/scanline) +-- +-- Char/sprites color palette 128 colors among 4096 +-- 12bits 4red/4green/4blue +-- full emulation in vhdl +-- +-- Terrain data +-- 8Ko + 4Ko + 4Ko rom +-- +-- Namco 06XX for 51/54XX control +-- simplified emulation in vhdl +-- +-- Namco 50XX for protection management +-- true mb88 processor ok +-- +-- Namco 51XX for coin/credit management +-- true mb88 processor ok +-- +-- Namco 54XX for sound effects +-- true mb88 processor ok +-- +-- Namco sound waveform and frequency synthetizer +-- full original emulation in vhdl +-- +-- Namco such as address generator, H/V counters and shift registers +-- full emulation in vhdl from what I think they should do. +-- +-- Working ram : 2Kx8bits + 3x2Kx8bits + 2x4Kox8bits (all shared) +-- Sprites ram : 1 scan line delay flip/flop 512x4bits +-- Sound registers ram : 2x16x4bits +-- Sound sequencer rom : 256x4bits (3 sequential 4 bits adders) +-- Sound wavetable rom : 256x4bits 8 waveform of 32 samples of 4bits/level +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity xevious is +port( + clock_18 : in std_logic; + reset : in std_logic; + + dn_addr : in std_logic_vector(16 downto 0); + dn_data : in std_logic_vector(7 downto 0); + dn_wr : in std_logic; + + video_r : out std_logic_vector(3 downto 0); + video_g : out std_logic_vector(3 downto 0); + video_b : out std_logic_vector(3 downto 0); + video_csync : out std_logic; + video_blankn : out std_logic; + video_hs : out std_logic; + video_vs : out std_logic; + video_en : out std_logic; + + blank_h : out std_logic; + blank_v : out std_logic; + + dip_switch_a : in std_logic_vector (7 downto 0); + dip_switch_b : in std_logic_vector (7 downto 0); + + flip : in std_logic; + h_offset : in signed(3 downto 0); + v_offset : in signed(3 downto 0); + test_v : in std_logic_vector (3 downto 0); + + audio : out std_logic_vector(15 downto 0); + +-- ledr : out std_logic_vector(17 downto 0); +-- sw : in std_logic_vector(17 downto 0); + + self_test : in std_logic; + service : in std_logic; + coin1 : in std_logic; + + start1 : in std_logic; + fire1 : in std_logic; + up1 : in std_logic; + down1 : in std_logic; + left1 : in std_logic; + right1 : in std_logic; + + coin2 : in std_logic; + start2 : in std_logic; + up2 : in std_logic; + down2 : in std_logic; + left2 : in std_logic; + right2 : in std_logic; + fire2 : in std_logic; + + pause : in std_logic; + + hs_address : in std_logic_vector(10 downto 0); + hs_data_out : out std_logic_vector(7 downto 0); + hs_data_in : in std_logic_vector(7 downto 0); + hs_write : in std_logic + ); +end xevious; + +architecture struct of xevious is + + signal reset_n: std_logic; + signal clock_18n : std_logic; + + signal slot24 : std_logic_vector(4 downto 0) := (others => '0'); + signal slot : std_logic_vector(2 downto 0) := (others => '0'); + signal hcnt : std_logic_vector(8 downto 0); + signal vcnt : std_logic_vector(8 downto 0); + signal hflip : std_logic_vector(8 downto 0); + signal vflip : std_logic_vector(8 downto 0); + signal vblank : std_logic; + signal bg_mask : std_logic_vector(8 downto 0); + signal ena_vidgen : std_logic; + signal ena_snd_machine : std_logic; + signal ena_sprite : std_logic; + signal ena_sprite_grph0: std_logic; + signal ena_sprite_grph1: std_logic; + signal cpu1_ena : std_logic; + signal cpu2_ena : std_logic; + signal cpu3_ena : std_logic; + + signal cpu1_addr : std_logic_vector(15 downto 0); +-- signal cpu1_di : std_logic_vector( 7 downto 0); + signal cpu1_do : std_logic_vector( 7 downto 0); + signal cpu1_wr_n : std_logic; + signal cpu1_mreq_n : std_logic; + signal cpu1_irq_n : std_logic; + signal cpu1_nmi_n : std_logic; + signal cpu1_m1_n : std_logic; + + signal cpu2_addr : std_logic_vector(15 downto 0); +-- signal cpu2_di : std_logic_vector( 7 downto 0); + signal cpu2_do : std_logic_vector( 7 downto 0); + signal cpu2_wr_n : std_logic; + signal cpu2_mreq_n : std_logic; + signal cpu2_irq_n : std_logic; + signal cpu2_m1_n : std_logic; + + signal cpu3_addr : std_logic_vector(15 downto 0); +-- signal cpu3_di : std_logic_vector( 7 downto 0); + signal cpu3_do : std_logic_vector( 7 downto 0); + signal cpu3_wr_n : std_logic; + signal cpu3_mreq_n : std_logic; + signal cpu3_nmi_n : std_logic; + signal cpu3_m1_n : std_logic; + + signal fg_scan_addr : std_logic_vector(10 downto 0); + signal bg_scan_addr : std_logic_vector(10 downto 0); + + signal bg_offset_h : std_logic_vector(8 downto 0); + signal bg_offset_hs: std_logic_vector(8 downto 0); + signal fg_offset_h : std_logic_vector(8 downto 0); + signal fg_offset_hs: std_logic_vector(8 downto 0); + signal bg_scan_h : std_logic_vector(8 downto 0); + signal fg_scan_h : std_logic_vector(8 downto 0); + signal bg_offset_v : std_logic_vector(8 downto 0); + signal bg_offset_vs: std_logic_vector(8 downto 0); + signal fg_offset_v : std_logic_vector(8 downto 0); + signal fg_offset_vs: std_logic_vector(8 downto 0); + signal bg_scan_v : std_logic_vector(8 downto 0); + signal fg_scan_v : std_logic_vector(8 downto 0); + + signal code_ram_do : std_logic_vector( 7 downto 0); + signal code_ram_we : std_logic; + signal attr_ram_do : std_logic_vector( 7 downto 0); + signal attr_ram_we : std_logic; + signal wram0_do : std_logic_vector( 7 downto 0); + signal wram0_we : std_logic; + signal wram1_do : std_logic_vector( 7 downto 0); + signal wram1_we : std_logic; + signal wram2_do : std_logic_vector( 7 downto 0); + signal wram2_we : std_logic; + signal wram3_do : std_logic_vector( 7 downto 0); + signal wram3_we : std_logic; + signal port_we : std_logic; + signal terrain_we : std_logic; + + signal rom_bus_addr : std_logic_vector(16 downto 0); + signal ram_bus_addr : std_logic_vector(15 downto 0); + signal mux_cpu_do : std_logic_vector( 7 downto 0); + signal cpus_di : std_logic_vector( 7 downto 0); + signal mux_cpu_we : std_logic; + signal mux_cpu_mreq : std_logic; + signal latch_we : std_logic; + signal io_we : std_logic; + + signal cs06XX_control : std_logic_vector( 7 downto 0); + signal cs06XX_do : std_logic_vector( 7 downto 0); + signal cs06XX_di : std_logic_vector( 7 downto 0); + signal cs06XX_nmi_state_next : std_logic; + signal cs06XX_nmi_stretch : std_logic; + signal cs06XX_nmi_cnt : std_logic_vector( 8 downto 0); + + signal cs51xx_rom_addr : std_logic_vector(10 downto 0); + signal cs51xx_rom_do : std_logic_vector( 7 downto 0); + + signal cs51xx_irq_n : std_logic := '1'; + signal cs51xx_ol_port_out: std_logic_vector( 3 downto 0); + signal cs51xx_oh_port_out: std_logic_vector( 3 downto 0); + signal cs51xx_k_port_in : std_logic_vector( 3 downto 0); + signal cs51XX_do : std_logic_vector( 7 downto 0); + signal change_next : std_logic; + + signal cs5Xxx_ena : std_logic; + signal cs5Xxx_rw : std_logic; + + signal cs54xx_ena : std_logic; + signal cs54xx_cnt : std_logic_vector( 1 downto 0); + signal cs54xx_rom_addr : std_logic_vector(10 downto 0); + signal cs54xx_rom_do : std_logic_vector( 7 downto 0); + + signal cs54xx_irq_n : std_logic := '1'; + signal cs54xx_k_port_in : std_logic_vector( 3 downto 0); + signal cs54xx_r0_port_in : std_logic_vector( 3 downto 0); + signal cs54xx_audio_1 : std_logic_vector( 3 downto 0); + signal cs54xx_audio_2 : std_logic_vector( 3 downto 0); + signal cs54xx_audio_3 : std_logic_vector( 3 downto 0); + + signal cs54xx_audio_1_lpf: std_logic_vector(15 downto 0); + signal cs54xx_audio_2_lpf: std_logic_vector(15 downto 0); + signal cs54xx_audio_3_lpf: std_logic_vector(15 downto 0); + + -- signal cs50XX_data_cnt : std_logic_vector( 1 downto 0); + -- signal cs50XX_cmd : std_logic_vector( 7 downto 0); + -- signal cs50XX_cmd_80_do : std_logic_vector( 7 downto 0); + -- signal cs50XX_cmd_E5_do : std_logic_vector( 7 downto 0); + signal cs50XX_do : std_logic_vector( 7 downto 0); + + signal cs50xx_rom_addr : std_logic_vector(10 downto 0); + signal cs50xx_rom_do : std_logic_vector( 7 downto 0); + + signal cs50xx_irq_n : std_logic := '1'; + signal cs50xx_k_port_in : std_logic_vector( 3 downto 0); + signal cs50xx_r0_port_in : std_logic_vector( 3 downto 0); + signal cs50xx_ol_port_out: std_logic_vector( 3 downto 0); + signal cs50xx_oh_port_out: std_logic_vector( 3 downto 0); + + signal dip_switch_do : std_logic_vector (1 downto 0); + + signal bg_code,bg_code_p : std_logic_vector( 7 downto 0); + signal bg_attr,bg_attr_p : std_logic_vector( 7 downto 0); + signal bg_grphx_addr : std_logic_vector(11 downto 0); + signal bg_grphx_0_p : std_logic_vector( 7 downto 0); + signal bg_grphx_0 : std_logic_vector( 7 downto 0); + signal bg_grphx_1_p : std_logic_vector( 7 downto 0); + signal bg_grphx_1 : std_logic_vector( 7 downto 0); + signal bg_bits : std_logic_vector( 1 downto 0); + signal bg_color_delay_0 : std_logic_vector( 7 downto 0); + signal bg_color_delay_1 : std_logic_vector( 7 downto 0); + signal bg_color_delay_2 : std_logic_vector( 7 downto 0); + signal bg_color_delay_3 : std_logic_vector( 7 downto 0); + signal bg_color_delay_4 : std_logic_vector( 7 downto 0); + signal bg_color_delay_5 : std_logic_vector( 7 downto 0); + signal bg_color : std_logic_vector( 5 downto 0); + + signal fg_code,fg_code_p : std_logic_vector( 7 downto 0); + signal fg_attr,fg_attr_p : std_logic_vector( 7 downto 0); + signal fg_grphx_addr : std_logic_vector(11 downto 0); + signal fg_grphx_p : std_logic_vector( 7 downto 0); + signal fg_grphx : std_logic_vector( 7 downto 0); + signal fg_bit : std_logic; + signal fg_color : std_logic_vector( 6 downto 0); + + signal terrain_bs0 : std_logic_vector( 7 downto 0); + signal terrain_bs1 : std_logic_vector( 7 downto 0); + signal terrain_2a_rom_addr : std_logic_vector(11 downto 0); + signal terrain_2a_rom_do : std_logic_vector( 7 downto 0); + signal terrain_2b_rom_addr : std_logic_vector(12 downto 0); + signal terrain_2b_rom_do : std_logic_vector( 7 downto 0); + signal terrain_2c_rom_addr : std_logic_vector(11 downto 0); + signal terrain_2c_rom_do : std_logic_vector( 7 downto 0); + signal terrain_mux_do : std_logic_vector( 2 downto 0); + signal terrain_bb0 : std_logic_vector( 7 downto 0); + signal terrain_bb1 : std_logic_vector( 7 downto 0); + signal terrain_do : std_logic_vector( 7 downto 0); + + signal bg_palette_addr : std_logic_vector( 8 downto 0); + signal bg_palette_lsb_do : std_logic_vector( 7 downto 0); + signal bg_palette_msb_do : std_logic_vector( 7 downto 0); + + signal rgb_palette_addr : std_logic_vector( 7 downto 0); + signal rgb_palette_red_do : std_logic_vector( 7 downto 0); + signal rgb_palette_green_do : std_logic_vector( 7 downto 0); + signal rgb_palette_blue_do : std_logic_vector( 7 downto 0); + + signal sprite_num : std_logic_vector(5 downto 0); + signal sprite_state : std_logic_vector(2 downto 0); + signal sp_line : std_logic_vector(7 downto 0); + signal sp_grphx_cnt : std_logic_vector(1 downto 0); + signal sp_scan_addr : std_logic_vector(6 downto 0); + signal sprite_code : std_logic_vector(7 downto 0); + signal sprite_color : std_logic_vector(7 downto 0); + signal sprite_attr : std_logic_vector(7 downto 0); + signal sp_code_ext : std_logic_vector(8 downto 0); + signal sprite_vcnt : std_logic_vector(4 downto 0); + signal sprite_hcnt : std_logic_vector(4 downto 0); + signal sp_ram_wr_addr : std_logic_vector(8 downto 0); + signal sp_ram_rd_addr : std_logic_vector(8 downto 0); + signal sp_ram_we : std_logic; + signal sp_ram_clr : std_logic; + signal sp_grphx_addr : std_logic_vector(14 downto 0); + signal sp_grphx_0 : std_logic_vector(7 downto 0); + signal sp_grphx_1 : std_logic_vector(3 downto 0); + signal sp_palette_addr : std_logic_vector(8 downto 0); + signal sp_palette_lsb_do: std_logic_vector(7 downto 0); + signal sp_palette_msb_do: std_logic_vector(7 downto 0); + signal sp_color_wr : std_logic_vector(7 downto 0); + signal sp_color_rd : std_logic_vector(6 downto 0); + signal spflip_V ,spflip_H : std_logic; + signal spflip_2V,spflip_2H : std_logic_vector(1 downto 0); + signal spflip_3V,spflip_3H : std_logic_vector(2 downto 0); + signal spflips : std_logic_vector(12 downto 0); + + signal flip_h : std_logic; + + signal sp_ram1_addr : std_logic_vector(8 downto 0); + signal sp_ram1_di : std_logic_vector(6 downto 0); + signal sp_ram1_do : std_logic_vector(6 downto 0); + signal sp_ram1_we : std_logic; + signal sp_ram2_addr : std_logic_vector(8 downto 0); + signal sp_ram2_di : std_logic_vector(6 downto 0); + signal sp_ram2_do : std_logic_vector(6 downto 0); + signal sp_ram2_we : std_logic; + + signal irq1_clr_n : std_logic; + signal irq2_clr_n : std_logic; + signal nmion_n : std_logic; + signal reset_cpu_n : std_logic; + + signal snd_ram_0_we : std_logic; + signal snd_ram_1_we : std_logic; + signal snd_audio : std_logic_vector(9 downto 0); + signal hcnt_r : std_logic_vector(8 downto 0); + + signal rom_bus_addr_o : std_logic_vector(16 downto 0); + signal rom_bus_do : std_logic_vector(7 downto 0); + + signal roms_cs,romta_cs,romtb_cs,romtc_cs,rom50_cs,rom51_cs,rom54_cs : std_logic; + +begin + +rom_bus_addr_o <= rom_bus_addr; + +clock_18n <= not clock_18; +reset_n <= not reset; + +blank_v <= vblank; + +video_en <= ena_vidgen; + +dip_switch_do <= dip_switch_a(to_integer(unsigned(ram_bus_addr(3 downto 0)))) & + dip_switch_b(to_integer(unsigned(ram_bus_addr(3 downto 0)))); + +audio <= ("00" & cs54xx_audio_1_lpf(15 downto 2)) + + ("00" & cs54xx_audio_2_lpf(15 downto 2)) + + ("00" & cs54xx_audio_3_lpf(15 downto 2)) + + ('0' & snd_audio & "00000"); + +-- sp stand for sprite, fg stand for foreground and bg stand for background. +-- make access slots from 18MHz +-- 1 access to any ram or rom for each cpu every 2 pixels +-- 1 access to ram(2 bytes) for foreground every 8 pixels (code and attr/color simultaneous) +-- 1 access to ram(2 bytes) for background every 8 pixels (code and attr/color simultaneous) +-- 8 access to ram(3 bytes) for sprites every 8 pixels (code, attr and color simultaneous) +-- 1 access to fg graphix rom every 8 pixels (1 color bit / pixel) for foreground scan machine +-- 2 access to bg graphix rom every 8 pixels (2 color bits / pixel) for background scan machine +-- 8 access to sp graphix rom every 8 pixels (3 color bits / pixel) for sprite scan machine +-- 2 access to sound ram every 2 pixels for sound machine +-- +-- sprite machine should access ram and rom graphics often enough to allow many sprites on the same scan line. +-- +-- hcnt | 0 | 1 | 2 | 3 | +-- slot | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 1 | 2 | 3 | 4 | 5 | +-- slot24 | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | +-- ram access | cpu1 | cpu2 | cpu3 | fg ram | sp ram | sp ram | cpu1 | cpu2 | cpu3 | bg ram | sp ram | sp ram | +-- rom access | cpu1 | cpu2 | cpu3 | sp gfx0| sp gfx1| fg gfx | cpu1 | cpu2 | cpu3 | sp gfx0| sp gfx1| bg gfx0| +-- sound access | cpu1 | cpu2 | cpu3 | sndram | n.u. | sndram | cpu1 | cpu2 | cpu3 | sndram | n.u. | sndram | + +-- hcnt | 4 | 5 | 6 | 7 | +-- slot | 0 | 1 | 2 | 3 | 4 | 5 | 0 | 1 | 2 | 3 | 4 | 5 | +-- slot24 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | +-- ram access | cpu1 | cpu2 | cpu3 | x | sp ram | sp ram | cpu1 | cpu2 | cpu3 | x | sp ram | sp ram | +-- rom access | cpu1 | cpu2 | cpu3 | sp gfx0| sp gfx1| bg gfx1| cpu1 | cpu2 | cpu3 | sp gfx0| sp gfx1| x | +-- sound access | cpu1 | cpu2 | cpu3 | sndram | n.u. | sndram | cpu1 | cpu2 | cpu3 | sndram | n.u. | sndram | + + +-- remember that enable signals are one slot early + +process (clock_18, hcnt) +begin + if rising_edge(clock_18) then + slot24 <= slot24 + "00001"; + slot <= slot + "001"; + + if slot = "101" then + if (hcnt(2 downto 0) = "111") then slot24 <= (others=>'0'); end if; + if (hcnt(0) = '1' ) then + slot <= "000"; + else + slot <= "011"; -- ensure slot and hcnt well synchronised + end if; + end if; + end if; +end process; + +process (clock_18) +begin + if rising_edge(clock_18) then + ena_vidgen <= '0'; + ena_snd_machine <= '0'; + cpu1_ena <= '0'; + cpu2_ena <= '0'; + cpu3_ena <= '0'; + ena_sprite <= '0'; + ena_sprite_grph0 <= '0'; + ena_sprite_grph1 <= '0'; + cs5Xxx_ena <= '0'; + cs54xx_ena <= '0'; + + if slot = "100" or slot = "001" then ena_vidgen <= '1'; end if; + if slot = "010" or slot = "100" then ena_snd_machine <= '1'; end if; -- sound ram access + if slot = "011" or slot = "100" then ena_sprite <= '1'; end if; -- ram_bus access (wram : sp regs) + if slot = "010" then ena_sprite_grph0 <= '1'; end if; -- rom_bus access (graphx) + if slot = "011" then ena_sprite_grph1 <= '1'; end if; -- rom_bus access (graphx) + + if slot = "101" then cpu1_ena <= '1'; end if; + if slot = "000" then cpu2_ena <= '1'; end if; + if slot = "001" then cpu3_ena <= '1'; end if; + + if slot24 = "00000" then + if cs54xx_cnt = "10" then + cs54xx_cnt <= "00"; + cs54xx_ena <= '1'; -- 1.5MHz/6 (??) + else + cs54xx_cnt <= cs54xx_cnt + 1; + end if; + cs5Xxx_ena <= '1'; -- 1.5MHz/2 + end if; + + end if; +end process; + +hflip <= hcnt when flip = '0' else 367 - hcnt; +vflip <= vcnt when flip = '0' else not vcnt; +bg_mask <= "000000000" when flip = '1' else "000000111"; + +--- SPRITES MACHINE --- +----------------------- +-- Sprite machine makes use of two video memory lines. Read and write process are toggled every other line. +-- +-- At each video line sprite machine has to scan all 64 sprite registers. +-- sprite_num holds which one of the 64 sprite is currently selected. +-- Process consist of : +-- * check from vertical sprite position, vertical sprite size and current video line +-- if sprite belong to current video line, if not go to next sprite +-- * if sprite belong to current video line, collect sprite code, sprite attributes +-- and sprite color (color_set) +-- * then with sprite code collect sprite graphix data from gfx rom, +-- 1.5 bytes for each 4 pixels, sprite is 16 or 32 pixels depending on horizontal size +-- (2 bytes are actulally read but only 1/2 of one of these 2 bytes is use) +-- * for each 1.5 bytes collected serialise 3bits of graphix data +-- * use serialized graphix data together with color_set to build palette rom address and +-- get actual color from palette rom +-- * fill shadow sprite memory with actual sprite color, sprite color has to be written +-- at the right address correponding to the horizontal position of the sprite. In that +-- process, sprites are written one after the others, as sprites may overlapped if the +-- 'new' written color is not transparent color then the 'new' color replace the 'previous' +-- written color. Highest priority sprites are the latest to be written (CPU take care of this point) +-- * go to next sprite until the last one +-- +-- Shadow memory filled during one video line is read and displayed on the next line (CPU take care +-- of this point). After each pixel read, the memory data is cleaned so that the written process will +-- get a 'fresh empty' memory space (unlike the write process which only writes data where sprites are, +-- the read process will read and clean the entire memory line) + +-- sprite registers content +-- | even address | - | odd address | +-- wram1 : 0x8xxx - 0x8FFF : 64 sprites | pos v | - | pos h lsb | +-- wram2 : 0x9xxx - 0x9FFF : 64 sprites |code msb|xxx|flip v|flip h|2xV|2xH| - |xxxxxxx|pos h msb| +-- wram3 : 0xAxxx - 0xAFFF : 64 sprites | code | - |x|ena| color | + +sp_scan_addr <= sprite_num & sprite_state(0); -- toggle odd/even wram address, valid when sprite_state = "000" or "001" +sp_line <= wram1_do + vflip(7 downto 0) + (flip & '0'); + + +process (clock_18, ena_sprite) +begin + if rising_edge(clock_18) then + -- restart start machine at beginning of line, start with the first sprite + if hcnt = std_logic_vector(to_unsigned(128,9)) + flip then + sprite_num <= "000000"; + sprite_state <= "000"; + sp_ram_rd_addr<= "111110000"; + end if; + -- when ena_sprite = '1' wrams are adressed by sp_scan_addr, sprite regs can be collected + if ena_sprite = '1' and sprite_state = "000" then + sprite_code <= wram3_do; + sprite_attr <= wram2_do; +-- sprite_code <= sw(7 downto 0); -- dbg +-- sprite_attr <= sw(15 downto 8); -- dbg + sprite_vcnt <= sp_line(4 downto 0); + -- sprite belong to current horizontal line ? yes go to next state + if sp_line(7 downto 4) = "1111" or -- size V x 1 + (sp_line(7 downto 5) = "111" and wram2_do(1)='1' )then -- size V x 2 +-- (sp_line(7 downto 5) = "111" and sw(9) ='1') then -- dbg + sprite_state <= "001"; + -- sprite doesn't belong to current horizontal line + else + -- if 64th sprite reached stop sprite machine + if sprite_num = "111111" then + sprite_state <= "111"; + -- if not 64th sprite go to next sprite + else + sprite_num <= sprite_num + "000001"; + sprite_state <= "000"; + end if; + end if; + end if; + + -- get sprite color set + -- prepare first shadow ram write position with respect to sprite horizontal position + -- prepare sprite_hcnt to get first grpahics data (2 or 4 differents graphics may be used for one video line) + if ena_sprite = '1' and sprite_state = "001" then + sprite_color <= wram3_do; + -- set sprite horizontal position depending on the flip screen state and sprite size + if flip = '0' then + sp_ram_wr_addr <= wram2_do(0) & wram1_do; -- pos h + else + if sprite_attr(0) = '0' then + sp_ram_wr_addr <= 351 - (wram2_do(0) & wram1_do); -- pos h inverted for size H x 1 + else + sp_ram_wr_addr <= 335 - (wram2_do(0) & wram1_do); -- pos h inverted for size H x 2 + + end if; + end if; + sprite_hcnt <= "00000"; + sprite_state <= "010"; + end if; + + -- when ena_sprite_grph0 ='1' gfx rom are addressed with first data of current sprite_code + -- collect first graphic byte + if ena_sprite_grph0 = '1' and sprite_state = "010" then + sp_grphx_0 <= rom_bus_do; + sprite_state <= "011"; + end if; + + -- when ena_sprite_grph1 ='1' gfx rom are addressed with second data of current sprite_code + -- collect second graphic byte, keep only 4lsb or 4msb depending on sprite attribut and code + if ena_sprite_grph1 = '1' and sprite_state = "011" then + if sprite_attr(7) = '0' then + if sprite_code(7) = '0' then + sp_grphx_1 <= rom_bus_do(3 downto 0); + else + sp_grphx_1 <= rom_bus_do(7 downto 4); + end if; + else + sp_grphx_1 <= X"0"; + end if; + sprite_state <= "100"; + end if; + + -- write process to shadow memory + -- manage sprite_hcnt to get correct graphics rom address + -- loop to state "010" to get graphics data, fill 4 pixels at each loop + -- loop until 16 or 32 pixels written depending on sprite horizontal size + -- when done, go to next sprite + if sprite_state = "100" then + sprite_hcnt <= sprite_hcnt + "00001"; + sp_ram_wr_addr <= sp_ram_wr_addr + "000000001"; + if sprite_hcnt(1 downto 0) = "11" then sprite_state <= "010"; end if; -- go seek for next graphx data + if (sprite_hcnt = "01111" and sprite_attr(0) = '0' ) or -- size H x 1 + (sprite_hcnt = "11111" and sprite_attr(0) = '1' ) then -- size H x 2 + if sprite_num = "111111" then + sprite_state <= "111"; + else + sprite_num <= sprite_num + "000001"; + sprite_state <= "000"; + end if; + end if; + end if; + + -- read process + -- get color from either ram + if slot = "000" or slot = "011" then + if vcnt(0) = '1' then + sp_color_rd <= sp_ram2_do; + else + sp_color_rd <= sp_ram1_do; + end if; + end if; + + -- clear ram after reading + sp_ram_clr <= '0'; + if slot = "001" or slot = "100" then + sp_ram_clr <= '1'; + end if; + + -- next read address + if slot = "010" or slot = "101" then + sp_ram_rd_addr <= sp_ram_rd_addr + "000000001"; + end if; + + end if; +end process; + +-- write to shadow ram if sprite color ready and not transparent +sp_ram_we <= '1' when sprite_state = "100" and sp_color_wr/=X"00" else '0'; +-- toggle read or write address on odd/even line (vertical) number +sp_ram1_addr <= sp_ram_wr_addr when vcnt(0) = '1' else sp_ram_rd_addr; +sp_ram2_addr <= sp_ram_wr_addr when vcnt(0) = '0' else sp_ram_rd_addr; +-- toggle sprite color or clear data to be written on odd/even line (vertical) number +sp_ram1_di <= sp_color_wr(6 downto 0) when vcnt(0) = '1' else "1111111"; +sp_ram2_di <= sp_color_wr(6 downto 0) when vcnt(0) = '0' else "1111111"; +-- toggle sprite write command or clear command on odd/even line (vertical) number +sp_ram1_we <= sp_ram_we when vcnt(0) = '1' else sp_ram_clr; +sp_ram2_we <= sp_ram_we when vcnt(0) = '0' else sp_ram_clr; + +-- build sprite code from both parts +sp_code_ext <= '0'&sprite_code when sprite_attr(7) = '0' else "100"&sprite_code(5 downto 0); +-- prepare flip masks +spflip_H <= sprite_attr(2) xor (flip_h xor flip); spflip_2H <= spflip_H & spflip_H; +spflip_V <= sprite_attr(3); spflip_2V <= spflip_V & spflip_V; +-- finish preparing flip mask from flip attribute (flip v, flip h) and with respect to sprite size (2xV, 2xH) +with sprite_attr(1 downto 0) select +spflips <= "0000000" & spflip_V & spflip_2H & spflip_V & spflip_2V when "00", + "000000" & spflip_H & spflip_V & spflip_2H & spflip_V & spflip_2V when "01", + "00000" & spflip_V & '0' & spflip_V & spflip_2H & spflip_V & spflip_2V when "10", + "00000" & spflip_V & spflip_H & spflip_V & spflip_2H & spflip_V & spflip_2V when others; + +-- set graphics rom address (external) from sprite code, flip mask, sprite size (2xV, 2xH), sprite horizontal tile and vertical line +-- rom data will be latch within sprite machine loop at sprite_state = "010" and sprite_state = "011" +with sprite_attr(1 downto 0) select +sp_grphx_addr <= (sp_code_ext(8 downto 0) & sprite_vcnt(3) & sprite_hcnt(3 downto 2) & sprite_vcnt(2 downto 0) ) xor spflips when "00", + (sp_code_ext(8 downto 1) & sprite_hcnt(4) & sprite_vcnt(3) & sprite_hcnt(3 downto 2) & sprite_vcnt(2 downto 0) ) xor spflips when "01", + (sp_code_ext(8 downto 2) & sprite_vcnt(4) & sp_code_ext(0) & sprite_vcnt(3) & sprite_hcnt(3 downto 2) & sprite_vcnt(2 downto 0) ) xor spflips when "10", + (sp_code_ext(8 downto 2) & sprite_vcnt(4) & sprite_hcnt(4) & sprite_vcnt(3) & sprite_hcnt(3 downto 2) & sprite_vcnt(2 downto 0) ) xor spflips when others; + +-- set palette rom address with sprite color_set and serialized sprite graphics (1.5byte => 3bits) with respect to horizontal flip cmd +sp_palette_addr <= sprite_color(5 downto 0) & + sp_grphx_1(to_integer(unsigned( ((not sprite_hcnt(1 downto 0)) xor spflip_2H )))) & + sp_grphx_0(to_integer(unsigned('1' & ((not sprite_hcnt(1 downto 0)) xor spflip_2H )))) & + sp_grphx_0(to_integer(unsigned('0' & ((not sprite_hcnt(1 downto 0)) xor spflip_2H )))); +-- get sprite_color to be written from color palette or transparent (00) if color_set > 63 +with sprite_color(6) select + sp_color_wr <= sp_palette_msb_do(3 downto 0) & sp_palette_lsb_do(3 downto 0) when '0', X"00" when others; + +--- FOREGROUND/BACKGROUND TILES MACHINE --- +------------------------------------------- + +-- synchronise offsets update out of displayed video +-- to avoid horizontal shrink +process (clock_18, slot24) +begin + if rising_edge(clock_18) and vcnt = "000000000" then + bg_offset_hs <= bg_offset_h + ('1'&X"6C") - flip; + bg_offset_vs <= bg_offset_v + ('0'&X"FE"); + end if; +end process; + +-- set bg/fg scan tile ram address with respect to h/v video counter and h/v offset. +-- for horizontal offset only 6 msb (8-3) are used to get synchronized with 8 pixels addressing process. +-- for background the 3 lsb (2-0) will be use to control a shift register to finish horizontal scrolling. +-- even in original there is no provision to finish horizontal scrolling for foreground. +bg_scan_h <= hflip + 264 + (bg_offset_hs(8 downto 3) & "000") when flip = '1' else hcnt + (bg_offset_hs(8 downto 3) & "000"); +bg_scan_v <= vflip - bg_offset_vs when flip = '1' else vcnt + bg_offset_vs; +bg_scan_addr <= bg_scan_v(7 downto 3) & bg_scan_h(8 downto 3); + +fg_offset_hs <= fg_offset_h + ('1'&X"77"); +fg_offset_vs <= fg_offset_v + ('0'&X"00"); + +fg_scan_h <= hflip - (fg_offset_hs(8 downto 3) & "000") - 16 when flip = '1' else hcnt + (fg_offset_hs(8 downto 3) & "000"); +fg_scan_v <= vflip - fg_offset_vs + 4 when flip = '1' else vcnt + fg_offset_vs; +fg_scan_addr <= fg_scan_v(7 downto 3) & fg_scan_h(8 downto 3); + +process (clock_18, slot24) +begin + if rising_edge(clock_18) then + -- get code, attr (inc. color_set), graphics with respect to slot and rom/ram addressing scheme + -- 1 graphics byte => 8 pixels of 2 colors for foreground (1 color 1 transparent) + -- 2 graphics bytes => 8 pixels of 4 colors for background (one the 4 colors could be transparent depending on bg color_set) + if slot24 = "00011" then + fg_code_p <= code_ram_do; + fg_attr_p <= attr_ram_do; + end if; + if slot24 = "00101" then + fg_grphx_p <= rom_bus_do; + end if; + if slot24 = "01001" then + bg_code_p <= code_ram_do; + bg_attr_p <= attr_ram_do; + end if; + if slot24 = "01011" then + bg_grphx_0_p <= rom_bus_do; + end if; + if slot24 = "10001" then + bg_grphx_1_p <= rom_bus_do; + end if; + -- synchronise graphics and attributes at end of current tile for fg and bg + if slot24 = "10111" then + fg_attr <= fg_attr_p; + bg_attr <= bg_attr_p; + fg_code <= fg_code_p; + bg_code <= bg_code_p; + -- flip h foreground graphics if needed + if fg_attr_p(6) = '0' then + fg_grphx <= fg_grphx_p; + else + for k in 0 to 7 loop + fg_grphx(k) <= fg_grphx_p(7-k); + end loop; + end if; + -- flip h background grphics if needed + if bg_attr_p(6) = '0' then + bg_grphx_0 <= bg_grphx_0_p; + bg_grphx_1 <= bg_grphx_1_p; + else + for k in 0 to 7 loop + bg_grphx_0(k) <= bg_grphx_0_p(7-k); + bg_grphx_1(k) <= bg_grphx_1_p(7-k); + end loop; + end if; + end if; + end if; +end process; + +-- set bg graphics rom address (external) from bg tile code, vertical bg line with respect to vertical flip +-- rom data will be latch within bg/fg machine for slot24 = "01011" and slot24 = "10001" +with bg_attr_p(7) select +bg_grphx_addr <= bg_attr_p(0) & bg_code_p & bg_scan_v(2 downto 0) when '0', + bg_attr_p(0) & bg_code_p & not bg_scan_v(2 downto 0) when others; + +-- set fg graphics rom address (external) from fg tile code, vertical fg line with respect to vertical flip +-- (flip H is used to access rom horizontal flipped character) +-- rom data will be latch within bg/fg machine for slot24 = "00101" +with fg_attr_p(7) select +fg_grphx_addr <= flip_h & fg_code_p & fg_scan_v(2 downto 0) when '0', + flip_h & fg_code_p & not fg_scan_v(2 downto 0) when others; + +-- serialize bg graphics (2 bits / pixel) +bg_bits <= bg_grphx_0(to_integer(unsigned(hcnt(2 downto 0) xor not(flip & flip & flip)))) & + bg_grphx_1(to_integer(unsigned(hcnt(2 downto 0) xor not(flip & flip & flip)))); + +-- serialize fg graphics (1 bit / pixel) +fg_bit <= fg_grphx(to_integer(unsigned(hcnt(2 downto 0) xor not(flip & flip & flip)))); + +-- set bg palette with bg color_set and bg serialized graphic bits +bg_palette_addr <= bg_attr(1 downto 0) & bg_code(7) & bg_attr(5 downto 2) & bg_bits; + +process (clock_18, ena_vidgen) +begin + if rising_edge(clock_18) and ena_vidgen = '1' then + -- 7 pixels length delay line feed with bg color 6bits + bg_color_delay_0 <= bg_color_delay_0(6 downto 0) & bg_palette_lsb_do(0); + bg_color_delay_1 <= bg_color_delay_1(6 downto 0) & bg_palette_lsb_do(1); + bg_color_delay_2 <= bg_color_delay_2(6 downto 0) & bg_palette_lsb_do(2); + bg_color_delay_3 <= bg_color_delay_3(6 downto 0) & bg_palette_lsb_do(3); + bg_color_delay_4 <= bg_color_delay_4(6 downto 0) & bg_palette_msb_do(0); + bg_color_delay_5 <= bg_color_delay_5(6 downto 0) & bg_palette_msb_do(1); + + -- select delay line output to finish bg horizontal scrolling with respect to 3 lsb bits + bg_color(0) <= bg_color_delay_0(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + bg_color(1) <= bg_color_delay_1(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + bg_color(2) <= bg_color_delay_2(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + bg_color(3) <= bg_color_delay_3(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + bg_color(4) <= bg_color_delay_4(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + bg_color(5) <= bg_color_delay_5(to_integer(unsigned(bg_mask xor bg_offset_hs(2 downto 0)))); + + -- set fg color or transparent color with respect to fg serialized graphic bit + if fg_bit = '1' then + fg_color <= "0"&fg_attr(1 downto 0) & fg_attr(5 downto 2); + else + fg_color <= "1111111"; + end if; + + end if; +end process; + +--- VIDEO MUX --- +----------------- + +process (clock_18, ena_vidgen) +begin + if rising_edge(clock_18) and ena_vidgen = '1'then + -- set rbg palette address prior with fg color if < 63 + -- or with sprite color if not transparent + -- otherwise with background color + if fg_color(6)='0' then + rgb_palette_addr <= '0' & fg_color; + else + if sp_color_rd /= "1111111" then + rgb_palette_addr <= "0" & sp_color_rd; + else + rgb_palette_addr <= "00" & bg_color; + end if; + end if; + end if; +end process; + +process (clock_18, ena_vidgen) +begin + -- output rbg color from rbg palette + if rising_edge(clock_18) then + video_r <= rgb_palette_red_do(3 downto 0); + video_g <= rgb_palette_green_do(3 downto 0); + video_b <= rgb_palette_blue_do(3 downto 0); + end if; +end process; + +--- TERRAIN MAP --- +------------------- +-- bs1/bs0 are set by CPU to retrieve to background area tile code and attribut. +-- seems that terrain map is addressed as 2x2 tile area that can be flipped h/v during read + +terrain_2a_rom_addr <= terrain_bs1(6 downto 1) & terrain_bs0(7 downto 2); +terrain_2b_rom_addr <= terrain_bs1(6 downto 1) & terrain_bs0(7 downto 1); + +terrain_mux_do <= terrain_2a_rom_do(2 downto 0) when terrain_bs0(1) = '0' else terrain_2a_rom_do(6 downto 4); + +terrain_2c_rom_addr <= hcnt(0) & terrain_mux_do(0) & -- hcnt(2) is used but any fast enough toggling signal would be ok. + terrain_2b_rom_do & + (terrain_bs1(0) xor terrain_mux_do(1)) & + (terrain_bs0(0) xor terrain_mux_do(2)); + +-- prepare both bb0/bb1 output registers to be read when CPU will required +-- register holds tile code and attribut that will be written to bg wram. +-- bg wram is written coherently with horizontal scrolling out of displayed zone +process (clock_18, ena_vidgen) +begin + if rising_edge(clock_18) then + if hcnt(0) = '0' then + terrain_bb0 <= (terrain_mux_do(1) xor terrain_2c_rom_do(6)) & + (terrain_mux_do(2) xor terrain_2c_rom_do(7)) & + terrain_2c_rom_do(5 downto 0); + else + terrain_bb1 <= terrain_2c_rom_do; + end if; + end if; +end process; + +-- select and return which register is addressed +terrain_do <= terrain_bb0 when ram_bus_addr(0) = '0' else terrain_bb1; + +--- SOUND MACHINE --- +--------------------- + +-- resynchronisation of hcnt with respect to ena_snd_machine +-- there is to be one (and only one) ena_snd_machine during 1 pixel +process (clock_18) +begin + if rising_edge(clock_18) then + hcnt_r <= hcnt; + end if; +end process; + + +sound_machine : entity work.sound_machine +port map( +clock_18 => clock_18, +ena => ena_snd_machine and not pause, +hcnt => hcnt_r(5 downto 0), +cpu_addr => ram_bus_addr(3 downto 0), +cpu_do => mux_cpu_do(3 downto 0), +ram_0_we => snd_ram_0_we, +ram_1_we => snd_ram_1_we, +audio => snd_audio +); + +--- CPUS ------------- +---------------------- + +-- rom address multiplexer +-- should reflect content of xevious_cpu_gfx_8/16bits.bin loaded to external memory +rom_bus_addr <= "000" & cpu1_addr(13 downto 0) when cpu1_ena = '1' else -- 0x0_0000 - 0x0_3FFF : 16K prog cpu1 + "0010" & cpu2_addr(12 downto 0) when cpu2_ena = '1' else -- 0x0_4000 - 0x0_5FFF : 8K prog cpu2 + "00110" & cpu3_addr(11 downto 0) when cpu3_ena = '1' else -- 0x0_6000 - 0x0_6FFF : 4K prog cpu3 + "00111" & fg_grphx_addr when slot24 = "00101" else -- 0x0_7000 - 0x0_7FFF : 4K fg grphx + "01000" & bg_grphx_addr when slot24 = "01011" else -- 0x0_8000 - 0x0_8FFF : 4K bg grphx1 + "01001" & bg_grphx_addr when slot24 = "10001" else -- 0x0_9000 - 0x0_9FFF : 4K bg grphx2 + ('0'&X"A000") + ("00"&sp_grphx_addr) when ena_sprite_grph0 = '1' else -- 0x0_A000 - 0x0_EFFF : 20K sp grphx1 -- ajouter '0_1010_0000_0000_0000' + ('0'&X"F000") + ("0000"&sp_grphx_addr(12 downto 0)) when ena_sprite_grph1 = '1' else -- 0x0_F000 - 0x1_0FFF : 8K sp grphx2 -- ajouter '0_1111_0000_0000_0000' + '0'&X"A5A5"; -- sighting mark + +-- ram address multiplexer +ram_bus_addr <= cpu1_addr when cpu1_ena = '1' else + cpu2_addr when cpu2_ena = '1' else + cpu3_addr when cpu3_ena = '1' else + "00000" & fg_scan_addr when slot24 = "00011" else -- X000-X7FF => B000-B7FF (fg code) / C000-C7FF (fg attr) + "00001" & bg_scan_addr when slot24 = "01001" else -- X800-XFFF => B800-BFFF (bg code) / C800-CFFF (bg attr) + "000001111" & sp_scan_addr; -- X780-X7FF => wram1/2/3 (sprite registers) + +-- cpu data out multiplexer +with slot select +mux_cpu_do <= cpu1_do when "000", + cpu2_do when "001", + cpu3_do when "010", + X"00" when others; + +-- cpu we multiplexer +mux_cpu_we <= (not cpu1_wr_n and cpu1_ena)or + (not cpu2_wr_n and cpu2_ena)or + (not cpu3_wr_n and cpu3_ena); + +-- cpu mreq multiplexer +mux_cpu_mreq <= (not cpu1_mreq_n and cpu1_ena) or + (not cpu2_mreq_n and cpu2_ena) or + (not cpu3_mreq_n and cpu3_ena); + +-- dispatch cpu(s) we to devices +snd_ram_0_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 11) = "01101" and ram_bus_addr(5 downto 4) = "00" else '0'; +snd_ram_1_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 11) = "01101" and ram_bus_addr(5 downto 4) = "01" else '0'; +latch_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 11) = "01101" else '0'; +io_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 11) = "01110" else '0'; +wram0_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 11) = "01111" else '0'; +wram1_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1000" else '0'; +wram2_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1001" else '0'; +wram3_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1010" else '0'; +attr_ram_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1011" else '0'; +code_ram_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1100" else '0'; +port_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1101" else '0'; -- x/y scroll offset, flip general +terrain_we <= '1' when mux_cpu_we = '1' and ram_bus_addr(15 downto 12) = "1111" else '0'; -- bs0/1 + +-- manage irq reset/enable, cpu1 and 2 reset, namco custom chips, misc. lacthes/registers +process (reset, clock_18n, io_we) +begin + if reset='1' then + irq1_clr_n <= '0'; + irq2_clr_n <= '0'; + nmion_n <= '0'; + reset_cpu_n <= '0'; + cpu1_irq_n <= '1'; + cpu2_irq_n <= '1'; + flip_h <= '0'; + cs51xx_irq_n <= '1'; + cs51xx_k_port_in <= X"0"; + cs54xx_irq_n <= '1'; + cs50xx_irq_n <= '1'; + cs50xx_r0_port_in <= X"0"; + cs50xx_k_port_in <= X"0"; + else + if rising_edge(clock_18n) then + if latch_we = '1' and ram_bus_addr(5 downto 4) = "10" then + if ram_bus_addr(2 downto 0) = "000" then irq1_clr_n <= mux_cpu_do(0); end if; + if ram_bus_addr(2 downto 0) = "001" then irq2_clr_n <= mux_cpu_do(0); end if; + if ram_bus_addr(2 downto 0) = "010" then nmion_n <= mux_cpu_do(0); end if; + if ram_bus_addr(2 downto 0) = "011" then reset_cpu_n <= mux_cpu_do(0); end if; + end if; + + if port_we = '1' then + if ram_bus_addr(6 downto 4) = "000" then bg_offset_h <= ram_bus_addr(0) & mux_cpu_do; end if; + if ram_bus_addr(6 downto 4) = "001" then fg_offset_h <= ram_bus_addr(0) & mux_cpu_do; end if; + if ram_bus_addr(6 downto 4) = "010" then bg_offset_v <= ram_bus_addr(0) & mux_cpu_do; end if; + if ram_bus_addr(6 downto 4) = "011" then fg_offset_v <= ram_bus_addr(0) & mux_cpu_do; end if; + if ram_bus_addr(6 downto 4) = "111" then flip_h <= mux_cpu_do(0); end if; + end if; + + if terrain_we = '1' then + if ram_bus_addr(0) = '0' then terrain_bs0 <= mux_cpu_do; end if; + if ram_bus_addr(0) = '1' then terrain_bs1 <= mux_cpu_do; end if; + end if; + + if irq1_clr_n = '0' then + cpu1_irq_n <= '1'; + elsif vcnt = std_logic_vector(to_unsigned(240,9)) and hcnt = std_logic_vector(to_unsigned(128,9)) then cpu1_irq_n <= '0'; + end if; + if irq2_clr_n = '0' then + cpu2_irq_n <= '1'; + elsif vcnt = std_logic_vector(to_unsigned(240,9)) and hcnt = std_logic_vector(to_unsigned(128,9)) then cpu2_irq_n <= '0'; + end if; + + -- write to cs06XX + if io_we = '1' then + -- write to data register (0x7000) + if ram_bus_addr(8) = '0' then + -- write data to device#4 (cs54XX) + if cs06XX_control(3 downto 0) = "1000" then + -- write data for k and r#0 port and launch irq to advice cs50xx + cs54xx_irq_n <= '0'; + cs54xx_k_port_in <= mux_cpu_do(7 downto 4); + cs54xx_r0_port_in <= mux_cpu_do(3 downto 0); + end if; + -- write data to device#1 (cs51XX) + if cs06XX_control(3 downto 0) = "0001" then + cs51xx_irq_n <= '0'; + cs51xx_k_port_in <= mux_cpu_do(3 downto 0); + end if; + -- write data to device#3 (cs50XX) + if cs06XX_control(3 downto 0) = "0100" then + cs50xx_irq_n <= '0'; + cs50xx_k_port_in <= mux_cpu_do(7 downto 4); + cs50xx_r0_port_in <= mux_cpu_do(3 downto 0); + end if; + + end if; + + -- write to control register (0x7100) + -- data(3..0) select custom chip 50xx/51xx/54xx + -- data (4) read/write mode for custom chip (1 = read mode) + if ram_bus_addr(8) = '1' then + cs06XX_control <= mux_cpu_do; + -- start/stop nmi timer (stop if no chip selected) + if mux_cpu_do(7 downto 5) = "000" then + cs06XX_nmi_cnt <= (others => '0'); + cpu1_nmi_n <= '1'; + cs51xx_irq_n <= '1'; + cs50xx_irq_n <= '1'; + cs54xx_irq_n <= '1'; + else + cs06XX_nmi_cnt <= (others => '0'); + cpu1_nmi_n <= '1'; + cs06XX_nmi_stretch <= mux_cpu_do(4); + cs06XX_nmi_state_next <= '1'; + end if; + end if; + end if; + + -- generate periodic nmi when timer is on + if cs06XX_control(7 downto 5) /= "000" then + if cpu1_ena = '1' then -- to get 333ns tick + + if cs06XX_nmi_cnt = 0 then + cs06XX_nmi_cnt <= cs06XX_control(7 downto 5) & "000000"; --64 * cs06XX_control(7 downto 5); + + if cs06XX_nmi_state_next = '1' then + cs5Xxx_rw <= cs06XX_control(4); + end if; + + if cs06XX_nmi_state_next = '1' and cs06XX_nmi_stretch = '0' then + cpu1_nmi_n <= '0'; + else + cpu1_nmi_n <= '1'; + end if; + + if cs06XX_nmi_state_next = '0' or cs06XX_nmi_stretch = '1' then + cs51xx_irq_n <= not (cs06XX_control(0) and cs06XX_nmi_state_next); + cs50xx_irq_n <= not (cs06XX_control(2) and cs06XX_nmi_state_next); + cs54xx_irq_n <= not (cs06XX_control(3) and cs06XX_nmi_state_next); + end if; + + cs06XX_nmi_state_next <= not cs06xx_nmi_state_next; + cs06XX_nmi_stretch <= '0'; + else + cs06XX_nmi_cnt <= cs06XX_nmi_cnt - 1; + end if; + end if; + end if; + + -- manage cs06XX data read (0x7000) + change_next <= '0'; + if mux_cpu_mreq = '1' and mux_cpu_we ='0' and ram_bus_addr(15 downto 11) = "01110" then + if ram_bus_addr(8) = '0' then + change_next <= '1'; + end if; + end if ; + -- cycle data_cnt at each read + if change_next = '1' then + if cs06XX_control(4 downto 0) = "10001" then + cs51xx_irq_n <= '0'; + end if; + if cs06XX_control(4 downto 0) = "10100" then + -- cs50xx (m88 emulation) + cs50xx_irq_n <= '0'; + end if; + end if; + + end if; + end if; +end process; + +cs51XX_do <= cs51xx_oh_port_out & cs51xx_ol_port_out; + +cs50XX_do <= cs50xx_oh_port_out & cs50xx_ol_port_out; + +-- select custom chip reply depending on current control mode for data read request +with cs06XX_control(3 downto 0) select +cs06XX_di <= cs51XX_do when "0001", + cs50XX_do when "0100", +-- cs54XX_do when "1000", + X"00" when others; + +-- select reply depending on data or control read +cs06XX_do <= cs06XX_di when ram_bus_addr(8)= '0' else cs06XX_control; + +-- trigger CPU3 nmi when enable during line 0x40 and 0x60 +process (clock_18, nmion_n) +begin + if nmion_n = '1' then + elsif rising_edge(clock_18) and ena_vidgen = '1' then + if hcnt = "100000000" then + if vcnt = "001000000" or vcnt = "011000000" then cpu3_nmi_n <= '0'; end if; + if vcnt = "001000001" or vcnt = "011000001" then cpu3_nmi_n <= '1'; end if; + end if; + end if; +end process; + +-- multiplex ram/rom/devices data out to cpu di with respect to multiplexed cpu address +-- remenber : rom_bus_addr = ram_bus_addr for any cpu access (see addressing scheme) +with ram_bus_addr(15 downto 11) select +cpus_di <= rom_bus_do when "00000", + rom_bus_do when "00001", + rom_bus_do when "00010", + rom_bus_do when "00011", + rom_bus_do when "00100", + rom_bus_do when "00101", + rom_bus_do when "00110", + rom_bus_do when "00111", + "000000" & dip_switch_do when "01101", + cs06XX_do when "01110", + wram0_do when "01111", + wram1_do when "10000", + wram1_do when "10001", + wram2_do when "10010", + wram2_do when "10011", + wram3_do when "10100", + wram3_do when "10101", + attr_ram_do when "10110", + attr_ram_do when "10111", + code_ram_do when "11000", + code_ram_do when "11001", + terrain_do when "11110", + terrain_do when "11111", + X"00" when others; + +-- video address/sync generator +gen_video : entity work.gen_video +port map( +clk => clock_18, +enable => ena_vidgen, +hcnt => hcnt, +vcnt => vcnt, +hsync => video_hs, +vsync => video_vs, +csync => video_csync, +blank_h => blank_h, +blank_v => vblank, +blankn => video_blankn, +h_offset => h_offset, +v_offset => v_offset +); + +-- microprocessor Z80 - 1 +cpu1 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( + RESET_n => reset_n, + CLK_n => clock_18, + CLKEN => cpu1_ena, + WAIT_n => not pause, + INT_n => cpu1_irq_n, + NMI_n => cpu1_nmi_n, + BUSRQ_n => '1', + M1_n => cpu1_m1_n, + MREQ_n => cpu1_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu1_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu1_addr, + DI => cpus_di, + DO => cpu1_do +); + +-- microprocessor Z80 - 2 +cpu2 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( +-- RESET_n => reset_n, + RESET_n => reset_cpu_n, + CLK_n => clock_18, + CLKEN => cpu2_ena, + WAIT_n => '1', + INT_n => cpu2_irq_n, + NMI_n => '1', --cpu_int_n, + BUSRQ_n => '1', + M1_n => cpu2_m1_n, + MREQ_n => cpu2_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu2_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu2_addr, + DI => cpus_di, + DO => cpu2_do +); + +-- microprocessor Z80 - 3 +cpu3 : entity work.T80se +generic map(Mode => 0, T2Write => 1, IOWait => 1) +port map( +-- RESET_n => reset_n, + RESET_n => reset_cpu_n, + CLK_n => clock_18, + CLKEN => cpu3_ena, + WAIT_n => not pause, + INT_n => '1', + NMI_n => cpu3_nmi_n, + BUSRQ_n => '1', + M1_n => cpu3_m1_n, + MREQ_n => cpu3_mreq_n, + IORQ_n => open, + RD_n => open, + WR_n => cpu3_wr_n, + RFSH_n => open, + HALT_n => open, + BUSAK_n => open, + A => cpu3_addr, + DI => cpus_di, + DO => cpu3_do +); + +-- mb88 - cs51xx (42 pins IC, 1024 bytes rom) +mb88_51xx : entity work.mb88 +port map( + reset_n => reset_cpu_n, --reset_n, + clock => clock_18, + ena => cs5Xxx_ena, + + r0_port_in => not (left1 & down1 & right1 & up1), -- pin 22,23,24,25 + r1_port_in => not (left2 & down2 & right2 & up2), -- pin 26,27,28,29 + r2_port_in => not (start2 & start1 & fire2 & fire1), -- pin 30,31,32,33 + r3_port_in => not (self_test & service & coin2 & coin1), -- pin 34,35,36,37 + r0_port_out => open, + r1_port_out => open, + r2_port_out => open, + r3_port_out => open, + k_port_in => cs5Xxx_rw & cs51xx_k_port_in(2 downto 0), -- pin 38,39,40,41 + ol_port_out => cs51xx_ol_port_out, -- pin 13,14,15,16 + oh_port_out => cs51xx_oh_port_out, -- pin 17,18,19,20 + p_port_out => open, -- pin 9,10,11,12 + + stby_n => '0', + tc_n => not vblank, -- pin 8 + irq_n => cs51xx_irq_n, -- pin 4 + sc_in_n => '0', -- pin 7 + si_n => '0', -- pin 6 + sc_out_n => open, -- pin 7 + so_n => open, -- pin 5 + to_n => open, -- pin 7 + + rom_addr => cs51xx_rom_addr, + rom_data => cs51xx_rom_do +); + +-- cs51xx program ROM +cs51xx_prog : work.dpram generic map (10,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and rom51_cs, + address_a => dn_addr(9 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => cs51xx_rom_addr(9 downto 0), + q_b => cs51xx_rom_do +); + +-- mb88 - cs54xx (28 pins IC, 1024 bytes rom) +mb88_54xx : entity work.mb88 +port map( + reset_n => reset_cpu_n, --reset_n, + clock => clock_18, + ena => cs54xx_ena, + + r0_port_in => cs54xx_r0_port_in, -- pin 12,13,15,16 + r1_port_in => X"0", + r2_port_in => X"0", + r3_port_in => X"0", + r0_port_out => open, + r1_port_out => cs54xx_audio_3, -- pin 17,18,19,20 (resistor divider 100K/22K) + r2_port_out => open, + r3_port_out => open, + k_port_in => cs54xx_k_port_in, -- pin 24,25,26,27 + ol_port_out => cs54xx_audio_1, -- pin 4, 5, 6, 7 (resistor divider 150K/22K) + oh_port_out => cs54xx_audio_2, -- pin 8, 9,10,11 (resistor divider 47K/10K) + p_port_out => open, + + stby_n => '0', + tc_n => '0', + irq_n => cs54xx_irq_n, + sc_in_n => '0', + si_n => '0', + sc_out_n => open, + so_n => open, + to_n => open, + + rom_addr => cs54xx_rom_addr, + rom_data => cs54xx_rom_do +); + +-- cs54xx program ROM +cs54xx_prog : work.dpram generic map (10,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and rom54_cs, + address_a => dn_addr(9 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => cs54xx_rom_addr(9 downto 0), + q_b => cs54xx_rom_do +); + +-- cs54xx audio 1 low pass filter +cs54xx_lpf1 : entity work.lpf +port map( + clock => clock_18, + reset => reset, + div => 768, -- sample rate: 18MHz/768 = 23437.5Hz + audio_in => ("00"&cs54xx_audio_1&"0000"), + gain_in => 2, + r1 => 150000, + r2 => 22000, + dt_over_c3 => 4267, -- 1/23437.5/0.01e-6 + dt_over_c4 => 4267, -- 1/23437.5/0.01e-6 + r5 => 470000, + audio_out => cs54xx_audio_1_lpf +); + +-- cs54xx audio2 low pass filter +cs54xx_lpf2 : entity work.lpf +port map( + clock => clock_18, + reset => reset, + div => 768, -- sample rate: 18MHz/768 = 23437.5Hz + audio_in => ("00"&cs54xx_audio_2&"0000"), + gain_in => 2, + r1 => 47000, + r2 => 10000, + dt_over_c3 => 4267, -- 1/23437.5/0.01e-6 + dt_over_c4 => 4267, -- 1/23437.5/0.01e-6 + r5 => 150000, + audio_out => cs54xx_audio_2_lpf +); + +-- cs54xx audio3 low pass filter +cs54xx_lpf3 : entity work.lpf +port map( + clock => clock_18, + reset => reset, + div => 768, -- sample rate: 18MHz/768 = 23437.5Hz + audio_in => ("00"&cs54xx_audio_3&"0000"), + gain_in => 2, + r1 => 100000, + r2 => 22000, + dt_over_c3 => 42667, -- 1/23437.5/0.001e-6 + dt_over_c4 => 42667, -- 1/23437.5/0.001e-6 + r5 => 220000, + audio_out => cs54xx_audio_3_lpf +); + +-- mb88 - cs50xx (28 pins IC, 2048 bytes rom) +mb88_50xx : entity work.mb88 +port map( + reset_n => reset_cpu_n, --reset_n, + clock => clock_18, + ena => cs5Xxx_ena, -- same clock for 50XX, 51XX, 54XX + + r0_port_in => cs50xx_r0_port_in, -- pin 12,13,15,16 (data in 0-3) + r1_port_in => X"0", + r2_port_in => "000"&cs5Xxx_rw, -- pin 21 (read '1', write '0') + r3_port_in => X"0", + r0_port_out => open, + r1_port_out => open, + r2_port_out => open, + r3_port_out => open, + k_port_in => cs50xx_k_port_in, -- pin 24,25,26,27 (data in 4-7) + ol_port_out => cs50xx_ol_port_out, -- pin 4, 5, 6, 7 (data out 0-3) + oh_port_out => cs50xx_oh_port_out, -- pin 8, 9,10,11 (data out 4-7) + p_port_out => open, + + stby_n => '0', + tc_n => '0', + irq_n => cs50xx_irq_n, + sc_in_n => '0', + si_n => '0', + sc_out_n => open, + so_n => open, + to_n => open, + + rom_addr => cs50xx_rom_addr, + rom_data => cs50xx_rom_do +); + +roms_cs <= '1' when dn_addr(16 downto 12) < "10001" else '0'; +romta_cs <= '1' when dn_addr(16 downto 12) = "10001" else '0'; +romtb_cs <= '1' when dn_addr(16 downto 13) = "1001" else '0'; +romtc_cs <= '1' when dn_addr(16 downto 12) = "10100" else '0'; +rom50_cs <= '1' when dn_addr(16 downto 11) = "101010" else '0'; +rom51_cs <= '1' when dn_addr(16 downto 10) = "1010110" else '0'; +rom54_cs <= '1' when dn_addr(16 downto 10) = "1010111" else '0'; + +sram : work.dpram generic map (17,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and roms_cs, + address_a => dn_addr(16 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => rom_bus_addr_o, + q_b => rom_bus_do +); + + +-- cs50xx program ROM +cs50xx_prog : work.dpram generic map (11,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and rom50_cs, + address_a => dn_addr(10 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => cs50xx_rom_addr(10 downto 0), + q_b => cs50xx_rom_do +); + +-- terrain map 2a ROM +terrain_2a : work.dpram generic map (12,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and romta_cs, + address_a => dn_addr(11 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => terrain_2a_rom_addr, + q_b => terrain_2a_rom_do +); + +-- terrain map 2b ROM +terrain_2b : work.dpram generic map (13,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and romtb_cs, + address_a => dn_addr(12 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => terrain_2b_rom_addr, + q_b => terrain_2b_rom_do +); + +-- terrain map 2c ROM +terrain_2c : work.dpram generic map (12,8) +port map +( + clock_a => clock_18, + wren_a => dn_wr and romtc_cs, + address_a => dn_addr(11 downto 0), + data_a => dn_data, + + clock_b => clock_18n, + address_b => terrain_2c_rom_addr, + q_b => terrain_2c_rom_do +); + +-- foreground/background attr RAM 0xB000-0xBFFF +attr_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_18n, + we => attr_ram_we, + addr => ram_bus_addr(11 downto 0), + d => mux_cpu_do, + q => attr_ram_do +); + +-- foreground/background code RAM 0xC000-0xCFFF +code_ram : entity work.gen_ram +generic map( dWidth => 8, aWidth => 12) +port map( + clk => clock_18n, + we => code_ram_we, + addr => ram_bus_addr(11 downto 0), + d => mux_cpu_do, + q => code_ram_do +); +-- working RAM0 0x7800-0x7FFF +wram0 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_18n, + we => wram0_we, + addr => ram_bus_addr(10 downto 0), + d => mux_cpu_do, + q => wram0_do +); +-- working/sprite register RAM1 0x8000-0x87FF / 0x8800-0x8FFF +wram1 : entity work.dpram +generic map(11,8) +port map( + clock_a => clock_18n, + wren_a => wram1_we, + address_a => ram_bus_addr(10 downto 0), + data_a => mux_cpu_do, + q_a => wram1_do, + + clock_b => clock_18, + wren_b => hs_write, + address_b => hs_address(10 downto 0), + data_b => hs_data_in, + q_b => hs_data_out +); + +-- working/sprite register RAM2 0x9000-0x97FF / 0x9800-0x9FFF +wram2 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_18n, + we => wram2_we, + addr => ram_bus_addr(10 downto 0), + d => mux_cpu_do, + q => wram2_do +); +-- working/sprite register RAM3 0xA000-0xA7FF / 0xA800-0xAFFF +wram3 : entity work.gen_ram +generic map( dWidth => 8, aWidth => 11) +port map( + clk => clock_18n, + we => wram3_we, + addr => ram_bus_addr(10 downto 0), + d => mux_cpu_do, + q => wram3_do +); +-- background palette lsb ROM +bg_palette_lsb : entity work.bg_palette_lsb +port map( + clk => clock_18n, + addr => bg_palette_addr, + data => bg_palette_lsb_do +); +-- background palette msb ROM +bg_palette_msb : entity work.bg_palette_msb +port map( + clk => clock_18n, + addr => bg_palette_addr, + data => bg_palette_msb_do +); + +-- red palette ROM +red_palette : entity work.red +port map( + clk => clock_18n, + addr => rgb_palette_addr, + data => rgb_palette_red_do +); +-- red palette ROM +green_palette : entity work.green +port map( + clk => clock_18n, + addr => rgb_palette_addr, + data => rgb_palette_green_do +); +-- red palette ROM +blue_palette : entity work.blue +port map( + clk => clock_18n, + addr => rgb_palette_addr, + data => rgb_palette_blue_do +); + +-- sprite RAM1 +sp_ram1 : entity work.gen_ram +generic map( dWidth => 7, aWidth => 9) +port map( + clk => clock_18, + we => sp_ram1_we, + addr => sp_ram1_addr, + d => sp_ram1_di, + q => sp_ram1_do +); + +-- sprite RAM2 +sp_ram2 : entity work.gen_ram +generic map( dWidth => 7, aWidth => 9) +port map( + clk => clock_18, + we => sp_ram2_we, + addr => sp_ram2_addr, + d => sp_ram2_di, + q => sp_ram2_do +); + +-- sprite palette lsb ROM +sp_palette_lsb : entity work.sp_palette_lsb +port map( + clk => clock_18n, + addr => sp_palette_addr, + data => sp_palette_lsb_do +); +-- sprite palette msb ROM +sp_palette_msb : entity work.sp_palette_msb +port map( + clk => clock_18n, + addr => sp_palette_addr, + data => sp_palette_msb_do +); + +end struct; diff --git a/target/pocket/core.qip b/target/pocket/core.qip new file mode 100644 index 0000000..aa1025d --- /dev/null +++ b/target/pocket/core.qip @@ -0,0 +1,5 @@ +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_top.v"] +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "core_bridge_cmd.v"] +set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) "core_constraints.sdc"] +set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase.qip"] +set_global_assignment -name SIGNALTAP_FILE [file join $::quartus(qip_path) "stp1.stp"] diff --git a/target/pocket/core_bridge_cmd.v b/target/pocket/core_bridge_cmd.v new file mode 100644 index 0000000..7fc8a70 --- /dev/null +++ b/target/pocket/core_bridge_cmd.v @@ -0,0 +1,445 @@ +// +// bridge host/target command handler +// 2022 Analogue +// + +// mapped to 0xF8xxxxxx on bridge +// the spec is loose enough to allow implementation with either +// block rams and a soft CPU, or simply hard logic with some case statements. +// +// the implementation spec is documented, and depending on your application you +// may want to completely replace this module. this is only one of many +// possible ways to accomplish the host/target command system and data table. +// +// this module should always be clocked by a direct clock input and never a PLL, +// because it should report PLL lock status +// + +module core_bridge_cmd ( + +input wire clk, +output reg reset_n, + +input wire bridge_endian_little, +input wire [31:0] bridge_addr, +input wire bridge_rd, +output reg [31:0] bridge_rd_data, +input wire bridge_wr, +input wire [31:0] bridge_wr_data, + +// all these signals should be synchronous to clk +// add synchronizers if these need to be used in other clock domains +input wire status_boot_done, // assert when PLLs lock and logic is ready +input wire status_setup_done, // assert when core is happy with what's been loaded into it +input wire status_running, // assert when pocket's taken core out of reset and is running + +output reg dataslot_requestread, +output reg [15:0] dataslot_requestread_id, +input wire dataslot_requestread_ack, +input wire dataslot_requestread_ok, + +output reg dataslot_requestwrite, +output reg [15:0] dataslot_requestwrite_id, +input wire dataslot_requestwrite_ack, +input wire dataslot_requestwrite_ok, + +output reg dataslot_allcomplete, + +input wire savestate_supported, +input wire [31:0] savestate_addr, +input wire [31:0] savestate_size, +input wire [31:0] savestate_maxloadsize, + +output reg osnotify_inmenu, + +output reg savestate_start, // core should detect rising edge on this, +input wire savestate_start_ack, // and then assert ack for at least 1 cycle +input wire savestate_start_busy, // assert constantly while in progress after ack +input wire savestate_start_ok, // assert continuously when done, and clear when new process is started +input wire savestate_start_err, // assert continuously on error, and clear when new process is started + +output reg savestate_load, +input wire savestate_load_ack, +input wire savestate_load_busy, +input wire savestate_load_ok, +input wire savestate_load_err, + +input wire [9:0] datatable_addr, +input wire datatable_wren, +input wire [31:0] datatable_data, +output wire [31:0] datatable_q + +); + +// handle endianness + reg [31:0] bridge_wr_data_in; + reg [31:0] bridge_rd_data_out; + + wire endian_little_s; +synch_3 s01(bridge_endian_little, endian_little_s, clk); + +always @(*) begin + bridge_rd_data <= endian_little_s ? { + bridge_rd_data_out[7:0], + bridge_rd_data_out[15:8], + bridge_rd_data_out[23:16], + bridge_rd_data_out[31:24] + } : bridge_rd_data_out; + + bridge_wr_data_in <= endian_little_s ? { + bridge_wr_data[7:0], + bridge_wr_data[15:8], + bridge_wr_data[23:16], + bridge_wr_data[31:24] + } : bridge_wr_data; +end + + +// minimalistic approach here - +// keep the commonly used registers in logic, but data table in BRAM. +// implementation could be changed quite a bit for a more advanced use case + +// host + + reg [31:0] host_0; + reg [31:0] host_4 = 'h20; // host cmd parameter data at 0x20 + reg [31:0] host_8 = 'h40; // host cmd response data at 0x40 + + reg [31:0] host_20; // parameter data + reg [31:0] host_24; + reg [31:0] host_28; + reg [31:0] host_2C; + + reg [31:0] host_40; // response data + reg [31:0] host_44; + reg [31:0] host_48; + reg [31:0] host_4C; + + reg host_cmd_start; + reg [15:0] host_cmd_startval; + reg [15:0] host_cmd; + reg [15:0] host_resultcode; + +localparam [3:0] ST_IDLE = 'd0; +localparam [3:0] ST_PARSE = 'd1; +localparam [3:0] ST_WORK = 'd2; +localparam [3:0] ST_DONE_OK = 'd13; +localparam [3:0] ST_DONE_CODE = 'd14; +localparam [3:0] ST_DONE_ERR = 'd15; + reg [3:0] hstate; + +// target + + reg [31:0] target_0; + reg [31:0] target_4 = 'h20; + reg [31:0] target_8 = 'h40; + + reg [31:0] target_20; // parameter data + reg [31:0] target_24; + reg [31:0] target_28; + reg [31:0] target_2C; + + reg [31:0] target_40; // response data + reg [31:0] target_44; + reg [31:0] target_48; + reg [31:0] target_4C; + +localparam [3:0] TARG_ST_IDLE = 'd0; +localparam [3:0] TARG_ST_READYTORUN = 'd1; +localparam [3:0] TARG_ST_DISPMSG = 'd2; +localparam [3:0] TARG_ST_SLOTREAD = 'd3; +localparam [3:0] TARG_ST_SLOTRELOAD = 'd4; +localparam [3:0] TARG_ST_SLOTWRITE = 'd5; +localparam [3:0] TARG_ST_SLOTFLUSH = 'd6; +localparam [3:0] TARG_ST_WAITRESULT = 'd15; + reg [3:0] tstate; + + reg status_setup_done_1; + reg status_setup_done_queue; + + +initial begin + reset_n <= 0; + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + dataslot_allcomplete <= 0; + savestate_start <= 0; + savestate_load <= 0; + osnotify_inmenu <= 0; + status_setup_done_queue <= 0; +end + +always @(posedge clk) begin + + // detect a rising edge on the input signal + // and flag a queue that will be cleared later + status_setup_done_1 <= status_setup_done; + if(status_setup_done & ~status_setup_done_1) begin + status_setup_done_queue <= 1; + end + + b_datatable_wren <= 0; + b_datatable_addr <= bridge_addr >> 2; + + if(bridge_wr) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: begin + host_0 <= bridge_wr_data_in; // command/status + // check for command + if(bridge_wr_data_in[31:16] == 16'h434D) begin + // host wants us to do a command + host_cmd_startval <= bridge_wr_data_in[15:0]; + host_cmd_start <= 1; + end + end + 8'h20: host_20 <= bridge_wr_data_in; // parameter data regs + 8'h24: host_24 <= bridge_wr_data_in; + 8'h28: host_28 <= bridge_wr_data_in; + 8'h2C: host_2C <= bridge_wr_data_in; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: target_0 <= bridge_wr_data_in; // command/status + 8'h4: target_4 <= bridge_wr_data_in; // parameter data pointer + 8'h8: target_8 <= bridge_wr_data_in; // response data pointer + 8'h40: target_40 <= bridge_wr_data_in; // response data regs + 8'h44: target_44 <= bridge_wr_data_in; + 8'h48: target_48 <= bridge_wr_data_in; + 8'h4C: target_4C <= bridge_wr_data_in; + endcase + end + 32'hF8xx2xxx: begin + b_datatable_wren <= 1; + end + endcase + end + if(bridge_rd) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= host_0; // command/status + 8'h4: bridge_rd_data_out <= host_4; // parameter data pointer + 8'h8: bridge_rd_data_out <= host_8; // response data pointer + 8'h40: bridge_rd_data_out <= host_40; // response data regs + 8'h44: bridge_rd_data_out <= host_44; + 8'h48: bridge_rd_data_out <= host_48; + 8'h4C: bridge_rd_data_out <= host_4C; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= target_0; + 8'h4: bridge_rd_data_out <= target_4; + 8'h8: bridge_rd_data_out <= target_8; + 8'h20: bridge_rd_data_out <= target_20; // parameter data regs + 8'h24: bridge_rd_data_out <= target_24; + 8'h28: bridge_rd_data_out <= target_28; + 8'h2C: bridge_rd_data_out <= target_2C; + endcase + end + 32'hF8xx2xxx: begin + bridge_rd_data_out <= b_datatable_q; + + end + endcase + end + + + + + + // host > target command executer + case(hstate) + ST_IDLE: begin + + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + savestate_start <= 0; + savestate_load <= 0; + + // there is no queueing. pocket will always make sure any outstanding host + // commands are finished before starting another + if(host_cmd_start) begin + host_cmd_start <= 0; + // save the command in case it gets clobbered later + host_cmd <= host_cmd_startval; + hstate <= ST_PARSE; + end + + end + ST_PARSE: begin + // overwrite command semaphore with busy flag + host_0 <= {16'h4255, host_cmd}; + + case(host_cmd) + 16'h0000: begin + // Request Status + host_resultcode <= 1; // default: booting + if(status_boot_done) begin + host_resultcode <= 2; // setup + if(status_setup_done) begin + host_resultcode <= 3; // idle + end else if(status_running) begin + host_resultcode <= 4; // running + end + end + hstate <= ST_DONE_CODE; + end + 16'h0010: begin + // Reset Enter + reset_n <= 0; + hstate <= ST_DONE_OK; + end + 16'h0011: begin + // Reset Exit + reset_n <= 1; + hstate <= ST_DONE_OK; + end + 16'h0080: begin + // Data slot request read + dataslot_allcomplete <= 0; + dataslot_requestread <= 1; + dataslot_requestread_id <= host_20[15:0]; + if(dataslot_requestread_ack) begin + host_resultcode <= 0; + if(!dataslot_requestread_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h0082: begin + // Data slot request write + dataslot_allcomplete <= 0; + dataslot_requestwrite <= 1; + dataslot_requestwrite_id <= host_20[15:0]; + if(dataslot_requestwrite_ack) begin + host_resultcode <= 0; + if(!dataslot_requestwrite_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h008F: begin + // Data slot access all complete + dataslot_allcomplete <= 1; + hstate <= ST_DONE_OK; + end + 16'h00A0: begin + // Savestate: Start/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_size; + + host_resultcode <= 0; + if(savestate_start_busy) host_resultcode <= 1; + if(savestate_start_ok) host_resultcode <= 2; + if(savestate_start_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Start! + savestate_start <= 1; + // stay in this state until ack'd + if(savestate_start_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00A4: begin + // Savestate: Load/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_maxloadsize; + + host_resultcode <= 0; + if(savestate_load_busy) host_resultcode <= 1; + if(savestate_load_ok) host_resultcode <= 2; + if(savestate_load_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Load! + savestate_load <= 1; + // stay in this state until ack'd + if(savestate_load_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00B0: begin + // OS Notify: Menu State + osnotify_inmenu <= host_20[0]; + hstate <= ST_DONE_OK; + end + default: begin + hstate <= ST_DONE_ERR; + end + endcase + end + ST_WORK: begin + hstate <= ST_IDLE; + end + ST_DONE_OK: begin + host_0 <= 32'h4F4B0000; // result code 0 + hstate <= ST_IDLE; + end + ST_DONE_CODE: begin + host_0 <= {16'h4F4B, host_resultcode}; + hstate <= ST_IDLE; + end + ST_DONE_ERR: begin + host_0 <= 32'h4F4BFFFF; // result code FFFF = unknown command + hstate <= ST_IDLE; + end + endcase + + + + + // target > host command executer + case(tstate) + TARG_ST_IDLE: begin + if(status_setup_done_queue) begin + status_setup_done_queue <= 0; + tstate <= TARG_ST_READYTORUN; + end + + end + TARG_ST_READYTORUN: begin + target_0 <= 32'h636D_0140; + tstate <= TARG_ST_WAITRESULT; + end + TARG_ST_WAITRESULT: begin + if(target_0[31:16] == 16'h6F6B) begin + // done + tstate <= TARG_ST_IDLE; + end + + end + endcase + + +end + + wire [31:0] b_datatable_q; + reg [9:0] b_datatable_addr; + reg b_datatable_wren; + +mf_datatable idt ( + .address_a ( datatable_addr ), + .address_b ( b_datatable_addr ), + .clock_a ( clk ), + .clock_b ( clk ), + .data_a ( datatable_data ), + .data_b ( bridge_wr_data_in ), + .wren_a ( datatable_wren ), + .wren_b ( b_datatable_wren ), + .q_a ( datatable_q ), + .q_b ( b_datatable_q ) +); + + +endmodule diff --git a/target/pocket/core_constraints.sdc b/target/pocket/core_constraints.sdc new file mode 100644 index 0000000..198f17b --- /dev/null +++ b/target/pocket/core_constraints.sdc @@ -0,0 +1,14 @@ +# +# user core constraints +# +# put your clock groups in here as well as any net assignments +# + +set_clock_groups -asynchronous \ + -group { bridge_spiclk } \ + -group { clk_74a } \ + -group { clk_74b } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } diff --git a/target/pocket/core_top.v b/target/pocket/core_top.v new file mode 100644 index 0000000..df394b6 --- /dev/null +++ b/target/pocket/core_top.v @@ -0,0 +1,665 @@ +// +// User core top-level +// +// Instantiated by the real top-level: apf_top +// + +`default_nettype none + +module core_top ( + + // + // physical connections + // + + /////////////////////////////////////////////////// + // clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + + input wire clk_74a, // mainclk1 + input wire clk_74b, // mainclk1 + + /////////////////////////////////////////////////// + // cartridge interface + // switches between 3.3v and 5v mechanically + // output enable for multibit translators controlled by pic32 + + // GBA AD[15:8] + inout wire [7:0] cart_tran_bank2, + output wire cart_tran_bank2_dir, + + // GBA AD[7:0] + inout wire [7:0] cart_tran_bank3, + output wire cart_tran_bank3_dir, + + // GBA A[23:16] + inout wire [7:0] cart_tran_bank1, + output wire cart_tran_bank1_dir, + + // GBA [7] PHI# + // GBA [6] WR# + // GBA [5] RD# + // GBA [4] CS1#/CS# + // [3:0] unwired + inout wire [7:4] cart_tran_bank0, + output wire cart_tran_bank0_dir, + + // GBA CS2#/RES# + inout wire cart_tran_pin30, + output wire cart_tran_pin30_dir, + // when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit + // the goal is that when unconfigured, the FPGA weak pullups won't interfere. + // thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators + // and general IO drive this pin. + output wire cart_pin30_pwroff_reset, + + // GBA IRQ/DRQ + inout wire cart_tran_pin31, + output wire cart_tran_pin31_dir, + + // infrared + input wire port_ir_rx, + output wire port_ir_tx, + output wire port_ir_rx_disable, + + // GBA link port + inout wire port_tran_si, + output wire port_tran_si_dir, + inout wire port_tran_so, + output wire port_tran_so_dir, + inout wire port_tran_sck, + output wire port_tran_sck_dir, + inout wire port_tran_sd, + output wire port_tran_sd_dir, + + /////////////////////////////////////////////////// + // cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + + output wire [21:16] cram0_a, + inout wire [15:0] cram0_dq, + input wire cram0_wait, + output wire cram0_clk, + output wire cram0_adv_n, + output wire cram0_cre, + output wire cram0_ce0_n, + output wire cram0_ce1_n, + output wire cram0_oe_n, + output wire cram0_we_n, + output wire cram0_ub_n, + output wire cram0_lb_n, + + output wire [21:16] cram1_a, + inout wire [15:0] cram1_dq, + input wire cram1_wait, + output wire cram1_clk, + output wire cram1_adv_n, + output wire cram1_cre, + output wire cram1_ce0_n, + output wire cram1_ce1_n, + output wire cram1_oe_n, + output wire cram1_we_n, + output wire cram1_ub_n, + output wire cram1_lb_n, + + /////////////////////////////////////////////////// + // sdram, 512mbit 16bit + + output wire [12:0] dram_a, + output wire [1:0] dram_ba, + inout wire [15:0] dram_dq, + output wire [1:0] dram_dqm, + output wire dram_clk, + output wire dram_cke, + output wire dram_ras_n, + output wire dram_cas_n, + output wire dram_we_n, + + /////////////////////////////////////////////////// + // sram, 1mbit 16bit + + output wire [16:0] sram_a, + inout wire [15:0] sram_dq, + output wire sram_oe_n, + output wire sram_we_n, + output wire sram_ub_n, + output wire sram_lb_n, + + /////////////////////////////////////////////////// + // vblank driven by dock for sync in a certain mode + + input wire vblank, + + /////////////////////////////////////////////////// + // i/o to 6515D breakout usb uart + + output wire dbg_tx, + input wire dbg_rx, + + /////////////////////////////////////////////////// + // i/o pads near jtag connector user can solder to + + output wire user1, + input wire user2, + + /////////////////////////////////////////////////// + // RFU internal i2c bus + + inout wire aux_sda, + output wire aux_scl, + + /////////////////////////////////////////////////// + // RFU, do not use + output wire vpll_feed, + + // + // logical connections + // + /////////////////////////////////////////////////// + // video, audio output to scaler + output wire [23:0] video_rgb, + output wire video_rgb_clock, + output wire video_rgb_clock_90, + output wire video_de, + output wire video_skip, + output wire video_vs, + output wire video_hs, + + output wire audio_mclk, + input wire audio_adc, + output wire audio_dac, + output wire audio_lrck, + + /////////////////////////////////////////////////// + // bridge bus connection + // synchronous to clk_74a + output wire bridge_endian_little, + input wire [31:0] bridge_addr, + input wire bridge_rd, + output reg [31:0] bridge_rd_data, + input wire bridge_wr, + input wire [31:0] bridge_wr_data, + + /////////////////////////////////////////////////// + // controller data + // + // key bitmap: + // [0] dpad_up + // [1] dpad_down + // [2] dpad_left + // [3] dpad_right + // [4] face_a + // [5] face_b + // [6] face_x + // [7] face_y + // [8] trig_l1 + // [9] trig_r1 + // [10] trig_l2 + // [11] trig_r2 + // [12] trig_l3 + // [13] trig_r3 + // [14] face_select + // [15] face_start + // joy values - unsigned + // [ 7: 0] lstick_x + // [15: 8] lstick_y + // [23:16] rstick_x + // [31:24] rstick_y + // trigger values - unsigned + // [ 7: 0] ltrig + // [15: 8] rtrig + // + input wire [15:0] cont1_key, + input wire [15:0] cont2_key, + input wire [15:0] cont3_key, + input wire [15:0] cont4_key, + input wire [31:0] cont1_joy, + input wire [31:0] cont2_joy, + input wire [31:0] cont3_joy, + input wire [31:0] cont4_joy, + input wire [15:0] cont1_trig, + input wire [15:0] cont2_trig, + input wire [15:0] cont3_trig, + input wire [15:0] cont4_trig + + ); + + // not using the IR port, so turn off both the LED, and + // disable the receive circuit to save power + assign port_ir_tx = 0; + assign port_ir_rx_disable = 1; + + // bridge endianness + assign bridge_endian_little = 0; + + // cart is unused, so set all level translators accordingly + // directions are 0:IN, 1:OUT + assign cart_tran_bank3 = 8'hzz; + assign cart_tran_bank3_dir = 1'b0; + assign cart_tran_bank2 = 8'hzz; + assign cart_tran_bank2_dir = 1'b0; + assign cart_tran_bank1 = 8'hzz; + assign cart_tran_bank1_dir = 1'b0; + assign cart_tran_bank0 = 4'hf; + assign cart_tran_bank0_dir = 1'b1; + assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself + assign cart_tran_pin30_dir = 1'bz; + assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this + assign cart_tran_pin31 = 1'bz; // input + assign cart_tran_pin31_dir = 1'b0; // input + + // link port is input only + assign port_tran_so = 1'bz; + assign port_tran_so_dir = 1'b0; // SO is output only + assign port_tran_si = 1'bz; + assign port_tran_si_dir = 1'b0; // SI is input only + assign port_tran_sck = 1'bz; + assign port_tran_sck_dir = 1'b0; // clock direction can change + assign port_tran_sd = 1'bz; + assign port_tran_sd_dir = 1'b0; // SD is input and not used + + // tie off the rest of the pins we are not using + assign cram0_a = 'h0; + assign cram0_dq = {16{1'bZ}}; + assign cram0_clk = 0; + assign cram0_adv_n = 1; + assign cram0_cre = 0; + assign cram0_ce0_n = 1; + assign cram0_ce1_n = 1; + assign cram0_oe_n = 1; + assign cram0_we_n = 1; + assign cram0_ub_n = 1; + assign cram0_lb_n = 1; + + assign cram1_a = 'h0; + assign cram1_dq = {16{1'bZ}}; + assign cram1_clk = 0; + assign cram1_adv_n = 1; + assign cram1_cre = 0; + assign cram1_ce0_n = 1; + assign cram1_ce1_n = 1; + assign cram1_oe_n = 1; + assign cram1_we_n = 1; + assign cram1_ub_n = 1; + assign cram1_lb_n = 1; + + assign dram_a = 'h0; + assign dram_ba = 'h0; + assign dram_dq = {16{1'bZ}}; + assign dram_dqm = 'h0; + assign dram_clk = 'h0; + assign dram_cke = 'h0; + assign dram_ras_n = 'h1; + assign dram_cas_n = 'h1; + assign dram_we_n = 'h1; + + assign sram_a = 'h0; + assign sram_dq = {16{1'bZ}}; + assign sram_oe_n = 1; + assign sram_we_n = 1; + assign sram_ub_n = 1; + assign sram_lb_n = 1; + + assign dbg_tx = 1'bZ; + assign user1 = 1'bZ; + assign aux_scl = 1'bZ; + assign vpll_feed = 1'bZ; + + // for bridge write data, we just broadcast it to all bus devices + // for bridge read data, we have to mux it + // add your own devices here + always @(*) begin + casex(bridge_addr) + 32'hF9000000: begin + bridge_rd_data <= bridge_read_buffer; + end + 32'hF8xxxxxx: begin + bridge_rd_data <= cmd_bridge_rd_data; + end + default: begin + bridge_rd_data <= 0; + end + endcase + end + + + // + // host/target command handler + // + wire reset_n; // driven by host commands, can be used as core-wide reset + wire [31:0] cmd_bridge_rd_data; + + // bridge host commands + // synchronous to clk_74a + wire status_boot_done = pll_core_locked; + wire status_setup_done = pll_core_locked; // rising edge triggers a target command + wire status_running = reset_n; // we are running as soon as reset_n goes high + + wire dataslot_requestread; + wire [15:0] dataslot_requestread_id; + wire dataslot_requestread_ack = 1; + wire dataslot_requestread_ok = 1; + + wire dataslot_requestwrite; + wire [15:0] dataslot_requestwrite_id; + wire dataslot_requestwrite_ack = 1; + wire dataslot_requestwrite_ok = 1; + + wire dataslot_allcomplete; + + wire savestate_supported; + wire [31:0] savestate_addr; + wire [31:0] savestate_size; + wire [31:0] savestate_maxloadsize; + + wire savestate_start; + wire savestate_start_ack; + wire savestate_start_busy; + wire savestate_start_ok; + wire savestate_start_err; + + wire savestate_load; + wire savestate_load_ack; + wire savestate_load_busy; + wire savestate_load_ok; + wire savestate_load_err; + + wire osnotify_inmenu; + // bridge target commands + // synchronous to clk_74a + + + // bridge data slot access + + wire [9:0] datatable_addr; + wire datatable_wren; + wire [31:0] datatable_data; + wire [31:0] datatable_q; + + core_bridge_cmd + icb ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( cmd_bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .status_boot_done ( status_boot_done ), + .status_setup_done ( status_setup_done ), + .status_running ( status_running ), + + .dataslot_requestread ( dataslot_requestread ), + .dataslot_requestread_id ( dataslot_requestread_id ), + .dataslot_requestread_ack ( dataslot_requestread_ack ), + .dataslot_requestread_ok ( dataslot_requestread_ok ), + + .dataslot_requestwrite ( dataslot_requestwrite ), + .dataslot_requestwrite_id ( dataslot_requestwrite_id ), + .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), + .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), + + .dataslot_allcomplete ( dataslot_allcomplete ), + + .savestate_supported ( savestate_supported ), + .savestate_addr ( savestate_addr ), + .savestate_size ( savestate_size ), + .savestate_maxloadsize ( savestate_maxloadsize ), + + .savestate_start ( savestate_start ), + .savestate_start_ack ( savestate_start_ack ), + .savestate_start_busy ( savestate_start_busy ), + .savestate_start_ok ( savestate_start_ok ), + .savestate_start_err ( savestate_start_err ), + + .savestate_load ( savestate_load ), + .savestate_load_ack ( savestate_load_ack ), + .savestate_load_busy ( savestate_load_busy ), + .savestate_load_ok ( savestate_load_ok ), + .savestate_load_err ( savestate_load_err ), + + .osnotify_inmenu ( osnotify_inmenu ), + + .datatable_addr ( datatable_addr ), + .datatable_wren ( datatable_wren ), + .datatable_data ( datatable_data ), + .datatable_q ( datatable_q ), + + ); + + //! ------------------------------------------------------------------------------------ + //! @IP Core + //! ------------------------------------------------------------------------------------ + + //! ------------------------------------------------------------------------------------ + //! A/V Signals + //! ------------------------------------------------------------------------------------ + wire xevious_hs, xevious_vs; //! Sync Horizontal/Vertical + wire xevious_hb, xevious_vb; //! Blank Horizontal/Vertical + wire xevious_de; //! Data Enable + wire [11:0] xevious_rgb; //! RGB 444 (12-bit - 4096 Colors) + wire [15:0] xevious_snd; //! Audio + + //! ------------------------------------------------------------------------------------ + //! Data I/O + //! ------------------------------------------------------------------------------------ + wire ioctl_wr; + wire [24:0] ioctl_addr; + wire [7:0] ioctl_dout; + + data_loader # + ( + .ADDRESS_SIZE(16) + ) + data_loader_dut ( + .clk_74a ( clk_74a ), + .clk_memory ( clk_sys ), + + .bridge_wr ( bridge_wr ), + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_wr_data ( bridge_wr_data ), + + .write_en ( ioctl_wr ), + .write_addr ( ioctl_addr ), + .write_data ( ioctl_dout ) + ); + + //! ------------------------------------------------------------------------------------ + //! Gamepad + //! ------------------------------------------------------------------------------------ + wire p1_coin, p1_start; + wire p1_up, p1_down, p1_left, p1_right; + wire p1_btn_a, p1_btn_b, p1_btn_x, p1_btn_y; + + wire p1_fire = p1_btn_a | p1_btn_b; + wire p1_bomb = p1_btn_x | p1_btn_y; + + pocket_gamepad + player1 ( + .iCLK ( clk_sys ), + .iJOY ( cont1_key ), + + .PAD_U ( p1_up ), + .PAD_D ( p1_down ), + .PAD_L ( p1_left ), + .PAD_R ( p1_right ), + + .BTN_A ( p1_btn_a ), + .BTN_B ( p1_btn_b ), + .BTN_X ( p1_btn_x ), + .BTN_Y ( p1_btn_y ), + + .BTN_SE ( p1_coin ), + .BTN_ST ( p1_start ), + ); + + //! ------------------------------------------------------------------------------------ + //! Dip Switches + //! ------------------------------------------------------------------------------------ + reg [31:0] bridge_read_buffer; + + reg [31:0] def_dsw = 16'h0000; + wire [31:0] def_dsw_s; + + always @(posedge clk_74a) begin + if(bridge_wr && bridge_addr == 32'hF9000000) begin + def_dsw <= bridge_wr_data; + end + if(bridge_rd) begin + casex(bridge_addr) + 32'hF9000000: begin + bridge_read_buffer <= def_dsw; + end + endcase + end + end + + synch_3 #(.WIDTH(32)) s2(def_dsw, def_dsw_s, clk_sys); + + wire [7:0] DSWA = ~def_dsw_s[7:0]; + wire [7:0] DSWB = ~def_dsw_s[15:8]; + + //! ------------------------------------------------------------------------------------ + //! Core + //! ------------------------------------------------------------------------------------ + xevious + xevious_dut ( + .clock_18 ( clk_sys ), + .reset ( ~reset_n ), + + .dn_addr ( ioctl_addr[16:0] ), + .dn_data ( ioctl_dout ), + .dn_wr ( ioctl_wr ), + + .video_r ( xevious_rgb[11:8] ), + .video_g ( xevious_rgb[7:4] ), + .video_b ( xevious_rgb[3:0] ), + + .video_blankn ( xevious_de ), + .video_hs ( xevious_hs ), + .video_vs ( xevious_vs ), + .blank_h ( xevious_hb ), + .blank_v ( xevious_vb ), + + .dip_switch_a ( DSWA ), + .dip_switch_b ( {DSWB[7:5], 1'b0, DSWB[3:1], ~p1_bomb} ), + + .flip ( ), + + .h_offset ( ), + .v_offset ( ), + + .test_v ( ), + + .audio ( xevious_snd ), + + .self_test ( ), + .service ( ), + + .coin1 ( p1_coin ), + .start1 ( p1_start ), + + .fire1 ( p1_fire ), + .up1 ( p1_up ), + .down1 ( p1_down ), + .left1 ( p1_left ), + .right1 ( p1_right ), + + .coin2 ( ), + .start2 ( ), + + .fire2 ( ), + .up2 ( ), + .down2 ( ), + .left2 ( ), + .right2 ( ), + + .pause ( ), + + .hs_address ( ), + .hs_data_out ( ), + .hs_data_in ( ), + .hs_write ( ) + ); + + //! ------------------------------------------------------------------------------------ + //! Video + //! ------------------------------------------------------------------------------------ + reg [23:0] video_rgb_reg; // R[23:16] G[15:8] B[7:0] + reg video_hs_reg; + reg video_vs_reg; + reg video_de_reg; + + reg [11:0] video_rgb_prev; // R[11:8] G[7:4] B[3:0] + reg video_hs_prev; + reg video_vs_prev; + reg video_de_prev; + + assign video_rgb = video_rgb_reg; + assign video_hs = video_hs_reg; + assign video_vs = video_vs_reg; + assign video_de = video_de_reg; + + assign video_rgb_clock = clk_vid; + assign video_rgb_clock_90 = clk_vid_90deg; + + always @(posedge clk_vid) begin + video_de_reg <= 0; + video_rgb_reg <= 24'h0; + + if (video_de_prev) begin + video_de_reg <= 1; + video_rgb_reg <= {video_rgb_prev[11:8], 4'h0, video_rgb_prev[7:4], 4'h0, video_rgb_prev[3:0], 4'h0}; + end + + // Set HSync and VSync to be high for a single cycle on the rising edge of the HSync and VSync coming out of the core + video_hs_reg <= ~video_hs_prev && xevious_hs; + video_vs_reg <= ~video_vs_prev && xevious_vs; + video_hs_prev <= xevious_hs; + video_vs_prev <= xevious_vs; + video_de_prev <= xevious_de; + video_rgb_prev <= xevious_rgb; + end + + //! ------------------------------------------------------------------------------------ + //! Audio + //! ------------------------------------------------------------------------------------ + wire [15:0] audio_left = {1'b0, xevious_snd[15:1]}; + wire [15:0] audio_right = audio_left; + pocket_i2s + i2s ( + .iCLK_74 ( clk_74a ), + + .AUDIO_L ( audio_left ), + .AUDIO_R ( audio_right ), + + .I2S_MCLK ( audio_mclk ), + .I2S_DAC ( audio_dac ), + .I2S_LRCK ( audio_lrck ) + ); + + //! ------------------------------------------------------------------------------------ + //! Clocks + //! ------------------------------------------------------------------------------------ + wire clk_sys; //! Core System Clock @ 18Mhz + wire clk_vid; //! Video: 288x224 @ 6Mhz + wire clk_vid_90deg; //! Video: 90º Phase Shift + wire pll_core_locked; + + mf_pllbase + mp1 ( + .refclk ( clk_74a ), + .rst ( 0 ), + + .outclk_0 ( clk_sys ), + .outclk_1 ( clk_vid ), + .outclk_2 ( clk_vid_90deg ), + + .locked ( pll_core_locked ) + ); + //! @end + +endmodule diff --git a/target/pocket/mf_pllbase.ppf b/target/pocket/mf_pllbase.ppf new file mode 100644 index 0000000..22e69f8 --- /dev/null +++ b/target/pocket/mf_pllbase.ppf @@ -0,0 +1,15 @@ + + + + + + + + + + + diff --git a/target/pocket/mf_pllbase.qip b/target/pocket/mf_pllbase.qip new file mode 100644 index 0000000..cd23213 --- /dev/null +++ b/target/pocket/mf_pllbase.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_VERSION "18.0" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "mf_pllbase" -name MISC_FILE [file join $::quartus(qip_path) "mf_pllbase.cmp"] +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mw==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mw==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTguMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NDg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTk4::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::Ni4w::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NDg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTk0::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MjAzNDU=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::Ni4w::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::NDg=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NTk0::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::NTgxMQ==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::LTQ1LjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MjI1LjAgZGVn::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::NTY0Mg==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MjcwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::Ni4wMDAwMDAgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::Ni4wMDAwMDAgTUh6::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::NDE2NjcgcHM=::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MjQsMjQsNiw1LGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsOSw5LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDI3LDI3LDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDI3LDI3LDE0LDQscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwyLDIwLDEwMDAwLDMyNC4wIE1IeiwxLGdjbGssZ2xiLGZiXzEscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] +set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] + +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "18.0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" diff --git a/target/pocket/mf_pllbase.v b/target/pocket/mf_pllbase.v new file mode 100644 index 0000000..e5e73a7 --- /dev/null +++ b/target/pocket/mf_pllbase.v @@ -0,0 +1,257 @@ +// megafunction wizard: %PLL Intel FPGA IP v18.0% +// GENERATION: XML +// mf_pllbase.v + +// Generated using ACDS version 18.0 614 + +`timescale 1 ps / 1 ps +module mf_pllbase ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire locked // locked.export + ); + + mf_pllbase_0002 mf_pllbase_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : mf_pllbase.vo +// RELATED_FILES: mf_pllbase.v, mf_pllbase_0002.v diff --git a/target/pocket/mf_pllbase/mf_pllbase_0002.qip b/target/pocket/mf_pllbase/mf_pllbase_0002.qip new file mode 100644 index 0000000..52c225f --- /dev/null +++ b/target/pocket/mf_pllbase/mf_pllbase_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" + +set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/target/pocket/mf_pllbase/mf_pllbase_0002.v b/target/pocket/mf_pllbase/mf_pllbase_0002.v new file mode 100644 index 0000000..1995518 --- /dev/null +++ b/target/pocket/mf_pllbase/mf_pllbase_0002.v @@ -0,0 +1,93 @@ +`timescale 1ns/10ps +module mf_pllbase_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("normal"), + .number_of_clocks(3), + .output_clock_frequency0("18.000000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("6.000000 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("6.000000 MHz"), + .phase_shift2("41667 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/target/pocket/pin_ddio_clk.ppf b/target/pocket/pin_ddio_clk.ppf new file mode 100644 index 0000000..7f6c108 --- /dev/null +++ b/target/pocket/pin_ddio_clk.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/target/pocket/pin_ddio_clk.qip b/target/pocket/pin_ddio_clk.qip new file mode 100644 index 0000000..a79964f --- /dev/null +++ b/target/pocket/pin_ddio_clk.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pin_ddio_clk.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk_inst.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pin_ddio_clk.ppf"] diff --git a/target/pocket/pin_ddio_clk.v b/target/pocket/pin_ddio_clk.v new file mode 100644 index 0000000..5885794 --- /dev/null +++ b/target/pocket/pin_ddio_clk.v @@ -0,0 +1,108 @@ +// megafunction wizard: %ALTDDIO_OUT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTDDIO_OUT + +// ============================================================ +// File Name: pin_ddio_clk.v +// Megafunction Name(s): +// ALTDDIO_OUT +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.1.1 Build 646 04/11/2019 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2019 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and any partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details, at +//https://fpgasoftware.intel.com/eula. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pin_ddio_clk ( + datain_h, + datain_l, + outclock, + dataout); + + input [0:0] datain_h; + input [0:0] datain_l; + input outclock; + output [0:0] dataout; + + wire [0:0] sub_wire0; + wire [0:0] dataout = sub_wire0[0:0]; + + altddio_out ALTDDIO_OUT_component ( + .datain_h (datain_h), + .datain_l (datain_l), + .outclock (outclock), + .dataout (sub_wire0), + .aclr (1'b0), + .aset (1'b0), + .oe (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + defparam + ALTDDIO_OUT_component.extend_oe_disable = "OFF", + ALTDDIO_OUT_component.intended_device_family = "Cyclone V", + ALTDDIO_OUT_component.invert_output = "OFF", + ALTDDIO_OUT_component.lpm_hint = "UNUSED", + ALTDDIO_OUT_component.lpm_type = "altddio_out", + ALTDDIO_OUT_component.oe_reg = "UNREGISTERED", + ALTDDIO_OUT_component.power_up_high = "OFF", + ALTDDIO_OUT_component.width = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +// Retrieval info: CONSTANT: WIDTH NUMERIC "1" +// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]" +// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0 +// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]" +// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0 +// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]" +// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0 +// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock" +// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_inst.v TRUE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.cmp FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pin_ddio_clk.ppf TRUE FALSE +// Retrieval info: LIB_FILE: altera_mf diff --git a/target/pocket/stp1.stp b/target/pocket/stp1.stp new file mode 100644 index 0000000..bc21612 --- /dev/null +++ b/target/pocket/stp1.stp @@ -0,0 +1,1135 @@ + + + + + + + + + + + + + + +
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