OpenHW Group

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Assembly 9 14 20 1 Updated Feb 17, 2020
cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RISCY from PULP-Platform

riscv riscv32imfc

SystemVerilog 126 320 81 (3 issues need help) 6 Updated Feb 17, 2020
openhwgroup.org

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…

HTML EPL-2.0 4 1 5 1 Updated Feb 14, 2020
core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

4 8 11 0 Updated Feb 14, 2020
core-v-cores

CORE-V Family of RISC-V Cores

0 1 0 0 Updated Feb 11, 2020
osdforum.org

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

HTML EPL-2.0 2 0 0 0 Updated Nov 12, 2019
riscv_vm

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

Shell Apache-2.0 1 3 8 0 Updated Oct 8, 2019

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