From f9354dc9fee27934520ec3a9d8db1ab7167c4072 Mon Sep 17 00:00:00 2001 From: Stefan Mach Date: Wed, 20 Dec 2017 19:20:05 +0100 Subject: [PATCH] :bug: Stall pipeline in write-after-write loads Fixes #8 by making sure that newer instructions cannot be overtaken by an in-flight stalled load. --- riscv_controller.sv | 6 +++++- riscv_id_stage.sv | 4 ++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/riscv_controller.sv b/riscv_controller.sv index 779c4128a..65b06a139 100644 --- a/riscv_controller.sv +++ b/riscv_controller.sv @@ -118,8 +118,12 @@ module riscv_controller input logic [DBG_SETS_W-1:0] dbg_settings_i, output logic dbg_trap_o, + // Regfile target + input logic [5:0] regfile_alu_waddr_id_i, // currently decoded target address + // Forwarding signals from regfile input logic regfile_we_ex_i, // FW: write enable from EX stage + input logic [5:0] regfile_waddr_ex_i, // FW: write address from EX stage input logic regfile_we_wb_i, // FW: write enable from WB stage input logic regfile_alu_we_fw_i, // FW: ALU/MUL write enable from EX stage @@ -726,7 +730,7 @@ module riscv_controller ( (data_req_ex_i == 1'b1) && (regfile_we_ex_i == 1'b1) || (wb_ready_i == 1'b0) && (regfile_we_wb_i == 1'b1) ) && - ( (reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1) ) + ( (reg_d_ex_is_reg_a_i == 1'b1) || (reg_d_ex_is_reg_b_i == 1'b1) || (reg_d_ex_is_reg_c_i == 1'b1) || (regfile_waddr_ex_i == regfile_alu_waddr_id_i)) ) begin deassert_we_o = 1'b1; diff --git a/riscv_id_stage.sv b/riscv_id_stage.sv index ee06014f5..f29108183 100644 --- a/riscv_id_stage.sv +++ b/riscv_id_stage.sv @@ -1169,8 +1169,12 @@ module riscv_id_stage .dbg_settings_i ( dbg_settings_i ), .dbg_trap_o ( dbg_trap_o ), + // Write targets from ID + .regfile_alu_waddr_id_i ( regfile_alu_waddr_id ), + // Forwarding signals from regfile .regfile_we_ex_i ( regfile_we_ex_o ), + .regfile_waddr_ex_i ( regfile_waddr_ex_o ), .regfile_we_wb_i ( regfile_we_wb_i ), // regfile port 2