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[Bug report] miss illegal instruction exception when rd of MULHU is the same as rs1 or rs2 #885
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Hi @JeanRochCoulon , this issue is more than 7 months old and has not received any updates. It looks like an important issue to me. Please assign the right person to move this along. |
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@AyoubJalali You should meet this case doing the ISACOV verification. Does ISACOV cover this case ? |
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@JeanRochCoulon It should be, but i'll look at it |
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@chenc6 hello, so I run a test with : so could you providing me with the source file .S, to try to reproduce the problem if it still. |
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@AyoubJalali Sorry, I couldn't find the .S file, but it should be easy to reproduce because the issue is only related to one instruction. Maybe you can change the instruction from |
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@chenc6 I don't thing also it's a problem, because i covered all possible combinations between all multiplications instructions with all values of rx registers : So could the problem be in spike version, so which version you use for this test ? |
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@AyoubJalali the version of spike may be the problem. |
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@chenc6 and @AyoubJalali The RISCV specification tells us that "rdh cannot be the same as rs1 or rs2". It is not clear to me if an illegal instruction must be triggered or not. Does the RISCV or the CVA6 ISA specification tells us what is the behaviour in that case? |
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@JeanRochCoulon @chenc6 @AyoubJalali The CVA6 behaves correctly. There is no reason to raise an illegal instruction exception on The specification only warns the software developer when using |
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@JeanRochCoulon I don't think the cva6 should raised an illegal instruction it's just a recommendation if you want the lower & upper part of the multiplication you should use a sequence mentioned in the RISCV spec. |
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Understood. Thank for your investigation. |


Hi,
The RISC-V ISA Volume I, 20190608, page 43 mentions: "MULH[[S]U] rdh, rs1, rs2; MUL

rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2)"
Our testcase shows cva6 will not throw illegal instruction exception in this case while spike does at line 84.

The testcase mem file, rtl trace log, and spike trace log are attached.
missexcept.zip
Thank you
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