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[Bug report] miss illegal instruction exception when rd of MULHU is the same as rs1 or rs2 #885

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@chenc6

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Hi,

The RISC-V ISA Volume I, 20190608, page 43 mentions: "MULH[[S]U] rdh, rs1, rs2; MUL
rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or rs2)"
image

Our testcase shows cva6 will not throw illegal instruction exception in this case while spike does at line 84.
image

The testcase mem file, rtl trace log, and spike trace log are attached.
missexcept.zip

Thank you

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Component:RTLFor issues in the RTL (e.g. for files in the rtl directory)Status:NewNewly created issue, nobody has looked at it yet.Type:BugFor bugs in the RTL, Documentation, Verification environment or Tool and Build system

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