Our co-simulation framework found the decoder has an incorrect behavior when execute a dret with non-zero rd field.
According to the Debug Specification Version 1.0.0:
To resume execution, the debug module sets a flag which causes the hart to execute a dret. dret is an instruction that only has meaning while in Debug Mode and not executing from the Program Buffer. Its recommended encoding is 0x7b200073.
When modified instr[11:7] to 5'b00001. cva6 treats this invalid dret as normal dret as well. No exception occurred. The implementation is missing a check for this field.
In the following test case, there is an invalid dret at 0x8000019c, whose rd field is 1, cva6 execute it as normal instruction, while spike throws an excaption.
Our co-simulation framework found the decoder has an incorrect behavior when execute a
dretwith non-zero rd field.According to the Debug Specification Version 1.0.0:
When modified instr[11:7] to 5'b00001. cva6 treats this invalid
dretas normaldretas well. No exception occurred. The implementation is missing a check for this field.In the following test case, there is an invalid
dretat 0x8000019c, whose rd field is 1, cva6 execute it as normal instruction, while spike throws an excaption.We believe is the debug mode checking reset the correct signal:
cva6/core/decoder.sv
Lines 134 to 135 in 909d85a
cva6-3.zip
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