Description
Our co-simulation framework found the decoder has an incorrect behavior when execute a fence.i/fence with non-zero rd field.
As discussed before 719, fence/fence.i should ignores immediate, rs1, rd field. We found the patch 724 does not fix this bug.
The checking after the patch still throws an exception for non-zero rd and rs1:
Lines 238 to 239 in 909d85a
According to the The RISC-V Instruction Set Manual Volume I: Unprivileged ISA:
FENCE: The unused fields in the FENCE instructions—rs1 and rd—are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.
FENCE.I: The unused fields in the FENCE.I instruction, imm[11:0], rs1, and rd, are reserved for finer-grain fences in future extensions. For forward compatibility, base implementations shall ignore these fields, and standard software shall zero these fields.
In the following test case, there is a valid fence.i at 0x80000194, whose rd field is 1, and a fence with non-zero rd at 0x80000198. cva6 still throws exceptions for them.
[cva6] Exception @ 68600, PC: 0000000080000194, Cause: Illegal Instruction,
[cva6] tval: 000000000000120f
[spike] core 0: 0x0000000080000194 (0x0000120f) fence.i
[error] PC SIM 0000000080000194, DUT 0000000080000004
[error] INSN SIM 0000120f, DUT 34202f73
[CJ] Commit Failed
@LuminaDCIX helps reproduce the problem