Skip to content

Commit

Permalink
8310948: Fix ignored-qualifiers warning in Hotspot
Browse files Browse the repository at this point in the history
Reviewed-by: kbarrett, dholmes
  • Loading branch information
djelinski committed Jul 3, 2023
1 parent 2c29705 commit 055b4b4
Show file tree
Hide file tree
Showing 74 changed files with 223 additions and 223 deletions.
4 changes: 2 additions & 2 deletions make/hotspot/lib/CompileJvm.gmk
Original file line number Diff line number Diff line change
Expand Up @@ -84,11 +84,11 @@ CFLAGS_VM_VERSION := \
# Disabled warnings

DISABLED_WARNINGS_gcc := array-bounds comment delete-non-virtual-dtor \
empty-body ignored-qualifiers implicit-fallthrough int-in-bool-context \
empty-body implicit-fallthrough int-in-bool-context \
maybe-uninitialized missing-field-initializers parentheses \
shift-negative-value unknown-pragmas

DISABLED_WARNINGS_clang := ignored-qualifiers sometimes-uninitialized \
DISABLED_WARNINGS_clang := sometimes-uninitialized \
missing-braces delete-non-abstract-non-virtual-dtor unknown-pragmas

ifneq ($(DEBUG_LEVEL), release)
Expand Down
16 changes: 8 additions & 8 deletions src/hotspot/cpu/aarch64/aarch64.ad
Original file line number Diff line number Diff line change
Expand Up @@ -2285,7 +2285,7 @@ int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf)

//=============================================================================

const bool Matcher::match_rule_supported(int opcode) {
bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode))
return false;

Expand Down Expand Up @@ -2320,7 +2320,7 @@ const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length)
}

// Vector calling convention not yet implemented.
const bool Matcher::supports_vector_calling_convention(void) {
bool Matcher::supports_vector_calling_convention(void) {
return false;
}

Expand All @@ -2340,7 +2340,7 @@ bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
}

// Vector width in bytes.
const int Matcher::vector_width_in_bytes(BasicType bt) {
int Matcher::vector_width_in_bytes(BasicType bt) {
// The MaxVectorSize should have been set by detecting SVE max vector register size.
int size = MIN2((UseSVE > 0) ? 256 : 16, (int)MaxVectorSize);
// Minimum 2 values in vector
Expand All @@ -2351,11 +2351,11 @@ const int Matcher::vector_width_in_bytes(BasicType bt) {
}

// Limits on vector size (number of elements) loaded into vector.
const int Matcher::max_vector_size(const BasicType bt) {
int Matcher::max_vector_size(const BasicType bt) {
return vector_width_in_bytes(bt)/type2aelembytes(bt);
}

const int Matcher::min_vector_size(const BasicType bt) {
int Matcher::min_vector_size(const BasicType bt) {
int max_size = max_vector_size(bt);
// Limit the min vector size to 8 bytes.
int size = 8 / type2aelembytes(bt);
Expand All @@ -2370,17 +2370,17 @@ const int Matcher::min_vector_size(const BasicType bt) {
return MIN2(size, max_size);
}

const int Matcher::superword_max_vector_size(const BasicType bt) {
int Matcher::superword_max_vector_size(const BasicType bt) {
return Matcher::max_vector_size(bt);
}

// Actual max scalable vector register length.
const int Matcher::scalable_vector_reg_size(const BasicType bt) {
int Matcher::scalable_vector_reg_size(const BasicType bt) {
return Matcher::max_vector_size(bt);
}

// Vector ideal reg.
const uint Matcher::vector_ideal_reg(int len) {
uint Matcher::vector_ideal_reg(int len) {
if (UseSVE > 0 && 16 < len && len <= 256) {
return Op_VecA;
}
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/aarch64/aarch64_vector.ad
Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ source %{
}
}

const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
if (UseSVE == 0) {
// These operations are not profitable to be vectorized on NEON, because no direct
// NEON instructions support them. But the match rule support for them is profitable for
Expand All @@ -148,7 +148,7 @@ source %{

// Identify extra cases that we might want to provide match rules for vector nodes and
// other intrinsics guarded with vector length (vlen) and element type (bt).
const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
if (!match_rule_supported(opcode)) {
return false;
}
Expand Down Expand Up @@ -232,7 +232,7 @@ source %{
return vector_size_supported(bt, vlen);
}

const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
// Only SVE supports masked operations.
if (UseSVE == 0) {
return false;
Expand Down Expand Up @@ -271,7 +271,7 @@ source %{
return match_rule_supported_vector(opcode, vlen, bt);
}

const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
// Only SVE has partial vector operations
if (UseSVE == 0) {
return false;
Expand Down
8 changes: 4 additions & 4 deletions src/hotspot/cpu/aarch64/aarch64_vector_ad.m4
Original file line number Diff line number Diff line change
Expand Up @@ -115,7 +115,7 @@ source %{
}
}

const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
if (UseSVE == 0) {
// These operations are not profitable to be vectorized on NEON, because no direct
// NEON instructions support them. But the match rule support for them is profitable for
Expand All @@ -138,7 +138,7 @@ source %{

// Identify extra cases that we might want to provide match rules for vector nodes and
// other intrinsics guarded with vector length (vlen) and element type (bt).
const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
if (!match_rule_supported(opcode)) {
return false;
}
Expand Down Expand Up @@ -222,7 +222,7 @@ source %{
return vector_size_supported(bt, vlen);
}

const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
// Only SVE supports masked operations.
if (UseSVE == 0) {
return false;
Expand Down Expand Up @@ -261,7 +261,7 @@ source %{
return match_rule_supported_vector(opcode, vlen, bt);
}

const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
// Only SVE has partial vector operations
if (UseSVE == 0) {
return false;
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/aarch64/assembler_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -4211,7 +4211,7 @@ Instruction_aarch64::~Instruction_aarch64() {
#undef starti

// Invert a condition
inline const Assembler::Condition operator~(const Assembler::Condition cond) {
inline Assembler::Condition operator~(const Assembler::Condition cond) {
return Assembler::Condition(int(cond) ^ 1);
}

Expand Down
6 changes: 3 additions & 3 deletions src/hotspot/cpu/aarch64/matcher_aarch64.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@
// Whether this platform implements the scalable vector feature
static const bool implements_scalable_vector = true;

static const bool supports_scalable_vector() {
static bool supports_scalable_vector() {
return UseSVE > 0;
}

Expand Down Expand Up @@ -144,12 +144,12 @@
}

// Does the CPU supports vector unsigned comparison instructions?
static const bool supports_vector_comparison_unsigned(int vlen, BasicType bt) {
static constexpr bool supports_vector_comparison_unsigned(int vlen, BasicType bt) {
return true;
}

// Some microarchitectures have mask registers used on vectors
static const bool has_predicated_vectors(void) {
static bool has_predicated_vectors(void) {
return UseSVE > 0;
}

Expand Down
24 changes: 12 additions & 12 deletions src/hotspot/cpu/arm/arm.ad
Original file line number Diff line number Diff line change
Expand Up @@ -947,7 +947,7 @@ int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
return offset;
}

const bool Matcher::match_rule_supported(int opcode) {
bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode))
return false;

Expand Down Expand Up @@ -1002,11 +1002,11 @@ const bool Matcher::match_rule_supported(int opcode) {
return true; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
return match_rule_supported_vector(opcode, vlen, bt);
}

const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {

// TODO
// identify extra cases that we might want to provide match rules for
Expand All @@ -1017,11 +1017,11 @@ const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType
return ret_value; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
return false;
}

const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
return false;
}

Expand All @@ -1034,7 +1034,7 @@ const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length)
}

// Vector calling convention not yet implemented.
const bool Matcher::supports_vector_calling_convention(void) {
bool Matcher::supports_vector_calling_convention(void) {
return false;
}

Expand All @@ -1044,16 +1044,16 @@ OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
}

// Vector width in bytes
const int Matcher::vector_width_in_bytes(BasicType bt) {
int Matcher::vector_width_in_bytes(BasicType bt) {
return MaxVectorSize;
}

const int Matcher::scalable_vector_reg_size(const BasicType bt) {
int Matcher::scalable_vector_reg_size(const BasicType bt) {
return -1;
}

// Vector ideal reg corresponding to specified size in bytes
const uint Matcher::vector_ideal_reg(int size) {
uint Matcher::vector_ideal_reg(int size) {
assert(MaxVectorSize >= size, "");
switch(size) {
case 8: return Op_VecD;
Expand All @@ -1064,17 +1064,17 @@ const uint Matcher::vector_ideal_reg(int size) {
}

// Limits on vector size (number of elements) loaded into vector.
const int Matcher::max_vector_size(const BasicType bt) {
int Matcher::max_vector_size(const BasicType bt) {
assert(is_java_primitive(bt), "only primitive type vectors");
return vector_width_in_bytes(bt)/type2aelembytes(bt);
}

const int Matcher::min_vector_size(const BasicType bt) {
int Matcher::min_vector_size(const BasicType bt) {
assert(is_java_primitive(bt), "only primitive type vectors");
return 8/type2aelembytes(bt);
}

const int Matcher::superword_max_vector_size(const BasicType bt) {
int Matcher::superword_max_vector_size(const BasicType bt) {
return Matcher::max_vector_size(bt);
}

Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/arm/assembler_arm.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -245,7 +245,7 @@ class Address {

bool uses(Register reg) const { return _base == reg || _index == reg; }

const relocInfo::relocType rtype() { return _rspec.type(); }
relocInfo::relocType rtype() { return _rspec.type(); }
const RelocationHolder& rspec() { return _rspec; }

// Convert the raw encoding form into the form expected by the
Expand Down
4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/matcher_ppc.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@

// PPC implementation uses VSX load/store instructions (if
// SuperwordUseVSX) which support 4 byte but not arbitrary alignment
static const bool misaligned_vectors_ok() {
static constexpr bool misaligned_vectors_ok() {
return false;
}

Expand Down Expand Up @@ -155,7 +155,7 @@

// true means we have fast l2f conversion
// false means that conversion is done by runtime call
static const bool convL2FSupported(void) {
static bool convL2FSupported(void) {
// fcfids can do the conversion (>= Power7).
// fcfid + frsp showed rounding problem when result should be 0x3f800001.
return VM_Version::has_fcfids();
Expand Down
24 changes: 12 additions & 12 deletions src/hotspot/cpu/ppc/ppc.ad
Original file line number Diff line number Diff line change
Expand Up @@ -2100,7 +2100,7 @@ static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
return 0;
}

const bool Matcher::match_rule_supported(int opcode) {
bool Matcher::match_rule_supported(int opcode) {
if (!has_match_rule(opcode)) {
return false; // no match rule present
}
Expand Down Expand Up @@ -2170,22 +2170,22 @@ const bool Matcher::match_rule_supported(int opcode) {
return true; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_superword(int opcode, int vlen, BasicType bt) {
return match_rule_supported_vector(opcode, vlen, bt);
}

const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
return false;
}
return true; // Per default match rules are supported.
}

const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
return false;
}

const bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
bool Matcher::vector_needs_partial_operations(Node* node, const TypeVect* vt) {
return false;
}

Expand All @@ -2198,7 +2198,7 @@ const TypeVectMask* Matcher::predicate_reg_type(const Type* elemTy, int length)
}

// Vector calling convention not yet implemented.
const bool Matcher::supports_vector_calling_convention(void) {
bool Matcher::supports_vector_calling_convention(void) {
return false;
}

Expand All @@ -2208,7 +2208,7 @@ OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
}

// Vector width in bytes.
const int Matcher::vector_width_in_bytes(BasicType bt) {
int Matcher::vector_width_in_bytes(BasicType bt) {
if (SuperwordUseVSX) {
assert(MaxVectorSize == 16, "");
return 16;
Expand All @@ -2219,7 +2219,7 @@ const int Matcher::vector_width_in_bytes(BasicType bt) {
}

// Vector ideal reg.
const uint Matcher::vector_ideal_reg(int size) {
uint Matcher::vector_ideal_reg(int size) {
if (SuperwordUseVSX) {
assert(MaxVectorSize == 16 && size == 16, "");
return Op_VecX;
Expand All @@ -2230,20 +2230,20 @@ const uint Matcher::vector_ideal_reg(int size) {
}

// Limits on vector size (number of elements) loaded into vector.
const int Matcher::max_vector_size(const BasicType bt) {
int Matcher::max_vector_size(const BasicType bt) {
assert(is_java_primitive(bt), "only primitive type vectors");
return vector_width_in_bytes(bt)/type2aelembytes(bt);
}

const int Matcher::min_vector_size(const BasicType bt) {
int Matcher::min_vector_size(const BasicType bt) {
return max_vector_size(bt); // Same as max.
}

const int Matcher::superword_max_vector_size(const BasicType bt) {
int Matcher::superword_max_vector_size(const BasicType bt) {
return Matcher::max_vector_size(bt);
}

const int Matcher::scalable_vector_reg_size(const BasicType bt) {
int Matcher::scalable_vector_reg_size(const BasicType bt) {
return -1;
}

Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/assembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -270,7 +270,7 @@ class Address {
return _mode != literal && base() == reg;
}

const address target() const {
address target() const {
assert_is_literal();
return _literal._target;
}
Expand Down

1 comment on commit 055b4b4

@openjdk-notifier
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please sign in to comment.