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8286182: [BACKOUT] x86: Handle integral division overflow during parsing
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8287035: [BACKOUT] PPC64: Handle integral division overflow during parsing

Reviewed-by: mdoerr, thartmann
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@merykitty @TheRealMDoerr
merykitty authored and TheRealMDoerr committed May 19, 2022
1 parent 7b19226 commit 079312c
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Showing 25 changed files with 490 additions and 701 deletions.
4 changes: 0 additions & 4 deletions src/hotspot/cpu/aarch64/aarch64.ad
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Expand Up @@ -2790,10 +2790,6 @@ bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack,
return false;
}

bool Parse::do_one_bytecode_targeted() {
return false;
}

#define MOV_VOLATILE(REG, BASE, INDEX, SCALE, DISP, SCRATCH, INSN) \
C2_MacroAssembler _masm(&cbuf); \
{ \
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4 changes: 0 additions & 4 deletions src/hotspot/cpu/arm/arm.ad
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Expand Up @@ -1159,10 +1159,6 @@ bool maybe_far_call(const MachCallNode *n) {
return !MacroAssembler::_reachable_from_cache(n->as_MachCall()->entry_point());
}

bool Parse::do_one_bytecode_targeted() {
return false;
}

%}

//----------ENCODING BLOCK-----------------------------------------------------
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47 changes: 0 additions & 47 deletions src/hotspot/cpu/ppc/parse_ppc.cpp
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This file was deleted.

142 changes: 122 additions & 20 deletions src/hotspot/cpu/ppc/ppc.ad
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Expand Up @@ -8848,10 +8848,26 @@ instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
ins_pipe(pipe_class_default);
%}

// Integer Division, but not min_jint / -1
instruct noOvfDivI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
match(Set dst (NoOvfDivI src1 src2));
ins_cost(3*DEFAULT_COST);
// Integer Division with Immediate -1: Negate.
instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
match(Set dst (DivI src1 src2));
ins_cost(DEFAULT_COST);

format %{ "NEG $dst, $src1 \t// /-1" %}
size(4);
ins_encode %{
__ neg($dst$$Register, $src1$$Register);
%}
ins_pipe(pipe_class_default);
%}

// Integer Division with constant, but not -1.
// We should be able to improve this by checking the type of src2.
// It might well be that src2 is known to be positive.
instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
match(Set dst (DivI src1 src2));
predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
ins_cost(2*DEFAULT_COST);

format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
size(4);
Expand All @@ -8861,10 +8877,56 @@ instruct noOvfDivI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
ins_pipe(pipe_class_default);
%}

// Long Division, but not min_jlong / -1
instruct noOvfDivL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
match(Set dst (NoOvfDivL src1 src2));
ins_cost(3*DEFAULT_COST);
instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
effect(USE_DEF dst, USE src1, USE crx);
predicate(false);

ins_variable_size_depending_on_alignment(true);

format %{ "CMOVE $dst, neg($src1), $crx" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(8);
ins_encode %{
Label done;
__ bne($crx$$CondRegister, done);
__ neg($dst$$Register, $src1$$Register);
__ bind(done);
%}
ins_pipe(pipe_class_default);
%}

// Integer Division with Registers not containing constants.
instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
match(Set dst (DivI src1 src2));
ins_cost(10*DEFAULT_COST);

expand %{
immI16 imm %{ (int)-1 %}
flagsReg tmp1;
cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
%}
%}

// Long Division with Immediate -1: Negate.
instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
match(Set dst (DivL src1 src2));
ins_cost(DEFAULT_COST);

format %{ "NEG $dst, $src1 \t// /-1, long" %}
size(4);
ins_encode %{
__ neg($dst$$Register, $src1$$Register);
%}
ins_pipe(pipe_class_default);
%}

// Long Division with constant, but not -1.
instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
match(Set dst (DivL src1 src2));
predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
ins_cost(2*DEFAULT_COST);

format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
size(4);
Expand All @@ -8874,31 +8936,71 @@ instruct noOvfDivL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
ins_pipe(pipe_class_default);
%}

instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
effect(USE_DEF dst, USE src1, USE crx);
predicate(false);

ins_variable_size_depending_on_alignment(true);

format %{ "CMOVE $dst, neg($src1), $crx" %}
// Worst case is branch + move + stop, no stop without scheduler.
size(8);
ins_encode %{
Label done;
__ bne($crx$$CondRegister, done);
__ neg($dst$$Register, $src1$$Register);
__ bind(done);
%}
ins_pipe(pipe_class_default);
%}

// Long Division with Registers not containing constants.
instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
match(Set dst (DivL src1 src2));
ins_cost(10*DEFAULT_COST);

expand %{
immL16 imm %{ (int)-1 %}
flagsReg tmp1;
cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
%}
%}

// Integer Remainder with registers.
instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
match(Set dst (NoOvfModI src1 src2));
ins_cost(5*DEFAULT_COST);
match(Set dst (ModI src1 src2));
ins_cost(10*DEFAULT_COST);

expand %{
iRegIdst tmp1;
immI16 imm %{ (int)-1 %}
flagsReg tmp1;
iRegIdst tmp2;
noOvfDivI_reg_reg(tmp1, src1, src2);
mulI_reg_reg(tmp2, src2, tmp1);
subI_reg_reg(dst, src1, tmp2);
iRegIdst tmp3;
cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
%}
%}

// Long Remainder with registers
instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
match(Set dst (NoOvfModL src1 src2));
ins_cost(5*DEFAULT_COST);
match(Set dst (ModL src1 src2));
ins_cost(10*DEFAULT_COST);

expand %{
iRegLdst tmp1;
immL16 imm %{ (int)-1 %}
flagsReg tmp1;
iRegLdst tmp2;
noOvfDivL_reg_reg(tmp1, src1, src2);
mulL_reg_reg(tmp2, src2, tmp1);
subL_reg_reg(dst, src1, tmp2);
iRegLdst tmp3;
cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
%}
%}

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4 changes: 0 additions & 4 deletions src/hotspot/cpu/riscv/riscv.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -2039,10 +2039,6 @@ bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack,
return clone_base_plus_offset_address(m, mstack, address_visited);
}

bool Parse::do_one_bytecode_targeted() {
return false;
}

%}


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4 changes: 0 additions & 4 deletions src/hotspot/cpu/s390/s390.ad
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Expand Up @@ -1693,10 +1693,6 @@ bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack,
return clone_base_plus_offset_address(m, mstack, address_visited);
}

bool Parse::do_one_bytecode_targeted() {
return false;
}

%} // source

//----------ENCODING BLOCK-----------------------------------------------------
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14 changes: 0 additions & 14 deletions src/hotspot/cpu/x86/assembler_x86.cpp
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Expand Up @@ -2235,13 +2235,6 @@ void Assembler::idivl(Register src) {
emit_int16((unsigned char)0xF7, (0xF8 | encode));
}

void Assembler::idivl(Address src) {
InstructionMark im(this);
prefix(src);
emit_int8((unsigned char)0xF7);
emit_operand(as_Register(7), src);
}

void Assembler::divl(Register src) { // Unsigned
int encode = prefix_and_encode(src->encoding());
emit_int16((unsigned char)0xF7, (0xF0 | encode));
Expand Down Expand Up @@ -12331,13 +12324,6 @@ void Assembler::idivq(Register src) {
emit_int16((unsigned char)0xF7, (0xF8 | encode));
}

void Assembler::idivq(Address src) {
InstructionMark im(this);
prefixq(src);
emit_int8((unsigned char)0xF7);
emit_operand(as_Register(7), src);
}

void Assembler::divq(Register src) {
int encode = prefixq_and_encode(src->encoding());
emit_int16((unsigned char)0xF7, (0xF0 | encode));
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10 changes: 5 additions & 5 deletions src/hotspot/cpu/x86/assembler_x86.hpp
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Expand Up @@ -1198,9 +1198,6 @@ class Assembler : public AbstractAssembler {
void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);

void divl(Register src);
void divq(Register src);

// Divide Scalar Double-Precision Floating-Point Values
void divsd(XMMRegister dst, Address src);
void divsd(XMMRegister dst, XMMRegister src);
Expand Down Expand Up @@ -1369,9 +1366,12 @@ class Assembler : public AbstractAssembler {
void hlt();

void idivl(Register src);
void idivl(Address src);
void divl(Register src); // Unsigned division

#ifdef _LP64
void idivq(Register src);
void idivq(Address src);
void divq(Register src); // Unsigned division
#endif

void imull(Register src);
void imull(Register dst, Register src);
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47 changes: 0 additions & 47 deletions src/hotspot/cpu/x86/parse_x86.cpp
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This file was deleted.

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