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8263354: Accumulated C2 code cleanups
Reviewed-by: thartmann, redestad
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Pengfei Li committed Mar 12, 2021
1 parent aa33443 commit 0bbe064c1bb4537d5068cfa3c45f16cb34836f2e
Showing 4 changed files with 44 additions and 62 deletions.
@@ -1,6 +1,6 @@
//
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, Arm Limited. All rights reserved.
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@@ -52,7 +52,6 @@ operand vmemA_immLOffset4()
interface(CONST_INTER);
%}


operand vmemA_indOffI4(iRegP reg, vmemA_immIOffset4 off)
%{
constraint(ALLOC_IN_RC(ptr_reg));
@@ -88,7 +87,6 @@ source_hpp %{
%}

source %{

static inline BasicType vector_element_basic_type(const MachNode* n) {
const TypeVect* vt = n->bottom_type()->is_vect();
return vt->element_basic_type();
@@ -210,16 +208,13 @@ source %{
return true;
}
}

%}

definitions %{
int_def SVE_COST (200, 200);
%}




// All SVE instructions

// vector load/store
@@ -253,7 +248,6 @@ instruct storeV(vReg src, vmemA mem) %{
ins_pipe(pipe_slow);
%}


// vector abs

instruct vabsB(vReg dst, vReg src) %{
@@ -1120,7 +1114,6 @@ instruct replicateL(vReg dst, iRegL src) %{
ins_pipe(pipe_slow);
%}


instruct replicateB_imm8(vReg dst, immI8 con) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 16);
match(Set dst (ReplicateB con));
@@ -1165,7 +1158,6 @@ instruct replicateL_imm8(vReg dst, immL8_shift8 con) %{
ins_pipe(pipe_slow);
%}


instruct replicateF(vReg dst, vRegF src) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= 4);
match(Set dst (ReplicateF src));
@@ -1708,4 +1700,3 @@ instruct vsubD(vReg dst, vReg src1, vReg src2) %{
%}
ins_pipe(pipe_slow);
%}

@@ -1,6 +1,6 @@
//
// Copyright (c) 2020, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, Arm Limited. All rights reserved.
// Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
// Copyright (c) 2020, 2021, Arm Limited. All rights reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
@@ -29,6 +29,8 @@ dnl

// AArch64 SVE Architecture Description File


// 4 bit signed offset -- for predicated load/store
dnl
dnl OPERAND_VMEMORYA_IMMEDIATE_OFFSET($1, $2, $3 )
dnl OPERAND_VMEMORYA_IMMEDIATE_OFFSET(imm_type_abbr, imm_type, imm_len)
@@ -42,9 +44,7 @@ operand vmemA_imm$1Offset$3()
op_cost(0);
format %{ %}
interface(CONST_INTER);
%}')
dnl
// 4 bit signed offset -- for predicated load/store
%}')dnl
OPERAND_VMEMORYA_IMMEDIATE_OFFSET(I, int, 4)
OPERAND_VMEMORYA_IMMEDIATE_OFFSET(L, long, 4)
dnl
@@ -63,8 +63,7 @@ operand vmemA_indOff$1$2(iRegP reg, vmemA_imm$1Offset$2 off)
scale(0x0);
disp($off);
%}
%}')
dnl
%}')dnl
OPERAND_VMEMORYA_INDIRECT_OFFSET(I, 4)
OPERAND_VMEMORYA_INDIRECT_OFFSET(L, 4)

@@ -75,7 +74,6 @@ source_hpp %{
%}

source %{

static inline BasicType vector_element_basic_type(const MachNode* n) {
const TypeVect* vt = n->bottom_type()->is_vect();
return vt->element_basic_type();
@@ -197,21 +195,19 @@ source %{
return true;
}
}

%}

definitions %{
int_def SVE_COST (200, 200);
%}


dnl
dnl ELEMENT_SHORT_CHART($1, $2)
dnl ELEMENT_SHORT_CHART(etype, node)
define(`ELEMENT_SHORT_CHAR',`ifelse(`$1', `T_SHORT',
`($2->bottom_type()->is_vect()->element_basic_type() == T_SHORT ||
($2->bottom_type()->is_vect()->element_basic_type() == T_CHAR))',
`($2->bottom_type()->is_vect()->element_basic_type() == $1)')')
`($2->bottom_type()->is_vect()->element_basic_type() == $1)')')dnl
dnl

// All SVE instructions
@@ -263,7 +259,7 @@ instruct $1(vReg dst, vReg src) %{
%}
ins_pipe(pipe_slow);
%}')dnl

dnl
// vector abs
UNARY_OP_TRUE_PREDICATE_ETYPE(vabsB, AbsVB, T_BYTE, B, 16, sve_abs)
UNARY_OP_TRUE_PREDICATE_ETYPE(vabsS, AbsVS, T_SHORT, H, 8, sve_abs)
@@ -743,12 +739,10 @@ REPLICATE(replicateB, ReplicateB, iRegIorL2I, B, 16)
REPLICATE(replicateS, ReplicateS, iRegIorL2I, H, 8)
REPLICATE(replicateI, ReplicateI, iRegIorL2I, S, 4)
REPLICATE(replicateL, ReplicateL, iRegL, D, 2)

REPLICATE_IMM8(replicateB_imm8, ReplicateB, immI8, B, 16)
REPLICATE_IMM8(replicateS_imm8, ReplicateS, immI8_shift8, H, 8)
REPLICATE_IMM8(replicateI_imm8, ReplicateI, immI8_shift8, S, 4)
REPLICATE_IMM8(replicateL_imm8, ReplicateL, immL8_shift8, D, 2)

FREPLICATE(replicateF, ReplicateF, vRegF, S, 4)
FREPLICATE(replicateD, ReplicateD, vRegD, D, 2)
dnl
@@ -767,9 +761,9 @@ instruct $1(vReg dst, vReg shift) %{
ins_pipe(pipe_slow);
%}')dnl
dnl
dnl VSHIFT_IMM_UNPREDICATE($1, $2, $3, $4, $5, $6 )
dnl VSHIFT_IMM_UNPREDICATE(insn_name, op_name, op_name2, size, min_vec_len, insn)
define(`VSHIFT_IMM_UNPREDICATE', `
dnl VSHIFT_IMM_UNPREDICATED($1, $2, $3, $4, $5, $6 )
dnl VSHIFT_IMM_UNPREDICATED(insn_name, op_name, op_name2, size, min_vec_len, insn)
define(`VSHIFT_IMM_UNPREDICATED', `
instruct $1(vReg dst, vReg src, immI shift) %{
predicate(UseSVE > 0 && n->as_Vector()->length() >= $5);
match(Set dst ($2 src ($3 shift)));
@@ -831,18 +825,18 @@ VSHIFT_TRUE_PREDICATE(vlsrB, URShiftVB, B, 16, sve_lsr)
VSHIFT_TRUE_PREDICATE(vlsrS, URShiftVS, H, 8, sve_lsr)
VSHIFT_TRUE_PREDICATE(vlsrI, URShiftVI, S, 4, sve_lsr)
VSHIFT_TRUE_PREDICATE(vlsrL, URShiftVL, D, 2, sve_lsr)
VSHIFT_IMM_UNPREDICATE(vasrB_imm, RShiftVB, RShiftCntV, B, 16, sve_asr)
VSHIFT_IMM_UNPREDICATE(vasrS_imm, RShiftVS, RShiftCntV, H, 8, sve_asr)
VSHIFT_IMM_UNPREDICATE(vasrI_imm, RShiftVI, RShiftCntV, S, 4, sve_asr)
VSHIFT_IMM_UNPREDICATE(vasrL_imm, RShiftVL, RShiftCntV, D, 2, sve_asr)
VSHIFT_IMM_UNPREDICATE(vlsrB_imm, URShiftVB, RShiftCntV, B, 16, sve_lsr)
VSHIFT_IMM_UNPREDICATE(vlsrS_imm, URShiftVS, RShiftCntV, H, 8, sve_lsr)
VSHIFT_IMM_UNPREDICATE(vlsrI_imm, URShiftVI, RShiftCntV, S, 4, sve_lsr)
VSHIFT_IMM_UNPREDICATE(vlsrL_imm, URShiftVL, RShiftCntV, D, 2, sve_lsr)
VSHIFT_IMM_UNPREDICATE(vlslB_imm, LShiftVB, LShiftCntV, B, 16, sve_lsl)
VSHIFT_IMM_UNPREDICATE(vlslS_imm, LShiftVS, LShiftCntV, H, 8, sve_lsl)
VSHIFT_IMM_UNPREDICATE(vlslI_imm, LShiftVI, LShiftCntV, S, 4, sve_lsl)
VSHIFT_IMM_UNPREDICATE(vlslL_imm, LShiftVL, LShiftCntV, D, 2, sve_lsl)
VSHIFT_IMM_UNPREDICATED(vasrB_imm, RShiftVB, RShiftCntV, B, 16, sve_asr)
VSHIFT_IMM_UNPREDICATED(vasrS_imm, RShiftVS, RShiftCntV, H, 8, sve_asr)
VSHIFT_IMM_UNPREDICATED(vasrI_imm, RShiftVI, RShiftCntV, S, 4, sve_asr)
VSHIFT_IMM_UNPREDICATED(vasrL_imm, RShiftVL, RShiftCntV, D, 2, sve_asr)
VSHIFT_IMM_UNPREDICATED(vlsrB_imm, URShiftVB, RShiftCntV, B, 16, sve_lsr)
VSHIFT_IMM_UNPREDICATED(vlsrS_imm, URShiftVS, RShiftCntV, H, 8, sve_lsr)
VSHIFT_IMM_UNPREDICATED(vlsrI_imm, URShiftVI, RShiftCntV, S, 4, sve_lsr)
VSHIFT_IMM_UNPREDICATED(vlsrL_imm, URShiftVL, RShiftCntV, D, 2, sve_lsr)
VSHIFT_IMM_UNPREDICATED(vlslB_imm, LShiftVB, LShiftCntV, B, 16, sve_lsl)
VSHIFT_IMM_UNPREDICATED(vlslS_imm, LShiftVS, LShiftCntV, H, 8, sve_lsl)
VSHIFT_IMM_UNPREDICATED(vlslI_imm, LShiftVI, LShiftCntV, S, 4, sve_lsl)
VSHIFT_IMM_UNPREDICATED(vlslL_imm, LShiftVL, LShiftCntV, D, 2, sve_lsl)
VSHIFT_COUNT(vshiftcntB, B, 16, T_BYTE)
VSHIFT_COUNT(vshiftcntS, H, 8, T_SHORT)
VSHIFT_COUNT(vshiftcntI, S, 4, T_INT)
@@ -859,4 +853,3 @@ BINARY_OP_UNPREDICATED(vsubI, SubVI, S, 4, sve_sub)
BINARY_OP_UNPREDICATED(vsubL, SubVL, D, 2, sve_sub)
BINARY_OP_UNPREDICATED(vsubF, SubVF, S, 4, sve_fsub)
BINARY_OP_UNPREDICATED(vsubD, SubVD, D, 2, sve_fsub)

@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -3822,7 +3822,6 @@ void MatchNode::count_commutative_op(int& count) {
"MaxV", "MinV",
"MulI","MulL","MulF","MulD",
"MulVB","MulVS","MulVI","MulVL","MulVF","MulVD",
"MinV","MaxV",
"OrI","OrL",
"OrV",
"XorI","XorL",
@@ -4173,7 +4172,6 @@ bool MatchRule::is_vector() const {
"MulVB","MulVS","MulVI","MulVL","MulVF","MulVD",
"CMoveVD", "CMoveVF",
"DivVF","DivVD",
"MinV","MaxV",
"AbsVB","AbsVS","AbsVI","AbsVL","AbsVF","AbsVD",
"NegVF","NegVD","NegVI",
"SqrtVD","SqrtVF",
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1998, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -61,23 +61,23 @@ class LoopNode : public RegionNode {
uint _loop_flags;
// Names for flag bitfields
enum { Normal=0, Pre=1, Main=2, Post=3, PreMainPostFlagsMask=3,
MainHasNoPreLoop=4,
HasExactTripCount=8,
InnerLoop=16,
PartialPeelLoop=32,
PartialPeelFailed=64,
HasReductions=128,
WasSlpAnalyzed=256,
PassedSlpAnalysis=512,
DoUnrollOnly=1024,
VectorizedLoop=2048,
HasAtomicPostLoop=4096,
HasRangeChecks=8192,
IsMultiversioned=16384,
StripMined=32768,
SubwordLoop=65536,
ProfileTripFailed=131072,
TransformedLongLoop=262144};
MainHasNoPreLoop = 1<<2,
HasExactTripCount = 1<<3,
InnerLoop = 1<<4,
PartialPeelLoop = 1<<5,
PartialPeelFailed = 1<<6,
HasReductions = 1<<7,
WasSlpAnalyzed = 1<<8,
PassedSlpAnalysis = 1<<9,
DoUnrollOnly = 1<<10,
VectorizedLoop = 1<<11,
HasAtomicPostLoop = 1<<12,
HasRangeChecks = 1<<13,
IsMultiversioned = 1<<14,
StripMined = 1<<15,
SubwordLoop = 1<<16,
ProfileTripFailed = 1<<17,
TransformedLongLoop = 1<<18 };
char _unswitch_count;
enum { _unswitch_max=3 };
char _postloop_flags;

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