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Cesar Soares LucasTheRealMDoerr
Cesar Soares Lucas
authored and
TheRealMDoerr
committed
8241503: C2: Share MacroAssembler between mach nodes during code emission
Reviewed-by: kvn, mdoerr, amitkumar, lucy
1 parent 0656f08 commit 31ee510

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+1713
-2026
lines changed

‎src/hotspot/cpu/aarch64/aarch64.ad‎

Lines changed: 78 additions & 154 deletions
Large diffs are not rendered by default.

‎src/hotspot/cpu/aarch64/aarch64_vector.ad‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ source %{
9494
PRegister Pg, const Address &adr);
9595

9696
// Predicated load/store, with optional ptrue to all elements of given predicate register.
97-
static void loadStoreA_predicated(C2_MacroAssembler masm, bool is_store, FloatRegister reg,
97+
static void loadStoreA_predicated(C2_MacroAssembler* masm, bool is_store, FloatRegister reg,
9898
PRegister pg, BasicType mem_elem_bt, BasicType vector_elem_bt,
9999
int opcode, Register base, int index, int size, int disp) {
100100
sve_mem_insn_predicate insn;
@@ -119,7 +119,7 @@ source %{
119119
ShouldNotReachHere();
120120
}
121121
int imm4 = disp / mesize / Matcher::scalable_vector_reg_size(vector_elem_bt);
122-
(masm.*insn)(reg, Assembler::elemType_to_regVariant(vector_elem_bt), pg, Address(base, imm4));
122+
(masm->*insn)(reg, Assembler::elemType_to_regVariant(vector_elem_bt), pg, Address(base, imm4));
123123
} else {
124124
assert(false, "unimplemented");
125125
ShouldNotReachHere();
@@ -422,7 +422,7 @@ instruct loadV(vReg dst, vmemA mem) %{
422422
BasicType bt = Matcher::vector_element_basic_type(this);
423423
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
424424
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
425-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ false,
425+
loadStoreA_predicated(masm, /* is_store */ false,
426426
$dst$$FloatRegister, ptrue, bt, bt, $mem->opcode(),
427427
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
428428
%}
@@ -439,7 +439,7 @@ instruct storeV(vReg src, vmemA mem) %{
439439
BasicType bt = Matcher::vector_element_basic_type(this, $src);
440440
uint length_in_bytes = Matcher::vector_length_in_bytes(this, $src);
441441
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
442-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ true,
442+
loadStoreA_predicated(masm, /* is_store */ true,
443443
$src$$FloatRegister, ptrue, bt, bt, $mem->opcode(),
444444
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
445445
%}
@@ -454,7 +454,7 @@ instruct loadV_masked(vReg dst, vmemA mem, pRegGov pg) %{
454454
format %{ "loadV_masked $dst, $pg, $mem" %}
455455
ins_encode %{
456456
BasicType bt = Matcher::vector_element_basic_type(this);
457-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ false, $dst$$FloatRegister,
457+
loadStoreA_predicated(masm, /* is_store */ false, $dst$$FloatRegister,
458458
$pg$$PRegister, bt, bt, $mem->opcode(),
459459
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
460460
%}
@@ -467,7 +467,7 @@ instruct storeV_masked(vReg src, vmemA mem, pRegGov pg) %{
467467
format %{ "storeV_masked $mem, $pg, $src" %}
468468
ins_encode %{
469469
BasicType bt = Matcher::vector_element_basic_type(this, $src);
470-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ true, $src$$FloatRegister,
470+
loadStoreA_predicated(masm, /* is_store */ true, $src$$FloatRegister,
471471
$pg$$PRegister, bt, bt, $mem->opcode(),
472472
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
473473
%}
@@ -4929,7 +4929,7 @@ instruct vloadmask_loadV(pReg dst, indirect mem, vReg tmp, rFlagsReg cr) %{
49294929
BasicType bt = Matcher::vector_element_basic_type(this);
49304930
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
49314931
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
4932-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
4932+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
49334933
ptrue, T_BOOLEAN, bt, $mem->opcode(),
49344934
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
49354935
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -4950,7 +4950,7 @@ instruct vloadmask_loadV_masked(pReg dst, indirect mem, pRegGov pg,
49504950
// Load valid mask values which are boolean type, and extend them to the
49514951
// defined vector element type. Convert the vector to predicate.
49524952
BasicType bt = Matcher::vector_element_basic_type(this);
4953-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
4953+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
49544954
$pg$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
49554955
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
49564956
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -4977,7 +4977,7 @@ instruct vloadmask_loadVMasked(pReg dst, vmemA mem, pRegGov pg, vReg tmp, rFlags
49774977
BasicType bt = Matcher::vector_element_basic_type(this);
49784978
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
49794979
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
4980-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
4980+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
49814981
ptrue, T_BOOLEAN, bt, $mem->opcode(),
49824982
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
49834983
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -5005,7 +5005,7 @@ instruct vloadmask_loadVMasked_masked(pReg dst, vmemA mem, pRegGov pg1, pRegGov
50055005
BasicType bt = Matcher::vector_element_basic_type(this);
50065006
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
50075007
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
5008-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
5008+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
50095009
$pg2$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
50105010
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
50115011
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -5030,7 +5030,7 @@ instruct storeV_vstoremask(indirect mem, pReg src, immI_gt_1 esize, vReg tmp) %{
50305030
assert(type2aelembytes(bt) == (int)$esize$$constant, "unsupported type");
50315031
Assembler::SIMD_RegVariant size = __ elemBytes_to_regVariant($esize$$constant);
50325032
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
5033-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
5033+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
50345034
ptrue, T_BOOLEAN, bt, $mem->opcode(),
50355035
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
50365036
%}
@@ -5052,7 +5052,7 @@ instruct storeV_vstoremask_masked(indirect mem, pReg src, immI_gt_1 esize,
50525052
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
50535053
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
50545054
__ sve_gen_mask_imm($pgtmp$$PRegister, bt, Matcher::vector_length(this, $src));
5055-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
5055+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
50565056
$pgtmp$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
50575057
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
50585058
%}
@@ -5078,7 +5078,7 @@ instruct storeVMasked_vstoremask(vmemA mem, pReg src, pRegGov pg, immI_gt_1 esiz
50785078
assert(type2aelembytes(bt) == (int)$esize$$constant, "unsupported type.");
50795079
Assembler::SIMD_RegVariant size = __ elemBytes_to_regVariant($esize$$constant);
50805080
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
5081-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
5081+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
50825082
ptrue, T_BOOLEAN, bt, $mem->opcode(),
50835083
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
50845084
%}
@@ -5105,7 +5105,7 @@ instruct storeVMasked_vstoremask_masked(vmemA mem, pReg src, pRegGov pg, immI_gt
51055105
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
51065106
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
51075107
__ sve_gen_mask_imm($pgtmp$$PRegister, bt, Matcher::vector_length(this, $src));
5108-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
5108+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
51095109
$pgtmp$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
51105110
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
51115111
%}

‎src/hotspot/cpu/aarch64/aarch64_vector_ad.m4‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ source %{
8484
PRegister Pg, const Address &adr);
8585

8686
// Predicated load/store, with optional ptrue to all elements of given predicate register.
87-
static void loadStoreA_predicated(C2_MacroAssembler masm, bool is_store, FloatRegister reg,
87+
static void loadStoreA_predicated(C2_MacroAssembler* masm, bool is_store, FloatRegister reg,
8888
PRegister pg, BasicType mem_elem_bt, BasicType vector_elem_bt,
8989
int opcode, Register base, int index, int size, int disp) {
9090
sve_mem_insn_predicate insn;
@@ -109,7 +109,7 @@ source %{
109109
ShouldNotReachHere();
110110
}
111111
int imm4 = disp / mesize / Matcher::scalable_vector_reg_size(vector_elem_bt);
112-
(masm.*insn)(reg, Assembler::elemType_to_regVariant(vector_elem_bt), pg, Address(base, imm4));
112+
(masm->*insn)(reg, Assembler::elemType_to_regVariant(vector_elem_bt), pg, Address(base, imm4));
113113
} else {
114114
assert(false, "unimplemented");
115115
ShouldNotReachHere();
@@ -361,7 +361,7 @@ instruct loadV(vReg dst, vmemA mem) %{
361361
BasicType bt = Matcher::vector_element_basic_type(this);
362362
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
363363
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
364-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ false,
364+
loadStoreA_predicated(masm, /* is_store */ false,
365365
$dst$$FloatRegister, ptrue, bt, bt, $mem->opcode(),
366366
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
367367
%}
@@ -378,7 +378,7 @@ instruct storeV(vReg src, vmemA mem) %{
378378
BasicType bt = Matcher::vector_element_basic_type(this, $src);
379379
uint length_in_bytes = Matcher::vector_length_in_bytes(this, $src);
380380
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
381-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ true,
381+
loadStoreA_predicated(masm, /* is_store */ true,
382382
$src$$FloatRegister, ptrue, bt, bt, $mem->opcode(),
383383
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
384384
%}
@@ -393,7 +393,7 @@ instruct loadV_masked(vReg dst, vmemA mem, pRegGov pg) %{
393393
format %{ "loadV_masked $dst, $pg, $mem" %}
394394
ins_encode %{
395395
BasicType bt = Matcher::vector_element_basic_type(this);
396-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ false, $dst$$FloatRegister,
396+
loadStoreA_predicated(masm, /* is_store */ false, $dst$$FloatRegister,
397397
$pg$$PRegister, bt, bt, $mem->opcode(),
398398
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
399399
%}
@@ -406,7 +406,7 @@ instruct storeV_masked(vReg src, vmemA mem, pRegGov pg) %{
406406
format %{ "storeV_masked $mem, $pg, $src" %}
407407
ins_encode %{
408408
BasicType bt = Matcher::vector_element_basic_type(this, $src);
409-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), /* is_store */ true, $src$$FloatRegister,
409+
loadStoreA_predicated(masm, /* is_store */ true, $src$$FloatRegister,
410410
$pg$$PRegister, bt, bt, $mem->opcode(),
411411
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
412412
%}
@@ -3321,7 +3321,7 @@ instruct vloadmask_loadV(pReg dst, indirect mem, vReg tmp, rFlagsReg cr) %{
33213321
BasicType bt = Matcher::vector_element_basic_type(this);
33223322
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
33233323
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
3324-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
3324+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
33253325
ptrue, T_BOOLEAN, bt, $mem->opcode(),
33263326
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
33273327
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -3342,7 +3342,7 @@ instruct vloadmask_loadV_masked(pReg dst, indirect mem, pRegGov pg,
33423342
// Load valid mask values which are boolean type, and extend them to the
33433343
// defined vector element type. Convert the vector to predicate.
33443344
BasicType bt = Matcher::vector_element_basic_type(this);
3345-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
3345+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
33463346
$pg$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
33473347
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
33483348
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -3369,7 +3369,7 @@ instruct vloadmask_loadVMasked(pReg dst, vmemA mem, pRegGov pg, vReg tmp, rFlags
33693369
BasicType bt = Matcher::vector_element_basic_type(this);
33703370
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
33713371
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
3372-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
3372+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
33733373
ptrue, T_BOOLEAN, bt, $mem->opcode(),
33743374
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
33753375
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -3397,7 +3397,7 @@ instruct vloadmask_loadVMasked_masked(pReg dst, vmemA mem, pRegGov pg1, pRegGov
33973397
BasicType bt = Matcher::vector_element_basic_type(this);
33983398
uint length_in_bytes = Matcher::vector_length_in_bytes(this);
33993399
assert(length_in_bytes == MaxVectorSize, "invalid vector length");
3400-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), false, $tmp$$FloatRegister,
3400+
loadStoreA_predicated(masm, false, $tmp$$FloatRegister,
34013401
$pg2$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
34023402
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
34033403
__ sve_cmp(Assembler::NE, $dst$$PRegister, __ elemType_to_regVariant(bt),
@@ -3422,7 +3422,7 @@ instruct storeV_vstoremask(indirect mem, pReg src, immI_gt_1 esize, vReg tmp) %{
34223422
assert(type2aelembytes(bt) == (int)$esize$$constant, "unsupported type");
34233423
Assembler::SIMD_RegVariant size = __ elemBytes_to_regVariant($esize$$constant);
34243424
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
3425-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
3425+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
34263426
ptrue, T_BOOLEAN, bt, $mem->opcode(),
34273427
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
34283428
%}
@@ -3444,7 +3444,7 @@ instruct storeV_vstoremask_masked(indirect mem, pReg src, immI_gt_1 esize,
34443444
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
34453445
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
34463446
__ sve_gen_mask_imm($pgtmp$$PRegister, bt, Matcher::vector_length(this, $src));
3447-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
3447+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
34483448
$pgtmp$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
34493449
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
34503450
%}
@@ -3470,7 +3470,7 @@ instruct storeVMasked_vstoremask(vmemA mem, pReg src, pRegGov pg, immI_gt_1 esiz
34703470
assert(type2aelembytes(bt) == (int)$esize$$constant, "unsupported type.");
34713471
Assembler::SIMD_RegVariant size = __ elemBytes_to_regVariant($esize$$constant);
34723472
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
3473-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
3473+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
34743474
ptrue, T_BOOLEAN, bt, $mem->opcode(),
34753475
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
34763476
%}
@@ -3497,7 +3497,7 @@ instruct storeVMasked_vstoremask_masked(vmemA mem, pReg src, pRegGov pg, immI_gt
34973497
Assembler::SIMD_RegVariant size = __ elemType_to_regVariant(bt);
34983498
__ sve_cpy($tmp$$FloatRegister, size, $src$$PRegister, 1, false);
34993499
__ sve_gen_mask_imm($pgtmp$$PRegister, bt, Matcher::vector_length(this, $src));
3500-
loadStoreA_predicated(C2_MacroAssembler(&cbuf), true, $tmp$$FloatRegister,
3500+
loadStoreA_predicated(masm, true, $tmp$$FloatRegister,
35013501
$pgtmp$$PRegister, T_BOOLEAN, bt, $mem->opcode(),
35023502
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
35033503
%}

‎src/hotspot/cpu/aarch64/ad_encode.m4‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ define(choose, `loadStore($1, &MacroAssembler::$3, $2, $4,
2929
%}')dnl
3030
define(access, `
3131
$3Register $1_reg = as_$3Register($$1$$reg);
32-
$4choose(C2_MacroAssembler(&cbuf), $1_reg,$2,$mem->opcode(),
32+
$4choose(masm, $1_reg,$2,$mem->opcode(),
3333
as_Register($mem$$base),$mem$$index,$mem$$scale,$mem$$disp,$5)')dnl
3434
define(load,`
3535
// This encoding class is generated automatically from ad_encode.m4.
@@ -59,8 +59,7 @@ define(STORE0,`
5959
// This encoding class is generated automatically from ad_encode.m4.
6060
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
6161
enc_class aarch64_enc_$2`'0(memory$4 mem) %{
62-
C2_MacroAssembler _masm(&cbuf);
63-
choose(_masm,zr,$2,$mem->opcode(),
62+
choose(masm,zr,$2,$mem->opcode(),
6463
as_$3Register($mem$$base),$mem$$index,$mem$$scale,$mem$$disp,$4)')dnl
6564
STORE(iRegI,strb,,,1)
6665
STORE0(iRegI,strb,,1)
@@ -72,7 +71,6 @@ STORE(iRegL,str,,
7271
`// we sometimes get asked to store the stack pointer into the
7372
// current thread -- we cannot do that directly on AArch64
7473
if (src_reg == r31_sp) {
75-
C2_MacroAssembler _masm(&cbuf);
7674
assert(as_Register($mem$$base) == rthread, "unexpected store for sp");
7775
__ mov(rscratch2, sp);
7876
src_reg = rscratch2;
@@ -85,8 +83,7 @@ STORE(vRegD,strd,Float,,8)
8583
// This encoding class is generated automatically from ad_encode.m4.
8684
// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
8785
enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
88-
C2_MacroAssembler _masm(&cbuf);
8986
__ membar(Assembler::StoreStore);
90-
loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
87+
loadStore(masm, &MacroAssembler::strb, zr, $mem->opcode(),
9188
as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
9289
%}

‎src/hotspot/cpu/aarch64/compiledIC_aarch64.cpp‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,24 +34,20 @@
3434

3535
// ----------------------------------------------------------------------------
3636

37-
#define __ _masm.
38-
address CompiledDirectCall::emit_to_interp_stub(CodeBuffer &cbuf, address mark) {
39-
precond(cbuf.stubs()->start() != badAddress);
40-
precond(cbuf.stubs()->end() != badAddress);
37+
#define __ masm->
38+
address CompiledDirectCall::emit_to_interp_stub(MacroAssembler *masm, address mark) {
39+
precond(__ code()->stubs()->start() != badAddress);
40+
precond(__ code()->stubs()->end() != badAddress);
4141

4242
// Stub is fixed up when the corresponding call is converted from
4343
// calling compiled code to calling interpreted code.
4444
// mov rmethod, 0
4545
// jmp -4 # to self
4646

4747
if (mark == nullptr) {
48-
mark = cbuf.insts_mark(); // Get mark within main instrs section.
48+
mark = __ inst_mark(); // Get mark within main instrs section.
4949
}
5050

51-
// Note that the code buffer's insts_mark is always relative to insts.
52-
// That's why we must use the macroassembler to generate a stub.
53-
MacroAssembler _masm(&cbuf);
54-
5551
address base = __ start_a_stub(to_interp_stub_size());
5652
int offset = __ offset();
5753
if (base == nullptr) {

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