Skip to content

Commit

Permalink
8315841: RISC-V: Check for hardware TSO support
Browse files Browse the repository at this point in the history
Reviewed-by: vkempik, rehn, fyang
  • Loading branch information
luhenry committed Sep 11, 2023
1 parent a04c6c1 commit 35bccac
Show file tree
Hide file tree
Showing 5 changed files with 28 additions and 1 deletion.
1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/globals_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,7 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions") \
product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions") \
product(bool, UseZicboz, false, EXPERIMENTAL, "Use Zicboz instructions") \
product(bool, UseZtso, false, EXPERIMENTAL, "Assume Ztso memory model") \
product(bool, UseZihintpause, false, EXPERIMENTAL, \
"Use Zihintpause instructions") \
product(bool, UseRVVForBigIntegerShiftIntrinsics, true, \
Expand Down
18 changes: 17 additions & 1 deletion src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -376,8 +376,24 @@ class MacroAssembler: public Assembler {
return ((predecessor & 0x3) << 2) | (successor & 0x3);
}

void fence(uint32_t predecessor, uint32_t successor) {
if (UseZtso) {
if ((pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) == StoreLoad) {
// TSO allows for stores to be reordered after loads. When the compiler
// generates a fence to disallow that, we are required to generate the
// fence for correctness.
Assembler::fence(predecessor, successor);
} else {
// TSO guarantees other fences already.
}
} else {
// always generate fence for RVWMO
Assembler::fence(predecessor, successor);
}
}

void pause() {
fence(w, 0);
Assembler::fence(w, 0);
}

// prints msg, dumps registers and stops execution
Expand Down
8 changes: 8 additions & 0 deletions src/hotspot/cpu/riscv/vm_version_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -210,6 +210,14 @@ void VM_Version::initialize() {
unaligned_access.value() == MISALIGNED_FAST);
}

#ifdef __riscv_ztso
// Hotspot is compiled with TSO support, it will only run on hardware which
// supports Ztso
if (FLAG_IS_DEFAULT(UseZtso)) {
FLAG_SET_DEFAULT(UseZtso, true);
}
#endif

if (UseZbb) {
if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
FLAG_SET_DEFAULT(UsePopCountInstruction, true);
Expand Down
1 change: 1 addition & 0 deletions src/hotspot/cpu/riscv/vm_version_riscv.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -134,6 +134,7 @@ class VM_Version : public Abstract_VM_Version {
decl(ext_Zicsr , "Zicsr" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zifencei , "Zifencei" , RV_NO_FLAG_BIT, true , NO_UPDATE_DEFAULT) \
decl(ext_Zic64b , "Zic64b" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZic64b)) \
decl(ext_Ztso , "Ztso" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZtso)) \
decl(ext_Zihintpause , "Zihintpause" , RV_NO_FLAG_BIT, true , UPDATE_DEFAULT(UseZihintpause)) \
decl(mvendorid , "VendorId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
decl(marchid , "ArchId" , RV_NO_FLAG_BIT, false, NO_UPDATE_DEFAULT) \
Expand Down
1 change: 1 addition & 0 deletions src/hotspot/os_cpu/linux_riscv/vm_version_linux_riscv.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -236,6 +236,7 @@ void VM_Version::rivos_features() {
ext_Zicsr.enable_feature();
ext_Zifencei.enable_feature();
ext_Zic64b.enable_feature();
ext_Ztso.enable_feature();
ext_Zihintpause.enable_feature();

unaligned_access.enable_feature(MISALIGNED_FAST);
Expand Down

1 comment on commit 35bccac

@openjdk-notifier
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Please sign in to comment.