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RealFYangRealFYang
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8343242: RISC-V: Refactor materialization of literal address
Reviewed-by: rehn, fjiang
1 parent d26412e commit 37a3398

14 files changed

+74
-133
lines changed

‎src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,9 +42,7 @@
4242
void C1SafepointPollStub::emit_code(LIR_Assembler* ce) {
4343
__ bind(_entry);
4444
InternalAddress safepoint_pc(__ pc() - __ offset() + safepoint_offset());
45-
__ relocate(safepoint_pc.rspec(), [&] {
46-
__ la(t0, safepoint_pc.target());
47-
});
45+
__ la(t0, safepoint_pc);
4846
__ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));
4947

5048
assert(SharedRuntime::polling_page_return_handler_blob() != nullptr,

‎src/hotspot/cpu/riscv/c1_LIRAssembler_arraycopy_riscv.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -333,8 +333,7 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
333333
const char *name = nullptr;
334334
address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
335335

336-
CodeBlob *cb = CodeCache::find_blob(entry);
337-
if (cb != nullptr) {
336+
if (CodeCache::contains(entry)) {
338337
__ far_call(RuntimeAddress(entry));
339338
} else {
340339
const int args_num = 3;

‎src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1402,9 +1402,7 @@ void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmit
14021402
}
14031403
int pc_for_athrow_offset = __ offset();
14041404
InternalAddress pc_for_athrow(__ pc());
1405-
__ relocate(pc_for_athrow.rspec(), [&] {
1406-
__ la(exceptionPC->as_register(), pc_for_athrow.target());
1407-
});
1405+
__ la(exceptionPC->as_register(), pc_for_athrow);
14081406
add_call_info(pc_for_athrow_offset, info); // for exception handler
14091407

14101408
__ verify_not_null_oop(x10);

‎src/hotspot/cpu/riscv/globals_riscv.hpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,6 @@ define_pd_global(intx, InlineSmallCode, 1000);
8181
range, \
8282
constraint) \
8383
\
84-
product(bool, NearCpool, true, \
85-
"constant pool is close to instructions") \
8684
product(bool, UseBlockZeroing, false, \
8785
"Use Zicboz for block zeroing") \
8886
product(intx, BlockZeroingLowLimit, 256, \

‎src/hotspot/cpu/riscv/interp_masm_riscv.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -191,10 +191,7 @@ void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(Register reg, i
191191
}
192192

193193
void InterpreterMacroAssembler::get_dispatch() {
194-
ExternalAddress target((address)Interpreter::dispatch_table());
195-
relocate(target.rspec(), [&] {
196-
la(xdispatch, target.target());
197-
});
194+
la(xdispatch, ExternalAddress((address)Interpreter::dispatch_table()));
198195
}
199196

200197
void InterpreterMacroAssembler::get_cache_index_at_bcp(Register index,

‎src/hotspot/cpu/riscv/interpreterRT_riscv.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ void InterpreterRuntime::SignatureHandlerGenerator::generate(uint64_t fingerprin
166166
iterate(fingerprint);
167167

168168
// return result handler
169-
__ la(x10, ExternalAddress(Interpreter::result_handler(method()->result_type())));
169+
__ movptr(x10, ExternalAddress(Interpreter::result_handler(method()->result_type())));
170170
__ ret();
171171

172172
__ flush();

‎src/hotspot/cpu/riscv/jniFastGetField_riscv.cpp

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -73,14 +73,10 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
7373
MacroAssembler* masm = new MacroAssembler(&cbuf);
7474
address fast_entry = __ pc();
7575

76-
Address target(SafepointSynchronize::safepoint_counter_addr());
77-
__ relocate(target.rspec(), [&] {
78-
__ la(rcounter_addr, target.target());
79-
});
80-
8176
Label slow;
82-
Address safepoint_counter_addr(rcounter_addr, 0);
83-
__ lwu(rcounter, safepoint_counter_addr);
77+
ExternalAddress counter(SafepointSynchronize::safepoint_counter_addr());
78+
__ la(rcounter_addr, counter);
79+
__ lwu(rcounter, Address(rcounter_addr));
8480
// An even value means there are no ongoing safepoint operations
8581
__ test_bit(t0, rcounter, 0);
8682
__ bnez(t0, slow);
@@ -91,12 +87,7 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
9187

9288
// Check to see if a field access watch has been set before we
9389
// take the fast path.
94-
ExternalAddress target((address) JvmtiExport::get_field_access_count_addr());
95-
__ relocate(target.rspec(), [&] {
96-
int32_t offset;
97-
__ la(result, target.target(), offset);
98-
__ lwu(result, Address(result, offset));
99-
});
90+
__ lwu(result, ExternalAddress(JvmtiExport::get_field_access_count_addr()));
10091
__ bnez(result, slow);
10192

10293
__ mv(robj, c_rarg1);
@@ -143,7 +134,7 @@ address JNI_FastGetField::generate_fast_get_int_field0(BasicType type) {
143134
// (LoadStore for volatile field).
144135
__ membar(MacroAssembler::LoadLoad | MacroAssembler::LoadStore);
145136

146-
__ lw(t0, safepoint_counter_addr);
137+
__ lw(t0, Address(rcounter_addr));
147138
__ bne(rcounter, t0, slow);
148139

149140
switch (type) {

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

Lines changed: 42 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -531,12 +531,7 @@ void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file,
531531
}
532532

533533
// Call indirectly to solve generation ordering problem
534-
RuntimeAddress target(StubRoutines::verify_oop_subroutine_entry_address());
535-
relocate(target.rspec(), [&] {
536-
int32_t offset;
537-
la(t1, target.target(), offset);
538-
ld(t1, Address(t1, offset));
539-
});
534+
ld(t1, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
540535
jalr(t1);
541536

542537
pop_reg(RegSet::of(ra, t0, t1, c_rarg0), sp);
@@ -576,12 +571,7 @@ void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* f
576571
}
577572

578573
// Call indirectly to solve generation ordering problem
579-
RuntimeAddress target(StubRoutines::verify_oop_subroutine_entry_address());
580-
relocate(target.rspec(), [&] {
581-
int32_t offset;
582-
la(t1, target.target(), offset);
583-
ld(t1, Address(t1, offset));
584-
});
574+
ld(t1, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
585575
jalr(t1);
586576

587577
pop_reg(RegSet::of(ra, t0, t1, c_rarg0), sp);
@@ -839,27 +829,30 @@ void MacroAssembler::la(Register Rd, const address addr) {
839829
}
840830

841831
void MacroAssembler::la(Register Rd, const address addr, int32_t &offset) {
842-
if (is_32bit_offset_from_codecache((int64_t)addr)) {
843-
int64_t distance = addr - pc();
844-
assert(is_valid_32bit_offset(distance), "Must be");
845-
auipc(Rd, (int32_t)distance + 0x800);
846-
offset = ((int32_t)distance << 20) >> 20;
847-
} else {
848-
assert(!CodeCache::contains(addr), "Must be");
849-
movptr(Rd, addr, offset);
850-
}
832+
int64_t distance = addr - pc();
833+
assert(is_valid_32bit_offset(distance), "Must be");
834+
auipc(Rd, (int32_t)distance + 0x800);
835+
offset = ((int32_t)distance << 20) >> 20;
851836
}
852837

838+
// Materialize with auipc + addi sequence if adr is a literal
839+
// address inside code cache. Emit a movptr sequence otherwise.
853840
void MacroAssembler::la(Register Rd, const Address &adr) {
854841
switch (adr.getMode()) {
855842
case Address::literal: {
856843
relocInfo::relocType rtype = adr.rspec().reloc()->type();
857844
if (rtype == relocInfo::none) {
858845
mv(Rd, (intptr_t)(adr.target()));
859846
} else {
860-
relocate(adr.rspec(), [&] {
861-
movptr(Rd, adr.target());
862-
});
847+
if (CodeCache::contains(adr.target())) {
848+
relocate(adr.rspec(), [&] {
849+
la(Rd, adr.target());
850+
});
851+
} else {
852+
relocate(adr.rspec(), [&] {
853+
movptr(Rd, adr.target());
854+
});
855+
}
863856
}
864857
break;
865858
}
@@ -975,11 +968,15 @@ void MacroAssembler::j(const address dest, Register temp) {
975968
void MacroAssembler::j(const Address &dest, Register temp) {
976969
switch (dest.getMode()) {
977970
case Address::literal: {
978-
relocate(dest.rspec(), [&] {
979-
int32_t offset;
980-
la(temp, dest.target(), offset);
981-
jr(temp, offset);
982-
});
971+
if (CodeCache::contains(dest.target())) {
972+
far_jump(dest, temp);
973+
} else {
974+
relocate(dest.rspec(), [&] {
975+
int32_t offset;
976+
movptr(temp, dest.target(), offset);
977+
jr(temp, offset);
978+
});
979+
}
983980
break;
984981
}
985982
case Address::base_plus_offset: {
@@ -1026,14 +1023,13 @@ void MacroAssembler::jalr(Register Rs, int32_t offset) {
10261023

10271024
void MacroAssembler::rt_call(address dest, Register tmp) {
10281025
assert(tmp != x5, "tmp register must not be x5.");
1029-
CodeBlob *cb = CodeCache::find_blob(dest);
10301026
RuntimeAddress target(dest);
1031-
if (cb) {
1027+
if (CodeCache::contains(dest)) {
10321028
far_call(target, tmp);
10331029
} else {
10341030
relocate(target.rspec(), [&] {
10351031
int32_t offset;
1036-
la(tmp, target.target(), offset);
1032+
movptr(tmp, target.target(), offset);
10371033
jalr(tmp, offset);
10381034
});
10391035
}
@@ -1974,16 +1970,18 @@ void MacroAssembler::reinit_heapbase() {
19741970
if (Universe::is_fully_initialized()) {
19751971
mv(xheapbase, CompressedOops::base());
19761972
} else {
1977-
ExternalAddress target(CompressedOops::base_addr());
1978-
relocate(target.rspec(), [&] {
1979-
int32_t offset;
1980-
la(xheapbase, target.target(), offset);
1981-
ld(xheapbase, Address(xheapbase, offset));
1982-
});
1973+
ld(xheapbase, ExternalAddress(CompressedOops::base_addr()));
19831974
}
19841975
}
19851976
}
19861977

1978+
void MacroAssembler::movptr(Register Rd, const Address &addr, Register temp) {
1979+
assert(addr.getMode() == Address::literal, "must be applied to a literal address");
1980+
relocate(addr.rspec(), [&] {
1981+
movptr(Rd, addr.target(), temp);
1982+
});
1983+
}
1984+
19871985
void MacroAssembler::movptr(Register Rd, address addr, Register temp) {
19881986
int offset = 0;
19891987
movptr(Rd, addr, offset, temp);
@@ -2520,10 +2518,10 @@ void MacroAssembler::movoop(Register dst, jobject obj) {
25202518
RelocationHolder rspec = oop_Relocation::spec(oop_index);
25212519

25222520
if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
2523-
la(dst, Address((address)obj, rspec));
2521+
movptr(dst, Address((address)obj, rspec));
25242522
} else {
25252523
address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
2526-
ld_constant(dst, Address(dummy, rspec));
2524+
ld(dst, Address(dummy, rspec));
25272525
}
25282526
}
25292527

@@ -2537,7 +2535,7 @@ void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
25372535
oop_index = oop_recorder()->find_index(obj);
25382536
}
25392537
RelocationHolder rspec = metadata_Relocation::spec(oop_index);
2540-
la(dst, Address((address)obj, rspec));
2538+
movptr(dst, Address((address)obj, rspec));
25412539
}
25422540

25432541
// Writes to stack successive pages until offset reached to check for
@@ -3622,7 +3620,7 @@ void MacroAssembler::atomic_cas(
36223620
}
36233621

36243622
void MacroAssembler::far_jump(const Address &entry, Register tmp) {
3625-
assert(CodeCache::find_blob(entry.target()) != nullptr,
3623+
assert(CodeCache::contains(entry.target()),
36263624
"destination of far jump not found in code cache");
36273625
assert(entry.rspec().type() == relocInfo::external_word_type
36283626
|| entry.rspec().type() == relocInfo::runtime_call_type
@@ -3641,7 +3639,7 @@ void MacroAssembler::far_jump(const Address &entry, Register tmp) {
36413639

36423640
void MacroAssembler::far_call(const Address &entry, Register tmp) {
36433641
assert(tmp != x5, "tmp register must not be x5.");
3644-
assert(CodeCache::find_blob(entry.target()) != nullptr,
3642+
assert(CodeCache::contains(entry.target()),
36453643
"destination of far call not found in code cache");
36463644
assert(entry.rspec().type() == relocInfo::external_word_type
36473645
|| entry.rspec().type() == relocInfo::runtime_call_type
@@ -4493,11 +4491,7 @@ void MacroAssembler::decrementw(const Address dst, int32_t value, Register tmp1,
44934491
void MacroAssembler::cmpptr(Register src1, const Address &src2, Label& equal, Register tmp) {
44944492
assert_different_registers(src1, tmp);
44954493
assert(src2.getMode() == Address::literal, "must be applied to a literal address");
4496-
relocate(src2.rspec(), [&] {
4497-
int32_t offset;
4498-
la(tmp, src2.target(), offset);
4499-
ld(tmp, Address(tmp, offset));
4500-
});
4494+
ld(tmp, src2);
45014495
beq(src1, tmp, equal);
45024496
}
45034497

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

Lines changed: 14 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -832,7 +832,6 @@ class MacroAssembler: public Assembler {
832832
compare_and_branch_insn insn,
833833
compare_and_branch_label_insn neg_insn, bool is_far = false);
834834

835-
// la will use movptr instead of GOT when not in reach for auipc.
836835
void la(Register Rd, Label &label);
837836
void la(Register Rd, const address addr);
838837
void la(Register Rd, const address addr, int32_t &offset);
@@ -866,8 +865,10 @@ class MacroAssembler: public Assembler {
866865
// patched to any 48-bit constant, i.e. address.
867866
// If common case supply additional temp register
868867
// to shorten the instruction sequence.
868+
void movptr(Register Rd, const Address &addr, Register tmp = noreg);
869869
void movptr(Register Rd, address addr, Register tmp = noreg);
870870
void movptr(Register Rd, address addr, int32_t &offset, Register tmp = noreg);
871+
871872
private:
872873
void movptr1(Register Rd, uintptr_t addr, int32_t &offset);
873874
void movptr2(Register Rd, uintptr_t addr, int32_t &offset, Register tmp);
@@ -926,8 +927,9 @@ class MacroAssembler: public Assembler {
926927
#define INSN(NAME) \
927928
void NAME(Register Rd, address dest) { \
928929
assert_cond(dest != nullptr); \
929-
int64_t distance = dest - pc(); \
930-
if (is_valid_32bit_offset(distance)) { \
930+
if (CodeCache::contains(dest)) { \
931+
int64_t distance = dest - pc(); \
932+
assert(is_valid_32bit_offset(distance), "Must be"); \
931933
auipc(Rd, (int32_t)distance + 0x800); \
932934
Assembler::NAME(Rd, Rd, ((int32_t)distance << 20) >> 20); \
933935
} else { \
@@ -983,8 +985,9 @@ class MacroAssembler: public Assembler {
983985
#define INSN(NAME) \
984986
void NAME(FloatRegister Rd, address dest, Register temp = t0) { \
985987
assert_cond(dest != nullptr); \
986-
int64_t distance = dest - pc(); \
987-
if (is_valid_32bit_offset(distance)) { \
988+
if (CodeCache::contains(dest)) { \
989+
int64_t distance = dest - pc(); \
990+
assert(is_valid_32bit_offset(distance), "Must be"); \
988991
auipc(temp, (int32_t)distance + 0x800); \
989992
Assembler::NAME(Rd, temp, ((int32_t)distance << 20) >> 20); \
990993
} else { \
@@ -1044,8 +1047,9 @@ class MacroAssembler: public Assembler {
10441047
void NAME(Register Rs, address dest, Register temp = t0) { \
10451048
assert_cond(dest != nullptr); \
10461049
assert_different_registers(Rs, temp); \
1047-
int64_t distance = dest - pc(); \
1048-
if (is_valid_32bit_offset(distance)) { \
1050+
if (CodeCache::contains(dest)) { \
1051+
int64_t distance = dest - pc(); \
1052+
assert(is_valid_32bit_offset(distance), "Must be"); \
10491053
auipc(temp, (int32_t)distance + 0x800); \
10501054
Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
10511055
} else { \
@@ -1089,8 +1093,9 @@ class MacroAssembler: public Assembler {
10891093
#define INSN(NAME) \
10901094
void NAME(FloatRegister Rs, address dest, Register temp = t0) { \
10911095
assert_cond(dest != nullptr); \
1092-
int64_t distance = dest - pc(); \
1093-
if (is_valid_32bit_offset(distance)) { \
1096+
if (CodeCache::contains(dest)) { \
1097+
int64_t distance = dest - pc(); \
1098+
assert(is_valid_32bit_offset(distance), "Must be"); \
10941099
auipc(temp, (int32_t)distance + 0x800); \
10951100
Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
10961101
} else { \
@@ -1613,19 +1618,6 @@ class MacroAssembler: public Assembler {
16131618

16141619
void repne_scan(Register addr, Register value, Register count, Register tmp);
16151620

1616-
void ld_constant(Register dest, const Address &const_addr) {
1617-
if (NearCpool) {
1618-
ld(dest, const_addr);
1619-
} else {
1620-
InternalAddress target(const_addr.target());
1621-
relocate(target.rspec(), [&] {
1622-
int32_t offset;
1623-
la(dest, target.target(), offset);
1624-
ld(dest, Address(dest, offset));
1625-
});
1626-
}
1627-
}
1628-
16291621
int bitset_to_regs(unsigned int bitset, unsigned char* regs);
16301622
Address add_memory_helper(const Address dst, Register tmp);
16311623

‎src/hotspot/cpu/riscv/riscv.ad

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1266,8 +1266,7 @@ int MachCallRuntimeNode::ret_addr_offset() {
12661266
// sd(t0, Address(sp, wordSize)) -> sd
12671267
// movptr(t1, addr, offset, t0) -> lui + lui + slli + add
12681268
// jalr(t1, offset) -> jalr
1269-
CodeBlob *cb = CodeCache::find_blob(_entry_point);
1270-
if (cb != nullptr) {
1269+
if (CodeCache::contains(_entry_point)) {
12711270
if (UseTrampolines) {
12721271
return 1 * NativeInstruction::instruction_size;
12731272
}
@@ -2494,8 +2493,7 @@ encode %{
24942493
// will be in a reachable segment) otherwise we have to use a jalr
24952494
// which loads the absolute address into a register.
24962495
address entry = (address)$meth$$method;
2497-
CodeBlob *cb = CodeCache::find_blob(entry);
2498-
if (cb != nullptr) {
2496+
if (CodeCache::contains(entry)) {
24992497
address call = __ reloc_call(Address(entry, relocInfo::runtime_call_type));
25002498
if (call == nullptr) {
25012499
ciEnv::current()->record_failure("CodeCache is full");

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