8299525: RISC-V: Add backend support for half float conversion intrinsics

Reviewed-by: fyang, fjiang

Author: Yadong Wang

src/hotspot/cpu/riscv/assembler_riscv.hpp

@@ -798,6 +798,8 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   INSN(fsqrt_d,  0b1010011, 0b00000, 0b0101101);
   INSN(fcvt_s_d, 0b1010011, 0b00001, 0b0100000);
   INSN(fcvt_d_s, 0b1010011, 0b00000, 0b0100001);
+  INSN(fcvt_s_h, 0b1010011, 0b00010, 0b0100000);
+  INSN(fcvt_h_s, 0b1010011, 0b00000, 0b0100010);
 #undef INSN
 
 // Immediate Instruction
@@ -1054,6 +1056,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
 
   INSN(fmv_w_x,  0b1010011, 0b000, 0b00000, 0b1111000);
   INSN(fmv_d_x,  0b1010011, 0b000, 0b00000, 0b1111001);
+  INSN(fmv_h_x,  0b1010011, 0b000, 0b00000, 0b1111010);
 
 #undef INSN
 
@@ -1074,6 +1077,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
   INSN(fclass_d, 0b1010011, 0b001, 0b00000, 0b1110001);
   INSN(fmv_x_w,  0b1010011, 0b000, 0b00000, 0b1110000);
   INSN(fmv_x_d,  0b1010011, 0b000, 0b00000, 0b1110001);
+  INSN(fmv_x_h,  0b1010011, 0b000, 0b00000, 0b1110010);
 
 #undef INSN
 

src/hotspot/cpu/riscv/globals_riscv.hpp

@@ -103,6 +103,7 @@ define_pd_global(intx, InlineSmallCode,          1000);
   product(bool, UseZba, false, EXPERIMENTAL, "Use Zba instructions")             \
   product(bool, UseZbb, false, EXPERIMENTAL, "Use Zbb instructions")             \
   product(bool, UseZbs, false, EXPERIMENTAL, "Use Zbs instructions")             \
+  product(bool, UseZfhmin, false, EXPERIMENTAL, "Use Zfhmin instructions")       \
   product(bool, UseZic64b, false, EXPERIMENTAL, "Use Zic64b instructions")       \
   product(bool, UseZicbom, false, EXPERIMENTAL, "Use Zicbom instructions")       \
   product(bool, UseZicbop, false, EXPERIMENTAL, "Use Zicbop instructions")       \

src/hotspot/cpu/riscv/riscv.ad

@@ -1842,6 +1842,10 @@ const bool Matcher::match_rule_supported(int opcode) {
     case Op_CountTrailingZerosI:
     case Op_CountTrailingZerosL:
       return UseZbb;
+
+    case Op_ConvF2HF:
+    case Op_ConvHF2F:
+      return UseZfhmin;
   }
 
   return true; // Per default match rules are supported.
@@ -8135,6 +8139,44 @@ instruct convL2F_reg_reg(fRegF dst, iRegL src) %{
   ins_pipe(fp_l2f);
 %}
 
+// float <-> half float
+
+instruct convHF2F_reg_reg(fRegF dst, iRegINoSp src, fRegF tmp) %{
+  predicate(UseZfhmin);
+  match(Set dst (ConvHF2F src));
+  effect(TEMP tmp);
+
+  ins_cost(XFER_COST);
+  format %{ "fmv.h.x $tmp, $src\t#@convHF2F_reg_reg\n\t"
+            "fcvt.s.h $dst, $tmp\t#@convHF2F_reg_reg"
+  %}
+
+  ins_encode %{
+    __ fmv_h_x($tmp$$FloatRegister, $src$$Register);
+    __ fcvt_s_h($dst$$FloatRegister, $tmp$$FloatRegister);
+  %}
+
+  ins_pipe(fp_i2f);
+%}
+
+instruct convF2HF_reg_reg(iRegINoSp dst, fRegF src, fRegF tmp) %{
+  predicate(UseZfhmin);
+  match(Set dst (ConvF2HF src));
+  effect(TEMP tmp);
+
+  ins_cost(XFER_COST);
+  format %{ "fcvt.h.s $tmp, $src\t#@convF2HF_reg_reg\n\t"
+            "fmv.x.h $dst, $tmp\t#@convF2HF_reg_reg"
+  %}
+
+  ins_encode %{
+    __ fcvt_h_s($tmp$$FloatRegister, $src$$FloatRegister);
+    __ fmv_x_h($dst$$Register, $tmp$$FloatRegister);
+  %}
+
+  ins_pipe(fp_f2i);
+%}
+
 // double <-> int
 
 instruct convD2I_reg_reg(iRegINoSp dst, fRegD src) %{

src/hotspot/cpu/riscv/vm_version_riscv.cpp

@@ -59,6 +59,9 @@ void VM_Version::initialize() {
     if (FLAG_IS_DEFAULT(UseZbb)) {
       FLAG_SET_DEFAULT(UseZbb, true);
     }
+    if (FLAG_IS_DEFAULT(UseZbs)) {
+      FLAG_SET_DEFAULT(UseZbs, true);
+    }
     if (FLAG_IS_DEFAULT(UseZic64b)) {
       FLAG_SET_DEFAULT(UseZic64b, true);
     }
@@ -71,6 +74,9 @@ void VM_Version::initialize() {
     if (FLAG_IS_DEFAULT(UseZicboz)) {
       FLAG_SET_DEFAULT(UseZicboz, true);
     }
+    if (FLAG_IS_DEFAULT(UseZfhmin)) {
+      FLAG_SET_DEFAULT(UseZfhmin, true);
+    }
   }
 
   if (UseZic64b) {