@@ -4640,29 +4640,9 @@ instruct reduction64B(rRegI dst, rRegI src1, legVec src2, legVec vtmp1, legVec v
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// =======================Short Reduction==========================================
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- instruct reductionS(rRegI dst, rRegI src1, vec src2, vec vtmp1, vec vtmp2) %{
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+ instruct reductionS(rRegI dst, rRegI src1, legVec src2, legVec vtmp1, legVec vtmp2) %{
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predicate(vector_element_basic_type(n->in(2)) == T_SHORT &&
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- vector_length(n->in(2)) <= 16); // src2
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- match(Set dst (AddReductionVI src1 src2));
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- match(Set dst (MulReductionVI src1 src2));
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- match(Set dst (AndReductionV src1 src2));
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- match(Set dst ( OrReductionV src1 src2));
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- match(Set dst (XorReductionV src1 src2));
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- match(Set dst (MinReductionV src1 src2));
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- match(Set dst (MaxReductionV src1 src2));
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- effect(TEMP vtmp1, TEMP vtmp2);
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- format %{ "vector_reduction_short $dst,$src1,$src2 ; using $vtmp1, $vtmp2 as TEMP" %}
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- ins_encode %{
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- int opcode = this->ideal_Opcode();
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- int vlen = vector_length(this, $src2);
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- __ reduceS(opcode, vlen, $dst$$Register, $src1$$Register, $src2$$XMMRegister, $vtmp1$$XMMRegister, $vtmp2$$XMMRegister);
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- %}
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- ins_pipe( pipe_slow );
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- %}
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-
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- instruct reduction32S(rRegI dst, rRegI src1, legVec src2, legVec vtmp1, legVec vtmp2) %{
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- predicate(vector_element_basic_type(n->in(2)) == T_SHORT &&
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- vector_length(n->in(2)) == 32); // src2
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+ vector_length(n->in(2)) <= 32); // src2
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match(Set dst (AddReductionVI src1 src2));
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match(Set dst (MulReductionVI src1 src2));
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match(Set dst (AndReductionV src1 src2));
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