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8294261: AArch64: Use pReg instead of pRegGov when possible
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Reviewed-by: ngasson, xgong
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Ningsheng Jian committed Oct 11, 2022
1 parent 891156a commit 4b17d28
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Showing 6 changed files with 86 additions and 97 deletions.
7 changes: 6 additions & 1 deletion src/hotspot/cpu/aarch64/aarch64.ad
Original file line number Diff line number Diff line change
Expand Up @@ -460,15 +460,16 @@ alloc_class chunk1(
);

alloc_class chunk2 (
// Governing predicates for load/store and arithmetic
P0,
P1,
P2,
P3,
P4,
P5,
P6,
P7,

// Extra predicates
P8,
P9,
P10,
Expand All @@ -477,6 +478,9 @@ alloc_class chunk2 (
P13,
P14,
P15,

// Preserved for all-true predicate
P7,
);

alloc_class chunk3(RFLAGS);
Expand Down Expand Up @@ -5538,6 +5542,7 @@ operand pRegGov()
%{
constraint(ALLOC_IN_RC(gov_pr));
match(RegVectMask);
match(pReg);
op_cost(0);
format %{ %}
interface(REG_INTER);
Expand Down
78 changes: 39 additions & 39 deletions src/hotspot/cpu/aarch64/aarch64_vector.ad
Original file line number Diff line number Diff line change
Expand Up @@ -4659,7 +4659,7 @@ instruct vloadmask_neon(vReg dst, vReg src) %{
ins_pipe(pipe_slow);
%}

instruct vloadmaskB_sve(pRegGov dst, vReg src, rFlagsReg cr) %{
instruct vloadmaskB_sve(pReg dst, vReg src, rFlagsReg cr) %{
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) == T_BYTE);
match(Set dst (VectorLoadMask src));
effect(KILL cr);
Expand All @@ -4671,7 +4671,7 @@ instruct vloadmaskB_sve(pRegGov dst, vReg src, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vloadmask_extend_sve(pRegGov dst, vReg src, vReg tmp, rFlagsReg cr) %{
instruct vloadmask_extend_sve(pReg dst, vReg src, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) != T_BYTE);
match(Set dst (VectorLoadMask src));
effect(TEMP tmp, KILL cr);
Expand All @@ -4685,7 +4685,7 @@ instruct vloadmask_extend_sve(pRegGov dst, vReg src, vReg tmp, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vloadmaskB_masked(pRegGov dst, vReg src, pRegGov pg, rFlagsReg cr) %{
instruct vloadmaskB_masked(pReg dst, vReg src, pRegGov pg, rFlagsReg cr) %{
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) == T_BYTE);
match(Set dst (VectorLoadMask src pg));
effect(KILL cr);
Expand All @@ -4697,7 +4697,7 @@ instruct vloadmaskB_masked(pRegGov dst, vReg src, pRegGov pg, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vloadmask_extend_masked(pRegGov dst, vReg src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
instruct vloadmask_extend_masked(pReg dst, vReg src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 && Matcher::vector_element_basic_type(n) != T_BYTE);
match(Set dst (VectorLoadMask src pg));
effect(TEMP tmp, KILL cr);
Expand Down Expand Up @@ -4751,7 +4751,7 @@ instruct vstoremask_narrow_neon(vReg dst, vReg src, immI_gt_1 size) %{

// vector store mask - sve

instruct vstoremaskB_sve(vReg dst, pRegGov src, immI_1 size) %{
instruct vstoremaskB_sve(vReg dst, pReg src, immI_1 size) %{
predicate(UseSVE > 0);
match(Set dst (VectorStoreMask src size));
format %{ "vstoremaskB_sve $dst, $src" %}
Expand All @@ -4761,7 +4761,7 @@ instruct vstoremaskB_sve(vReg dst, pRegGov src, immI_1 size) %{
ins_pipe(pipe_slow);
%}

instruct vstoremask_narrow_sve(vReg dst, pRegGov src, immI_gt_1 size, vReg tmp) %{
instruct vstoremask_narrow_sve(vReg dst, pReg src, immI_gt_1 size, vReg tmp) %{
predicate(UseSVE > 0);
match(Set dst (VectorStoreMask src size));
effect(TEMP_DEF dst, TEMP tmp);
Expand All @@ -4778,7 +4778,7 @@ instruct vstoremask_narrow_sve(vReg dst, pRegGov src, immI_gt_1 size, vReg tmp)
// Combined rules for vector mask load when the vector element type is not T_BYTE

// VectorLoadMask+LoadVector, and the VectorLoadMask is unpredicated.
instruct vloadmask_loadV(pRegGov dst, indirect mem, vReg tmp, rFlagsReg cr) %{
instruct vloadmask_loadV(pReg dst, indirect mem, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
match(Set dst (VectorLoadMask (LoadVector mem)));
Expand All @@ -4800,7 +4800,7 @@ instruct vloadmask_loadV(pRegGov dst, indirect mem, vReg tmp, rFlagsReg cr) %{
%}

// VectorLoadMask+LoadVector, and the VectorLoadMask is predicated.
instruct vloadmask_loadV_masked(pRegGov dst, indirect mem, pRegGov pg,
instruct vloadmask_loadV_masked(pReg dst, indirect mem, pRegGov pg,
vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
Expand All @@ -4821,7 +4821,7 @@ instruct vloadmask_loadV_masked(pRegGov dst, indirect mem, pRegGov pg,
%}

// VectorLoadMask+LoadVectorMasked, and the VectorLoadMask is unpredicated.
instruct vloadmask_loadVMasked(pRegGov dst, vmemA mem, pRegGov pg, vReg tmp, rFlagsReg cr) %{
instruct vloadmask_loadVMasked(pReg dst, vmemA mem, pRegGov pg, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
match(Set dst (VectorLoadMask (LoadVectorMasked mem pg)));
Expand All @@ -4848,7 +4848,7 @@ instruct vloadmask_loadVMasked(pRegGov dst, vmemA mem, pRegGov pg, vReg tmp, rFl
%}

// VectorLoadMask+LoadVectorMasked, and the VectorLoadMask is predicated.
instruct vloadmask_loadVMasked_masked(pRegGov dst, vmemA mem, pRegGov pg1, pRegGov pg2,
instruct vloadmask_loadVMasked_masked(pReg dst, vmemA mem, pRegGov pg1, pRegGov pg2,
vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
type2aelembytes(Matcher::vector_element_basic_type(n)) > 1);
Expand Down Expand Up @@ -4878,7 +4878,7 @@ instruct vloadmask_loadVMasked_masked(pRegGov dst, vmemA mem, pRegGov pg1, pRegG
// Combined rules for vector mask store when the vector element type is not T_BYTE

// StoreVector+VectorStoreMask, and the vector size of "src" is equal to the MaxVectorSize.
instruct storeV_vstoremask(indirect mem, pRegGov src, immI_gt_1 esize, vReg tmp) %{
instruct storeV_vstoremask(indirect mem, pReg src, immI_gt_1 esize, vReg tmp) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n->as_StoreVector()->in(MemNode::ValueIn)->in(1)) == MaxVectorSize);
match(Set mem (StoreVector mem (VectorStoreMask src esize)));
Expand All @@ -4899,7 +4899,7 @@ instruct storeV_vstoremask(indirect mem, pRegGov src, immI_gt_1 esize, vReg tmp)
%}

// StoreVector+VectorStoreMask, and the vector size of "src" is less than the MaxVectorSize.
instruct storeV_vstoremask_masked(indirect mem, pRegGov src, immI_gt_1 esize,
instruct storeV_vstoremask_masked(indirect mem, pReg src, immI_gt_1 esize,
vReg tmp, pRegGov pgtmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n->as_StoreVector()->in(MemNode::ValueIn)->in(1)) < MaxVectorSize);
Expand All @@ -4921,7 +4921,7 @@ instruct storeV_vstoremask_masked(indirect mem, pRegGov src, immI_gt_1 esize,
%}

// StoreVectorMasked+VectorStoreMask, and the vector size of "src" is equal to the MaxVectorSize.
instruct storeVMasked_vstoremask(vmemA mem, pRegGov src, pRegGov pg, immI_gt_1 esize, vReg tmp) %{
instruct storeVMasked_vstoremask(vmemA mem, pReg src, pRegGov pg, immI_gt_1 esize, vReg tmp) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n->as_StoreVector()->in(MemNode::ValueIn)->in(1)) == MaxVectorSize);
match(Set mem (StoreVectorMasked mem (Binary (VectorStoreMask src esize) pg)));
Expand All @@ -4947,7 +4947,7 @@ instruct storeVMasked_vstoremask(vmemA mem, pRegGov src, pRegGov pg, immI_gt_1 e
%}

// StoreVectorMasked+VectorStoreMask, and the vector size of "src" is less than the MaxVectorSize.
instruct storeVMasked_vstoremask_masked(vmemA mem, pRegGov src, pRegGov pg, immI_gt_1 esize,
instruct storeVMasked_vstoremask_masked(vmemA mem, pReg src, pRegGov pg, immI_gt_1 esize,
vReg tmp, pRegGov pgtmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n->as_StoreVector()->in(MemNode::ValueIn)->in(1)) < MaxVectorSize);
Expand Down Expand Up @@ -4977,7 +4977,7 @@ instruct storeVMasked_vstoremask_masked(vmemA mem, pRegGov src, pRegGov pg, immI

// vector mask logical ops: and/or/xor/and_not

instruct vmask_and(pRegGov pd, pRegGov pn, pRegGov pm) %{
instruct vmask_and(pReg pd, pReg pn, pReg pm) %{
predicate(UseSVE > 0);
match(Set pd (AndVMask pn pm));
format %{ "vmask_and $pd, $pn, $pm" %}
Expand All @@ -4987,7 +4987,7 @@ instruct vmask_and(pRegGov pd, pRegGov pn, pRegGov pm) %{
ins_pipe(pipe_slow);
%}

instruct vmask_or(pRegGov pd, pRegGov pn, pRegGov pm) %{
instruct vmask_or(pReg pd, pReg pn, pReg pm) %{
predicate(UseSVE > 0);
match(Set pd (OrVMask pn pm));
format %{ "vmask_or $pd, $pn, $pm" %}
Expand All @@ -4997,7 +4997,7 @@ instruct vmask_or(pRegGov pd, pRegGov pn, pRegGov pm) %{
ins_pipe(pipe_slow);
%}

instruct vmask_xor(pRegGov pd, pRegGov pn, pRegGov pm) %{
instruct vmask_xor(pReg pd, pReg pn, pReg pm) %{
predicate(UseSVE > 0);
match(Set pd (XorVMask pn pm));
format %{ "vmask_xor $pd, $pn, $pm" %}
Expand All @@ -5007,7 +5007,7 @@ instruct vmask_xor(pRegGov pd, pRegGov pn, pRegGov pm) %{
ins_pipe(pipe_slow);
%}

instruct vmask_and_notI(pRegGov pd, pRegGov pn, pRegGov pm, immI_M1 m1) %{
instruct vmask_and_notI(pReg pd, pReg pn, pReg pm, immI_M1 m1) %{
predicate(UseSVE > 0);
match(Set pd (AndVMask pn (XorVMask pm (MaskAll m1))));
format %{ "vmask_and_notI $pd, $pn, $pm" %}
Expand All @@ -5017,7 +5017,7 @@ instruct vmask_and_notI(pRegGov pd, pRegGov pn, pRegGov pm, immI_M1 m1) %{
ins_pipe(pipe_slow);
%}

instruct vmask_and_notL(pRegGov pd, pRegGov pn, pRegGov pm, immL_M1 m1) %{
instruct vmask_and_notL(pReg pd, pReg pn, pReg pm, immL_M1 m1) %{
predicate(UseSVE > 0);
match(Set pd (AndVMask pn (XorVMask pm (MaskAll m1))));
format %{ "vmask_and_notL $pd, $pn, $pm" %}
Expand Down Expand Up @@ -5045,7 +5045,7 @@ instruct vmaskcmp_neon(vReg dst, vReg src1, vReg src2, immI cond) %{
ins_pipe(pipe_slow);
%}

instruct vmaskcmp_sve(pRegGov dst, vReg src1, vReg src2, immI cond, rFlagsReg cr) %{
instruct vmaskcmp_sve(pReg dst, vReg src1, vReg src2, immI cond, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
effect(KILL cr);
Expand All @@ -5060,7 +5060,7 @@ instruct vmaskcmp_sve(pRegGov dst, vReg src1, vReg src2, immI cond, rFlagsReg cr
ins_pipe(pipe_slow);
%}

instruct vmaskcmp_masked(pRegGov dst, vReg src1, vReg src2, immI cond,
instruct vmaskcmp_masked(pReg dst, vReg src1, vReg src2, immI cond,
pRegGov pg, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (VectorMaskCmp (Binary src1 src2) (Binary cond pg)));
Expand All @@ -5087,7 +5087,7 @@ instruct vmaskcast_same_esize_neon(vReg dst_src) %{
ins_pipe(pipe_class_empty);
%}

instruct vmaskcast_same_esize_sve(pRegGov dst_src) %{
instruct vmaskcast_same_esize_sve(pReg dst_src) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1)));
match(Set dst_src (VectorMaskCast dst_src));
Expand All @@ -5097,7 +5097,7 @@ instruct vmaskcast_same_esize_sve(pRegGov dst_src) %{
ins_pipe(pipe_class_empty);
%}

instruct vmaskcast_extend(pRegGov dst, pReg src) %{
instruct vmaskcast_extend(pReg dst, pReg src) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n) > Matcher::vector_length_in_bytes(n->in(1)));
match(Set dst (VectorMaskCast src));
Expand All @@ -5114,7 +5114,7 @@ instruct vmaskcast_extend(pRegGov dst, pReg src) %{
ins_pipe(pipe_slow);
%}

instruct vmaskcast_narrow(pRegGov dst, pReg src) %{
instruct vmaskcast_narrow(pReg dst, pReg src) %{
predicate(UseSVE > 0 &&
Matcher::vector_length_in_bytes(n) < Matcher::vector_length_in_bytes(n->in(1)));
match(Set dst (VectorMaskCast src));
Expand All @@ -5133,7 +5133,7 @@ instruct vmaskcast_narrow(pRegGov dst, pReg src) %{

// vector mask reinterpret

instruct vmask_reinterpret_same_esize(pRegGov dst_src) %{
instruct vmask_reinterpret_same_esize(pReg dst_src) %{
predicate(UseSVE > 0 &&
Matcher::vector_length(n) == Matcher::vector_length(n->in(1)) &&
Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1)));
Expand All @@ -5144,7 +5144,7 @@ instruct vmask_reinterpret_same_esize(pRegGov dst_src) %{
ins_pipe(pipe_class_empty);
%}

instruct vmask_reinterpret_diff_esize(pRegGov dst, pRegGov src, vReg tmp, rFlagsReg cr) %{
instruct vmask_reinterpret_diff_esize(pReg dst, pReg src, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
Matcher::vector_length(n) != Matcher::vector_length(n->in(1)) &&
Matcher::vector_length_in_bytes(n) == Matcher::vector_length_in_bytes(n->in(1)));
Expand Down Expand Up @@ -5290,7 +5290,7 @@ instruct vmask_firsttrue_sve(iRegINoSp dst, pReg src, pReg ptmp) %{
ins_pipe(pipe_slow);
%}

instruct vmask_firsttrue_masked(iRegINoSp dst, pReg src, pRegGov pg, pReg ptmp) %{
instruct vmask_firsttrue_masked(iRegINoSp dst, pReg src, pReg pg, pReg ptmp) %{
predicate(UseSVE > 0);
match(Set dst (VectorMaskFirstTrue src pg));
effect(TEMP ptmp);
Expand Down Expand Up @@ -5402,7 +5402,7 @@ instruct vmask_tolong_sve(iRegLNoSp dst, pReg src, vReg tmp1, vReg tmp2) %{

// fromlong

instruct vmask_fromlong(pRegGov dst, iRegL src, vReg tmp1, vReg tmp2) %{
instruct vmask_fromlong(pReg dst, iRegL src, vReg tmp1, vReg tmp2) %{
match(Set dst (VectorLongToMask src));
effect(TEMP tmp1, TEMP tmp2);
format %{ "vmask_fromlong $dst, $src\t# vector (sve2). KILL $tmp1, $tmp2" %}
Expand All @@ -5419,7 +5419,7 @@ instruct vmask_fromlong(pRegGov dst, iRegL src, vReg tmp1, vReg tmp2) %{

// maskAll

instruct vmaskAll_immI(pRegGov dst, immI src, rFlagsReg cr) %{
instruct vmaskAll_immI(pReg dst, immI src, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src));
effect(KILL cr);
Expand All @@ -5437,7 +5437,7 @@ instruct vmaskAll_immI(pRegGov dst, immI src, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vmaskAllI(pRegGov dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
instruct vmaskAllI(pReg dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src));
effect(TEMP tmp, KILL cr);
Expand All @@ -5453,7 +5453,7 @@ instruct vmaskAllI(pRegGov dst, iRegIorL2I src, vReg tmp, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vmaskAllI_masked(pRegGov dst, iRegIorL2I src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
instruct vmaskAllI_masked(pReg dst, iRegIorL2I src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src pg));
effect(TEMP tmp, KILL cr);
Expand All @@ -5468,7 +5468,7 @@ instruct vmaskAllI_masked(pRegGov dst, iRegIorL2I src, pRegGov pg, vReg tmp, rFl
ins_pipe(pipe_slow);
%}

instruct vmaskAll_immL(pRegGov dst, immL src, rFlagsReg cr) %{
instruct vmaskAll_immL(pReg dst, immL src, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src));
effect(KILL cr);
Expand All @@ -5486,7 +5486,7 @@ instruct vmaskAll_immL(pRegGov dst, immL src, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vmaskAllL(pRegGov dst, iRegL src, vReg tmp, rFlagsReg cr) %{
instruct vmaskAllL(pReg dst, iRegL src, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src));
effect(TEMP tmp, KILL cr);
Expand All @@ -5502,7 +5502,7 @@ instruct vmaskAllL(pRegGov dst, iRegL src, vReg tmp, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vmaskAllL_masked(pRegGov dst, iRegL src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
instruct vmaskAllL_masked(pReg dst, iRegL src, pRegGov pg, vReg tmp, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set dst (MaskAll src pg));
effect(TEMP tmp, KILL cr);
Expand All @@ -5519,7 +5519,7 @@ instruct vmaskAllL_masked(pRegGov dst, iRegL src, pRegGov pg, vReg tmp, rFlagsRe

// vetcor mask generation

instruct vmask_gen_I(pRegGov pd, iRegIorL2I src, rFlagsReg cr) %{
instruct vmask_gen_I(pReg pd, iRegIorL2I src, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set pd (VectorMaskGen (ConvI2L src)));
effect(KILL cr);
Expand All @@ -5531,7 +5531,7 @@ instruct vmask_gen_I(pRegGov pd, iRegIorL2I src, rFlagsReg cr) %{
ins_pipe(pipe_class_default);
%}

instruct vmask_gen_L(pRegGov pd, iRegL src, rFlagsReg cr) %{
instruct vmask_gen_L(pReg pd, iRegL src, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set pd (VectorMaskGen src));
effect(KILL cr);
Expand All @@ -5543,7 +5543,7 @@ instruct vmask_gen_L(pRegGov pd, iRegL src, rFlagsReg cr) %{
ins_pipe(pipe_slow);
%}

instruct vmask_gen_imm(pRegGov pd, immL con, rFlagsReg cr) %{
instruct vmask_gen_imm(pReg pd, immL con, rFlagsReg cr) %{
predicate(UseSVE > 0);
match(Set pd (VectorMaskGen con));
effect(KILL cr);
Expand Down Expand Up @@ -5837,7 +5837,7 @@ instruct vtest_anytrue_neon(iRegINoSp dst, vReg src1, vReg src2, vReg tmp, rFlag
ins_pipe(pipe_slow);
%}

instruct vtest_anytrue_sve(iRegINoSp dst, pRegGov src1, pRegGov src2, rFlagsReg cr) %{
instruct vtest_anytrue_sve(iRegINoSp dst, pReg src1, pReg src2, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
match(Set dst (VectorTest src1 src2));
Expand Down Expand Up @@ -5871,7 +5871,7 @@ instruct vtest_alltrue_neon(iRegINoSp dst, vReg src1, vReg src2, vReg tmp, rFlag
ins_pipe(pipe_slow);
%}

instruct vtest_alltrue_sve(iRegINoSp dst, pRegGov src1, pRegGov src2, pReg ptmp, rFlagsReg cr) %{
instruct vtest_alltrue_sve(iRegINoSp dst, pReg src1, pReg src2, pReg ptmp, rFlagsReg cr) %{
predicate(UseSVE > 0 &&
static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
match(Set dst (VectorTest src1 src2));
Expand Down

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