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feilongjiangRealFYang
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8296435: RISC-V: Small refactoring for increment/decrement
Reviewed-by: fyang
1 parent 47d2c7b commit 4c80dff

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3 files changed

+36
-42
lines changed

3 files changed

+36
-42
lines changed

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -3271,60 +3271,60 @@ address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
32713271
return stub_start_addr;
32723272
}
32733273

3274-
Address MacroAssembler::add_memory_helper(const Address dst) {
3274+
Address MacroAssembler::add_memory_helper(const Address dst, Register tmp) {
32753275
switch (dst.getMode()) {
32763276
case Address::base_plus_offset:
32773277
// This is the expected mode, although we allow all the other
32783278
// forms below.
3279-
return form_address(t1, dst.base(), dst.offset());
3279+
return form_address(tmp, dst.base(), dst.offset());
32803280
default:
3281-
la(t1, dst);
3282-
return Address(t1);
3281+
la(tmp, dst);
3282+
return Address(tmp);
32833283
}
32843284
}
32853285

3286-
void MacroAssembler::increment(const Address dst, int64_t value) {
3286+
void MacroAssembler::increment(const Address dst, int64_t value, Register tmp1, Register tmp2) {
32873287
assert(((dst.getMode() == Address::base_plus_offset &&
32883288
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
32893289
"invalid value and address mode combination");
3290-
Address adr = add_memory_helper(dst);
3291-
assert(!adr.uses(t0), "invalid dst for address increment");
3292-
ld(t0, adr);
3293-
add(t0, t0, value, t1);
3294-
sd(t0, adr);
3290+
Address adr = add_memory_helper(dst, tmp2);
3291+
assert(!adr.uses(tmp1), "invalid dst for address increment");
3292+
ld(tmp1, adr);
3293+
add(tmp1, tmp1, value, tmp2);
3294+
sd(tmp1, adr);
32953295
}
32963296

3297-
void MacroAssembler::incrementw(const Address dst, int32_t value) {
3297+
void MacroAssembler::incrementw(const Address dst, int32_t value, Register tmp1, Register tmp2) {
32983298
assert(((dst.getMode() == Address::base_plus_offset &&
32993299
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
33003300
"invalid value and address mode combination");
3301-
Address adr = add_memory_helper(dst);
3302-
assert(!adr.uses(t0), "invalid dst for address increment");
3303-
lwu(t0, adr);
3304-
addw(t0, t0, value, t1);
3305-
sw(t0, adr);
3301+
Address adr = add_memory_helper(dst, tmp2);
3302+
assert(!adr.uses(tmp1), "invalid dst for address increment");
3303+
lwu(tmp1, adr);
3304+
addw(tmp1, tmp1, value, tmp2);
3305+
sw(tmp1, adr);
33063306
}
33073307

3308-
void MacroAssembler::decrement(const Address dst, int64_t value) {
3308+
void MacroAssembler::decrement(const Address dst, int64_t value, Register tmp1, Register tmp2) {
33093309
assert(((dst.getMode() == Address::base_plus_offset &&
33103310
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
33113311
"invalid value and address mode combination");
3312-
Address adr = add_memory_helper(dst);
3313-
assert(!adr.uses(t0), "invalid dst for address decrement");
3314-
ld(t0, adr);
3315-
sub(t0, t0, value, t1);
3316-
sd(t0, adr);
3312+
Address adr = add_memory_helper(dst, tmp2);
3313+
assert(!adr.uses(tmp1), "invalid dst for address decrement");
3314+
ld(tmp1, adr);
3315+
sub(tmp1, tmp1, value, tmp2);
3316+
sd(tmp1, adr);
33173317
}
33183318

3319-
void MacroAssembler::decrementw(const Address dst, int32_t value) {
3319+
void MacroAssembler::decrementw(const Address dst, int32_t value, Register tmp1, Register tmp2) {
33203320
assert(((dst.getMode() == Address::base_plus_offset &&
33213321
is_offset_in_range(dst.offset(), 12)) || is_imm_in_range(value, 12, 0)),
33223322
"invalid value and address mode combination");
3323-
Address adr = add_memory_helper(dst);
3324-
assert(!adr.uses(t0), "invalid dst for address decrement");
3325-
lwu(t0, adr);
3326-
subw(t0, t0, value, t1);
3327-
sw(t0, adr);
3323+
Address adr = add_memory_helper(dst, tmp2);
3324+
assert(!adr.uses(tmp1), "invalid dst for address decrement");
3325+
lwu(tmp1, adr);
3326+
subw(tmp1, tmp1, value, tmp2);
3327+
sw(tmp1, adr);
33283328
}
33293329

33303330
void MacroAssembler::cmpptr(Register src1, Address src2, Label& equal) {

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1054,11 +1054,11 @@ class MacroAssembler: public Assembler {
10541054
// to use a 2nd scratch register to hold the constant. so, an address
10551055
// increment/decrement may trash both t0 and t1.
10561056

1057-
void increment(const Address dst, int64_t value = 1);
1058-
void incrementw(const Address dst, int32_t value = 1);
1057+
void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1058+
void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
10591059

1060-
void decrement(const Address dst, int64_t value = 1);
1061-
void decrementw(const Address dst, int32_t value = 1);
1060+
void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1061+
void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
10621062

10631063
void cmpptr(Register src1, Address src2, Label& equal);
10641064

@@ -1272,7 +1272,7 @@ class MacroAssembler: public Assembler {
12721272
}
12731273

12741274
int bitset_to_regs(unsigned int bitset, unsigned char* regs);
1275-
Address add_memory_helper(const Address dst);
1275+
Address add_memory_helper(const Address dst, Register tmp);
12761276

12771277
void load_reserved(Register addr, enum operand_size size, Assembler::Aqrl acquire);
12781278
void store_conditional(Register addr, Register new_val, enum operand_size size, Assembler::Aqrl release);

src/hotspot/cpu/riscv/riscv.ad

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2450,17 +2450,13 @@ encode %{
24502450

24512451
// Recursive lock case
24522452
__ mv(flag, zr);
2453-
__ ld(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2454-
__ add(tmp, tmp, 1);
2455-
__ sd(tmp, Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value));
2453+
__ increment(Address(disp_hdr, ObjectMonitor::recursions_offset_in_bytes() - markWord::monitor_value), 1, t0, tmp);
24562454

24572455
__ bind(cont);
24582456

24592457
__ bnez(flag, no_count);
24602458

2461-
__ ld(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
2462-
__ add(tmp, tmp, 1);
2463-
__ sd(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
2459+
__ increment(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
24642460

24652461
__ bind(no_count);
24662462
%}
@@ -2537,9 +2533,7 @@ encode %{
25372533

25382534
__ bnez(flag, no_count);
25392535

2540-
__ ld(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
2541-
__ sub(tmp, tmp, 1);
2542-
__ sd(tmp, Address(xthread, JavaThread::held_monitor_count_offset()));
2536+
__ decrement(Address(xthread, JavaThread::held_monitor_count_offset()), 1, t0, tmp);
25432537

25442538
__ bind(no_count);
25452539
%}

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