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8319716: RISC-V: Add SHA-2
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Co-authored-by: Robbin Ehn <rehn@openjdk.org>
Reviewed-by: fyang, mli, luhenry
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@luhenry @robehn
luhenry and robehn committed Jan 9, 2024
1 parent 7286f52 commit 4cf131a
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Showing 5 changed files with 516 additions and 19 deletions.
77 changes: 73 additions & 4 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1334,6 +1334,7 @@ enum VectorMask {
INSN(vsll_vi, 0b1010111, 0b011, 0b100101);

// Vector Slide Instructions
INSN(vslideup_vi, 0b1010111, 0b011, 0b001110);
INSN(vslidedown_vi, 0b1010111, 0b011, 0b001111);

#undef INSN
Expand Down Expand Up @@ -1689,7 +1690,6 @@ enum VectorMask {
INSN(vmv_v_x, 0b1010111, 0b100, v0, 0b1, 0b010111);

#undef INSN
#undef patch_VArith

#define INSN(NAME, op, funct13, funct6) \
void NAME(VectorRegister Vd, VectorMask vm = unmasked) { \
Expand Down Expand Up @@ -1731,14 +1731,29 @@ enum Nf {
patch_reg((address)&insn, 15, Rs1); \
emit(insn)

#define INSN(NAME, op, lumop, vm, mop, nf) \
void NAME(VectorRegister Vd, Register Rs1, uint32_t width = 0, bool mew = false) { \
#define INSN(NAME, op, width, lumop, vm, mop, mew, nf) \
void NAME(VectorRegister Vd, Register Rs1) { \
guarantee(is_uimm3(width), "width is invalid"); \
patch_VLdSt(op, Vd, width, Rs1, lumop, vm, mop, mew, nf); \
}

// Vector Load/Store Instructions
INSN(vl1re8_v, 0b0000111, 0b01000, 0b1, 0b00, g1);
INSN(vl1re8_v, 0b0000111, 0b000, 0b01000, 0b1, 0b00, 0b0, g1);
INSN(vl1re16_v, 0b0000111, 0b101, 0b01000, 0b1, 0b00, 0b0, g1);
INSN(vl1re32_v, 0b0000111, 0b110, 0b01000, 0b1, 0b00, 0b0, g1);
INSN(vl1re64_v, 0b0000111, 0b111, 0b01000, 0b1, 0b00, 0b0, g1);
INSN(vl2re8_v, 0b0000111, 0b000, 0b01000, 0b1, 0b00, 0b0, g2);
INSN(vl2re16_v, 0b0000111, 0b101, 0b01000, 0b1, 0b00, 0b0, g2);
INSN(vl2re32_v, 0b0000111, 0b110, 0b01000, 0b1, 0b00, 0b0, g2);
INSN(vl2re64_v, 0b0000111, 0b111, 0b01000, 0b1, 0b00, 0b0, g2);
INSN(vl4re8_v, 0b0000111, 0b000, 0b01000, 0b1, 0b00, 0b0, g4);
INSN(vl4re16_v, 0b0000111, 0b101, 0b01000, 0b1, 0b00, 0b0, g4);
INSN(vl4re32_v, 0b0000111, 0b110, 0b01000, 0b1, 0b00, 0b0, g4);
INSN(vl4re64_v, 0b0000111, 0b111, 0b01000, 0b1, 0b00, 0b0, g4);
INSN(vl8re8_v, 0b0000111, 0b000, 0b01000, 0b1, 0b00, 0b0, g8);
INSN(vl8re16_v, 0b0000111, 0b101, 0b01000, 0b1, 0b00, 0b0, g8);
INSN(vl8re32_v, 0b0000111, 0b110, 0b01000, 0b1, 0b00, 0b0, g8);
INSN(vl8re64_v, 0b0000111, 0b111, 0b01000, 0b1, 0b00, 0b0, g8);

#undef INSN

Expand All @@ -1749,6 +1764,9 @@ enum Nf {

// Vector Load/Store Instructions
INSN(vs1r_v, 0b0100111, 0b000, 0b01000, 0b1, 0b00, 0b0, g1);
INSN(vs2r_v, 0b0100111, 0b000, 0b01000, 0b1, 0b00, 0b0, g2);
INSN(vs4r_v, 0b0100111, 0b000, 0b01000, 0b1, 0b00, 0b0, g4);
INSN(vs8r_v, 0b0100111, 0b000, 0b01000, 0b1, 0b00, 0b0, g8);

#undef INSN

Expand Down Expand Up @@ -1794,9 +1812,11 @@ enum Nf {
}

// Vector unordered indexed load instructions
INSN( vluxei8_v, 0b0000111, 0b000, 0b01, 0b0);
INSN(vluxei32_v, 0b0000111, 0b110, 0b01, 0b0);

// Vector unordered indexed store instructions
INSN( vsuxei8_v, 0b0100111, 0b000, 0b01, 0b0);
INSN(vsuxei32_v, 0b0100111, 0b110, 0b01, 0b0);

#undef INSN
Expand All @@ -1820,6 +1840,55 @@ enum Nf {
#undef INSN
#undef patch_VLdSt

// ====================================
// RISC-V Vector Crypto Extension
// ====================================

#define INSN(NAME, op, funct3, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, VectorRegister Vs1, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}

// Vector Bit-manipulation used in Cryptography (Zvkb) Extension
INSN(vandn_vv, 0b1010111, 0b000, 0b000001);
INSN(vandn_vx, 0b1010111, 0b100, 0b000001);
INSN(vandn_vi, 0b1010111, 0b011, 0b000001);
INSN(vclmul_vv, 0b1010111, 0b010, 0b001100);
INSN(vclmul_vx, 0b1010111, 0b110, 0b001100);
INSN(vclmulh_vv, 0b1010111, 0b010, 0b001101);
INSN(vclmulh_vx, 0b1010111, 0b110, 0b001101);
INSN(vror_vv, 0b1010111, 0b000, 0b010100);
INSN(vror_vx, 0b1010111, 0b100, 0b010100);
INSN(vrol_vv, 0b1010111, 0b000, 0b010101);
INSN(vrol_vx, 0b1010111, 0b100, 0b010101);

#undef INSN

#define INSN(NAME, op, funct3, Vs1, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, VectorMask vm = unmasked) { \
patch_VArith(op, Vd, funct3, Vs1, Vs2, vm, funct6); \
}

// Vector Bit-manipulation used in Cryptography (Zvkb) Extension
INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010);
INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010);

#undef INSN

#define INSN(NAME, op, funct3, vm, funct6) \
void NAME(VectorRegister Vd, VectorRegister Vs2, VectorRegister Vs1) { \
patch_VArith(op, Vd, funct3, Vs1->raw_encoding(), Vs2, vm, funct6); \
}

// Vector SHA-2 Secure Hash (Zvknh[ab]) Extension
INSN(vsha2ms_vv, 0b1110111, 0b010, 0b1, 0b101101);
INSN(vsha2ch_vv, 0b1110111, 0b010, 0b1, 0b101110);
INSN(vsha2cl_vv, 0b1110111, 0b010, 0b1, 0b101111);

#undef INSN

#undef patch_VArith

// ====================================
// RISC-V Bit-Manipulation Extension
// Currently only support Zba, Zbb and Zbs bitmanip extensions.
Expand Down
2 changes: 2 additions & 0 deletions src/hotspot/cpu/riscv/globals_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -113,6 +113,8 @@ define_pd_global(intx, InlineSmallCode, 1000);
product(bool, UseZtso, false, EXPERIMENTAL, "Assume Ztso memory model") \
product(bool, UseZihintpause, false, EXPERIMENTAL, \
"Use Zihintpause instructions") \
product(bool, UseZvkn, false, EXPERIMENTAL, \
"Use Zvkn group extension, Zvkned, Zvknhb, Zvkb, Zvkt") \
product(bool, UseRVVForBigIntegerShiftIntrinsics, true, \
"Use RVV instructions for left/right shift of BigInteger")

Expand Down
14 changes: 14 additions & 0 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1361,6 +1361,16 @@ class MacroAssembler: public Assembler {
vmfle_vv(vd, vs1, vs2, vm);
}

inline void vmsltu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
guarantee(imm >= 1 && imm <= 16, "imm is invalid");
vmsleu_vi(Vd, Vs2, imm-1, vm);
}

inline void vmsgeu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
guarantee(imm >= 1 && imm <= 16, "imm is invalid");
vmsgtu_vi(Vd, Vs2, imm-1, vm);
}

// Copy mask register
inline void vmmv_m(VectorRegister vd, VectorRegister vs) {
vmand_mm(vd, vs, vs);
Expand All @@ -1376,6 +1386,10 @@ class MacroAssembler: public Assembler {
vmxnor_mm(vd, vd, vd);
}

inline void vnot_v(VectorRegister Vd, VectorRegister Vs, VectorMask vm = unmasked) {
vxor_vi(Vd, Vs, -1, vm);
}

static const int zero_words_block_size;

void cast_primitive_type(BasicType type, Register Rt) {
Expand Down
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