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8327716: RISC-V: Change type of vector_length param of several assemb…
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…ler functions from int to uint

Reviewed-by: fyang
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@zifeihan @RealFYang
zifeihan authored and RealFYang committed Mar 12, 2024
1 parent 586396c commit 4d6235e
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Showing 3 changed files with 23 additions and 23 deletions.
18 changes: 9 additions & 9 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2621,7 +2621,7 @@ void C2_MacroAssembler::string_indexof_char_v(Register str1, Register cnt1,

// Set dst to NaN if any NaN input.
void C2_MacroAssembler::minmax_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2,
BasicType bt, bool is_min, int vector_length) {
BasicType bt, bool is_min, uint vector_length) {
assert_different_registers(dst, src1, src2);

vsetvli_helper(bt, vector_length);
Expand All @@ -2640,7 +2640,7 @@ void C2_MacroAssembler::minmax_fp_v(VectorRegister dst, VectorRegister src1, Vec
// are handled with a mask-undisturbed policy.
void C2_MacroAssembler::minmax_fp_masked_v(VectorRegister dst, VectorRegister src1, VectorRegister src2,
VectorRegister vmask, VectorRegister tmp1, VectorRegister tmp2,
BasicType bt, bool is_min, int vector_length) {
BasicType bt, bool is_min, uint vector_length) {
assert_different_registers(src1, src2, tmp1, tmp2);
vsetvli_helper(bt, vector_length);

Expand All @@ -2663,7 +2663,7 @@ void C2_MacroAssembler::minmax_fp_masked_v(VectorRegister dst, VectorRegister sr
void C2_MacroAssembler::reduce_minmax_fp_v(FloatRegister dst,
FloatRegister src1, VectorRegister src2,
VectorRegister tmp1, VectorRegister tmp2,
bool is_double, bool is_min, int vector_length, VectorMask vm) {
bool is_double, bool is_min, uint vector_length, VectorMask vm) {
assert_different_registers(dst, src1);
assert_different_registers(src2, tmp1, tmp2);

Expand Down Expand Up @@ -2708,7 +2708,7 @@ bool C2_MacroAssembler::in_scratch_emit_size() {

void C2_MacroAssembler::reduce_integral_v(Register dst, Register src1,
VectorRegister src2, VectorRegister tmp,
int opc, BasicType bt, int vector_length, VectorMask vm) {
int opc, BasicType bt, uint vector_length, VectorMask vm) {
assert(bt == T_BYTE || bt == T_SHORT || bt == T_INT || bt == T_LONG, "unsupported element type");
vsetvli_helper(bt, vector_length);
vmv_s_x(tmp, src1);
Expand Down Expand Up @@ -2740,7 +2740,7 @@ void C2_MacroAssembler::reduce_integral_v(Register dst, Register src1,

// Set vl and vtype for full and partial vector operations.
// (vma = mu, vta = tu, vill = false)
void C2_MacroAssembler::vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul, Register tmp) {
void C2_MacroAssembler::vsetvli_helper(BasicType bt, uint vector_length, LMUL vlmul, Register tmp) {
Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
if (vector_length <= 31) {
vsetivli(tmp, vector_length, sew, vlmul);
Expand All @@ -2753,7 +2753,7 @@ void C2_MacroAssembler::vsetvli_helper(BasicType bt, int vector_length, LMUL vlm
}

void C2_MacroAssembler::compare_integral_v(VectorRegister vd, VectorRegister src1, VectorRegister src2,
int cond, BasicType bt, int vector_length, VectorMask vm) {
int cond, BasicType bt, uint vector_length, VectorMask vm) {
assert(is_integral_type(bt), "unsupported element type");
assert(vm == Assembler::v0_t ? vd != v0 : true, "should be different registers");
vsetvli_helper(bt, vector_length);
Expand All @@ -2772,7 +2772,7 @@ void C2_MacroAssembler::compare_integral_v(VectorRegister vd, VectorRegister src
}

void C2_MacroAssembler::compare_fp_v(VectorRegister vd, VectorRegister src1, VectorRegister src2,
int cond, BasicType bt, int vector_length, VectorMask vm) {
int cond, BasicType bt, uint vector_length, VectorMask vm) {
assert(is_floating_point_type(bt), "unsupported element type");
assert(vm == Assembler::v0_t ? vd != v0 : true, "should be different registers");
vsetvli_helper(bt, vector_length);
Expand All @@ -2790,7 +2790,7 @@ void C2_MacroAssembler::compare_fp_v(VectorRegister vd, VectorRegister src1, Vec
}
}

void C2_MacroAssembler::integer_extend_v(VectorRegister dst, BasicType dst_bt, int vector_length,
void C2_MacroAssembler::integer_extend_v(VectorRegister dst, BasicType dst_bt, uint vector_length,
VectorRegister src, BasicType src_bt) {
assert(type2aelembytes(dst_bt) > type2aelembytes(src_bt) && type2aelembytes(dst_bt) <= 8 && type2aelembytes(src_bt) <= 4, "invalid element size");
assert(dst_bt != T_FLOAT && dst_bt != T_DOUBLE && src_bt != T_FLOAT && src_bt != T_DOUBLE, "unsupported element type");
Expand Down Expand Up @@ -2828,7 +2828,7 @@ void C2_MacroAssembler::integer_extend_v(VectorRegister dst, BasicType dst_bt, i

// Vector narrow from src to dst with specified element sizes.
// High part of dst vector will be filled with zero.
void C2_MacroAssembler::integer_narrow_v(VectorRegister dst, BasicType dst_bt, int vector_length,
void C2_MacroAssembler::integer_narrow_v(VectorRegister dst, BasicType dst_bt, uint vector_length,
VectorRegister src, BasicType src_bt) {
assert(type2aelembytes(dst_bt) < type2aelembytes(src_bt) && type2aelembytes(dst_bt) <= 4 && type2aelembytes(src_bt) <= 8, "invalid element size");
assert(dst_bt != T_FLOAT && dst_bt != T_DOUBLE && src_bt != T_FLOAT && src_bt != T_DOUBLE, "unsupported element type");
Expand Down
26 changes: 13 additions & 13 deletions src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -156,9 +156,9 @@
vl1r_v(v, t0);
}

void spill_copy_vector_stack_to_stack(int src_offset, int dst_offset, int vector_length_in_bytes) {
void spill_copy_vector_stack_to_stack(int src_offset, int dst_offset, uint vector_length_in_bytes) {
assert(vector_length_in_bytes % 16 == 0, "unexpected vector reg size");
for (int i = 0; i < vector_length_in_bytes / 8; i++) {
for (int i = 0; i < (int)vector_length_in_bytes / 8; i++) {
unspill(t0, true, src_offset + (i * 8));
spill(t0, true, dst_offset + (i * 8));
}
Expand Down Expand Up @@ -227,30 +227,30 @@

void minmax_fp_v(VectorRegister dst,
VectorRegister src1, VectorRegister src2,
BasicType bt, bool is_min, int vector_length);
BasicType bt, bool is_min, uint vector_length);

void minmax_fp_masked_v(VectorRegister dst, VectorRegister src1, VectorRegister src2,
VectorRegister vmask, VectorRegister tmp1, VectorRegister tmp2,
BasicType bt, bool is_min, int vector_length);
BasicType bt, bool is_min, uint vector_length);

void reduce_minmax_fp_v(FloatRegister dst,
FloatRegister src1, VectorRegister src2,
VectorRegister tmp1, VectorRegister tmp2,
bool is_double, bool is_min, int vector_length,
bool is_double, bool is_min, uint vector_length,
VectorMask vm = Assembler::unmasked);

void reduce_integral_v(Register dst, Register src1,
VectorRegister src2, VectorRegister tmp,
int opc, BasicType bt, int vector_length,
int opc, BasicType bt, uint vector_length,
VectorMask vm = Assembler::unmasked);

void vsetvli_helper(BasicType bt, int vector_length, LMUL vlmul = Assembler::m1, Register tmp = t0);
void vsetvli_helper(BasicType bt, uint vector_length, LMUL vlmul = Assembler::m1, Register tmp = t0);

void compare_integral_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
BasicType bt, uint vector_length, VectorMask vm = Assembler::unmasked);

void compare_fp_v(VectorRegister dst, VectorRegister src1, VectorRegister src2, int cond,
BasicType bt, int vector_length, VectorMask vm = Assembler::unmasked);
BasicType bt, uint vector_length, VectorMask vm = Assembler::unmasked);

// In Matcher::scalable_predicate_reg_slots,
// we assume each predicate register is one-eighth of the size of
Expand All @@ -267,18 +267,18 @@
vle8_v(v, t0);
}

void spill_copy_vmask_stack_to_stack(int src_offset, int dst_offset, int vector_length_in_bytes) {
void spill_copy_vmask_stack_to_stack(int src_offset, int dst_offset, uint vector_length_in_bytes) {
assert(vector_length_in_bytes % 4 == 0, "unexpected vector mask reg size");
for (int i = 0; i < vector_length_in_bytes / 4; i++) {
for (int i = 0; i < (int)vector_length_in_bytes / 4; i++) {
unspill(t0, false, src_offset + (i * 4));
spill(t0, false, dst_offset + (i * 4));
}
}

void integer_extend_v(VectorRegister dst, BasicType dst_bt, int vector_length,
void integer_extend_v(VectorRegister dst, BasicType dst_bt, uint vector_length,
VectorRegister src, BasicType src_bt);

void integer_narrow_v(VectorRegister dst, BasicType dst_bt, int vector_length,
void integer_narrow_v(VectorRegister dst, BasicType dst_bt, uint vector_length,
VectorRegister src, BasicType src_bt);

void vfcvt_rtz_x_f_v_safe(VectorRegister dst, VectorRegister src);
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/riscv_v.ad
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ source %{

static void loadStore(C2_MacroAssembler masm, bool is_store,
VectorRegister reg, BasicType bt, Register base,
int vector_length, Assembler::VectorMask vm = Assembler::unmasked) {
uint vector_length, Assembler::VectorMask vm = Assembler::unmasked) {
Assembler::SEW sew = Assembler::elemtype_to_sew(bt);
masm.vsetvli_helper(bt, vector_length);

Expand Down

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