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RealFYangRealFYang
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8347352: RISC-V: Cleanup bitwise AND assembler routines
Reviewed-by: rehn, fjiang, mli
1 parent afc4529 commit 4f3dc9d

5 files changed

+32
-41
lines changed

‎src/hotspot/cpu/riscv/assembler_riscv.hpp

+18-18
Original file line numberDiff line numberDiff line change
@@ -835,7 +835,7 @@ enum operand_size { int8, int16, int32, uint32, int64 };
835835

836836
// Immediate Instruction
837837
#define INSN(NAME, op, funct3) \
838-
void NAME(Register Rd, Register Rs1, int32_t imm) { \
838+
void NAME(Register Rd, Register Rs1, int64_t imm) { \
839839
guarantee(is_simm12(imm), "Immediate is out of validity"); \
840840
unsigned insn = 0; \
841841
patch((address)&insn, 6, 0, op); \
@@ -846,17 +846,17 @@ enum operand_size { int8, int16, int32, uint32, int64 };
846846
emit(insn); \
847847
}
848848

849-
INSN(_addi, 0b0010011, 0b000);
850-
INSN(slti, 0b0010011, 0b010);
851-
INSN(_addiw, 0b0011011, 0b000);
852-
INSN(_and_imm12, 0b0010011, 0b111);
853-
INSN(ori, 0b0010011, 0b110);
854-
INSN(xori, 0b0010011, 0b100);
849+
INSN(_addi, 0b0010011, 0b000);
850+
INSN(_addiw, 0b0011011, 0b000);
851+
INSN(_andi, 0b0010011, 0b111);
852+
INSN(ori, 0b0010011, 0b110);
853+
INSN(xori, 0b0010011, 0b100);
854+
INSN(slti, 0b0010011, 0b010);
855855

856856
#undef INSN
857857

858858
#define INSN(NAME, op, funct3) \
859-
void NAME(Register Rd, Register Rs1, uint32_t imm) { \
859+
void NAME(Register Rd, Register Rs1, uint64_t imm) { \
860860
guarantee(is_uimm12(imm), "Immediate is out of validity"); \
861861
unsigned insn = 0; \
862862
patch((address)&insn,6, 0, op); \
@@ -2230,7 +2230,7 @@ enum Nf {
22302230
}
22312231

22322232
#define INSN(NAME, funct3, op) \
2233-
void NAME(Register Rd_Rs1, int32_t imm) { \
2233+
void NAME(Register Rd_Rs1, int64_t imm) { \
22342234
assert_cond(is_simm6(imm)); \
22352235
uint16_t insn = 0; \
22362236
c_patch((address)&insn, 1, 0, op); \
@@ -2247,7 +2247,7 @@ enum Nf {
22472247
#undef INSN
22482248

22492249
#define INSN(NAME, funct3, op) \
2250-
void NAME(int32_t imm) { \
2250+
void NAME(int64_t imm) { \
22512251
assert_cond(is_simm10(imm)); \
22522252
assert_cond((imm & 0b1111) == 0); \
22532253
assert_cond(imm != 0); \
@@ -2268,7 +2268,7 @@ enum Nf {
22682268
#undef INSN
22692269

22702270
#define INSN(NAME, funct3, op) \
2271-
void NAME(Register Rd, uint32_t uimm) { \
2271+
void NAME(Register Rd, uint64_t uimm) { \
22722272
assert_cond(is_uimm10(uimm)); \
22732273
assert_cond((uimm & 0b11) == 0); \
22742274
assert_cond(uimm != 0); \
@@ -2325,7 +2325,7 @@ enum Nf {
23252325
#undef INSN
23262326

23272327
#define INSN(NAME, funct3, funct2, op) \
2328-
void NAME(Register Rd_Rs1, int32_t imm) { \
2328+
void NAME(Register Rd_Rs1, int64_t imm) { \
23292329
assert_cond(is_simm6(imm)); \
23302330
uint16_t insn = 0; \
23312331
c_patch((address)&insn, 1, 0, op); \
@@ -2950,7 +2950,7 @@ enum Nf {
29502950
// Immediate Instructions
29512951
// --------------------------
29522952
#define INSN(NAME) \
2953-
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2953+
void NAME(Register Rd, Register Rs1, int64_t imm) { \
29542954
/* addi -> c.addi/c.nop/c.mv/c.addi16sp/c.addi4spn */ \
29552955
if (do_compress()) { \
29562956
if (Rd == Rs1 && is_simm6(imm)) { \
@@ -2978,7 +2978,7 @@ enum Nf {
29782978

29792979
// --------------------------
29802980
#define INSN(NAME) \
2981-
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2981+
void NAME(Register Rd, Register Rs1, int64_t imm) { \
29822982
/* addiw -> c.addiw */ \
29832983
if (do_compress() && (Rd == Rs1 && Rd != x0 && is_simm6(imm))) { \
29842984
c_addiw(Rd, imm); \
@@ -2993,17 +2993,17 @@ enum Nf {
29932993

29942994
// --------------------------
29952995
#define INSN(NAME) \
2996-
void NAME(Register Rd, Register Rs1, int32_t imm) { \
2997-
/* and_imm12 -> c.andi */ \
2996+
void NAME(Register Rd, Register Rs1, int64_t imm) { \
2997+
/* andi -> c.andi */ \
29982998
if (do_compress() && \
29992999
(Rd == Rs1 && Rd->is_compressed_valid() && is_simm6(imm))) { \
30003000
c_andi(Rd, imm); \
30013001
return; \
30023002
} \
3003-
_and_imm12(Rd, Rs1, imm); \
3003+
_andi(Rd, Rs1, imm); \
30043004
}
30053005

3006-
INSN(and_imm12);
3006+
INSN(andi);
30073007

30083008
#undef INSN
30093009

‎src/hotspot/cpu/riscv/c1_MacroAssembler_riscv.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ void C1_MacroAssembler::allocate_array(Register obj, Register len, Register tmp1
301301
// align object end
302302
mv(arr_size, (int32_t)base_offset_in_bytes + MinObjAlignmentInBytesMask);
303303
shadd(arr_size, len, arr_size, t0, f);
304-
andi(arr_size, arr_size, ~(uint)MinObjAlignmentInBytesMask);
304+
andi(arr_size, arr_size, ~MinObjAlignmentInBytesMask);
305305

306306
try_allocate(obj, arr_size, 0, tmp1, tmp2, slow_case);
307307

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

+4-14
Original file line numberDiff line numberDiff line change
@@ -2619,7 +2619,7 @@ void MacroAssembler::sub(Register Rd, Register Rn, int64_t decrement, Register t
26192619
add(Rd, Rn, -decrement, tmp);
26202620
}
26212621

2622-
void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register tmp) {
2622+
void MacroAssembler::addw(Register Rd, Register Rn, int64_t increment, Register tmp) {
26232623
if (is_simm12(increment)) {
26242624
addiw(Rd, Rn, increment);
26252625
} else {
@@ -2629,7 +2629,7 @@ void MacroAssembler::addw(Register Rd, Register Rn, int32_t increment, Register
26292629
}
26302630
}
26312631

2632-
void MacroAssembler::subw(Register Rd, Register Rn, int32_t decrement, Register tmp) {
2632+
void MacroAssembler::subw(Register Rd, Register Rn, int64_t decrement, Register tmp) {
26332633
addw(Rd, Rn, -decrement, tmp);
26342634
}
26352635

@@ -2901,16 +2901,6 @@ void MacroAssembler::rolw(Register dst, Register src, uint32_t shift, Register t
29012901
orr(dst, dst, tmp);
29022902
}
29032903

2904-
void MacroAssembler::andi(Register Rd, Register Rn, int64_t imm, Register tmp) {
2905-
if (is_simm12(imm)) {
2906-
and_imm12(Rd, Rn, imm);
2907-
} else {
2908-
assert_different_registers(Rn, tmp);
2909-
mv(tmp, imm);
2910-
andr(Rd, Rn, tmp);
2911-
}
2912-
}
2913-
29142904
void MacroAssembler::orptr(Address adr, RegisterOrConstant src, Register tmp1, Register tmp2) {
29152905
ld(tmp1, adr);
29162906
if (src.is_register()) {
@@ -6142,10 +6132,10 @@ void MacroAssembler::test_bit(Register Rd, Register Rs, uint32_t bit_pos) {
61426132
}
61436133
int64_t imm = (int64_t)(1UL << bit_pos);
61446134
if (is_simm12(imm)) {
6145-
and_imm12(Rd, Rs, imm);
6135+
andi(Rd, Rs, imm);
61466136
} else {
61476137
srli(Rd, Rs, bit_pos);
6148-
and_imm12(Rd, Rd, 1);
6138+
andi(Rd, Rd, 1);
61496139
}
61506140
}
61516141

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

+7-7
Original file line numberDiff line numberDiff line change
@@ -886,17 +886,17 @@ class MacroAssembler: public Assembler {
886886
public:
887887

888888
// arith
889-
void add(Register Rd, Register Rn, int64_t increment, Register tmp = t0);
890-
void sub(Register Rd, Register Rn, int64_t decrement, Register tmp = t0);
891-
void addw(Register Rd, Register Rn, int32_t increment, Register tmp = t0);
892-
void subw(Register Rd, Register Rn, int32_t decrement, Register tmp = t0);
889+
void add (Register Rd, Register Rn, int64_t increment, Register tmp = t0);
890+
void sub (Register Rd, Register Rn, int64_t decrement, Register tmp = t0);
891+
void addw(Register Rd, Register Rn, int64_t increment, Register tmp = t0);
892+
void subw(Register Rd, Register Rn, int64_t decrement, Register tmp = t0);
893893

894-
void subi(Register Rd, Register Rn, int32_t decrement) {
894+
void subi(Register Rd, Register Rn, int64_t decrement) {
895895
assert(is_simm12(-decrement), "Must be");
896896
addi(Rd, Rn, -decrement);
897897
}
898898

899-
void subiw(Register Rd, Register Rn, int32_t decrement) {
899+
void subiw(Register Rd, Register Rn, int64_t decrement) {
900900
assert(is_simm12(-decrement), "Must be");
901901
addiw(Rd, Rn, -decrement);
902902
}
@@ -928,7 +928,7 @@ class MacroAssembler: public Assembler {
928928

929929
void ror(Register dst, Register src, uint32_t shift, Register tmp = t0);
930930
void rolw(Register dst, Register src, uint32_t shift, Register tmp = t0);
931-
void andi(Register Rd, Register Rn, int64_t imm, Register tmp = t0);
931+
932932
void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1);
933933

934934
// Load and Store Instructions

‎src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -1715,7 +1715,8 @@ nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
17151715
// NOTE: the oopMark is in swap_reg % 10 as the result of cmpxchg
17161716

17171717
__ sub(swap_reg, swap_reg, sp);
1718-
__ andi(swap_reg, swap_reg, 3 - (int)os::vm_page_size());
1718+
__ mv(t0, 3 - (int)os::vm_page_size());
1719+
__ andr(swap_reg, swap_reg, t0);
17191720

17201721
// Save the test result, for recursive case, the result is zero
17211722
__ sd(swap_reg, Address(lock_reg, mark_word_offset));

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