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8265403: consolidate definition of CPU features
Reviewed-by: kvn, iklam
  • Loading branch information
Doug Simon committed Apr 23, 2021
1 parent 20a373a commit 5aed446e20c4b93a518c2e43fcd2ccb8995d7c75
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2015, 2021, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, Red Hat Inc. All rights reserved. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -39,4 +39,7 @@

#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)

#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT)

#endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP
@@ -195,16 +195,9 @@ void VM_Version::initialize() {
char buf[512];
sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
if (_features & CPU_ASIMD) strcat(buf, ", simd");
if (_features & CPU_CRC32) strcat(buf, ", crc");
if (_features & CPU_AES) strcat(buf, ", aes");
if (_features & CPU_SHA1) strcat(buf, ", sha1");
if (_features & CPU_SHA2) strcat(buf, ", sha256");
if (_features & CPU_SHA3) strcat(buf, ", sha3");
if (_features & CPU_SHA512) strcat(buf, ", sha512");
if (_features & CPU_LSE) strcat(buf, ", lse");
if (_features & CPU_SVE) strcat(buf, ", sve");
if (_features & CPU_SVE2) strcat(buf, ", sve2");
#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (_features & CPU_##id) strcat(buf, ", " name);
CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
#undef ADD_FEATURE_IF_SUPPORTED

_features_string = os::strdup(buf);

@@ -97,23 +97,28 @@ class VM_Version : public Abstract_VM_Version {
};

enum Feature_Flag {
CPU_FP = (1<<0),
CPU_ASIMD = (1<<1),
CPU_EVTSTRM = (1<<2),
CPU_AES = (1<<3),
CPU_PMULL = (1<<4),
CPU_SHA1 = (1<<5),
CPU_SHA2 = (1<<6),
CPU_CRC32 = (1<<7),
CPU_LSE = (1<<8),
CPU_DCPOP = (1<<16),
CPU_SHA3 = (1<<17),
CPU_SHA512 = (1<<21),
CPU_SVE = (1<<22),
// flags above must follow Linux HWCAP
CPU_SVE2 = (1<<28),
CPU_STXR_PREFETCH= (1<<29),
CPU_A53MAC = (1<<30),
#define CPU_FEATURE_FLAGS(decl) \
decl(FP, "fp", 0) \
decl(ASIMD, "simd", 1) \
decl(EVTSTRM, "evtstrm", 2) \
decl(AES, "aes", 3) \
decl(PMULL, "pmull", 4) \
decl(SHA1, "sha1", 5) \
decl(SHA2, "sha256", 6) \
decl(CRC32, "crc", 7) \
decl(LSE, "lse", 8) \
decl(DCPOP, "dcpop", 16) \
decl(SHA3, "sha3", 17) \
decl(SHA512, "sha512", 21) \
decl(SVE, "sve", 22) \
/* flags above must follow Linux HWCAP */ \
decl(SVE2, "sve2", 28) \
decl(STXR_PREFETCH, "stxr_prefetch", 29) \
decl(A53MAC, "a53mac", 30)

#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1 << bit),
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
};

static int cpu_family() { return _cpu; }
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2001, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -39,52 +39,9 @@
declare_constant(frame::interpreter_frame_sender_sp_offset) \
declare_constant(frame::interpreter_frame_last_sp_offset)

#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
declare_constant(VM_Version::CPU_CX8) \
declare_constant(VM_Version::CPU_CMOV) \
declare_constant(VM_Version::CPU_FXSR) \
declare_constant(VM_Version::CPU_HT) \
declare_constant(VM_Version::CPU_MMX) \
declare_constant(VM_Version::CPU_3DNOW_PREFETCH) \
declare_constant(VM_Version::CPU_SSE) \
declare_constant(VM_Version::CPU_SSE2) \
declare_constant(VM_Version::CPU_SSE3) \
declare_constant(VM_Version::CPU_SSSE3) \
declare_constant(VM_Version::CPU_SSE4A) \
declare_constant(VM_Version::CPU_SSE4_1) \
declare_constant(VM_Version::CPU_SSE4_2) \
declare_constant(VM_Version::CPU_POPCNT) \
declare_constant(VM_Version::CPU_LZCNT) \
declare_constant(VM_Version::CPU_TSC) \
declare_constant(VM_Version::CPU_TSCINV) \
declare_constant(VM_Version::CPU_AVX) \
declare_constant(VM_Version::CPU_AVX2) \
declare_constant(VM_Version::CPU_AES) \
declare_constant(VM_Version::CPU_ERMS) \
declare_constant(VM_Version::CPU_CLMUL) \
declare_constant(VM_Version::CPU_BMI1) \
declare_constant(VM_Version::CPU_BMI2) \
declare_constant(VM_Version::CPU_RTM) \
declare_constant(VM_Version::CPU_ADX) \
declare_constant(VM_Version::CPU_AVX512F) \
declare_constant(VM_Version::CPU_AVX512DQ) \
declare_constant(VM_Version::CPU_AVX512PF) \
declare_constant(VM_Version::CPU_AVX512ER) \
declare_constant(VM_Version::CPU_AVX512CD) \
declare_constant(VM_Version::CPU_AVX512BW) \
declare_constant(VM_Version::CPU_AVX512VL) \
declare_constant(VM_Version::CPU_SHA) \
declare_constant(VM_Version::CPU_FMA) \
declare_constant(VM_Version::CPU_VZEROUPPER) \
declare_constant(VM_Version::CPU_AVX512_VPOPCNTDQ) \
declare_constant(VM_Version::CPU_AVX512_VPCLMULQDQ) \
declare_constant(VM_Version::CPU_AVX512_VAES) \
declare_constant(VM_Version::CPU_AVX512_VNNI) \
declare_constant(VM_Version::CPU_FLUSH) \
declare_constant(VM_Version::CPU_FLUSHOPT) \
declare_constant(VM_Version::CPU_CLWB) \
declare_constant(VM_Version::CPU_AVX512_VBMI2) \
declare_constant(VM_Version::CPU_AVX512_VBMI) \
declare_constant(VM_Version::CPU_HV)
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)

#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
#define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT)

#endif // CPU_X86_VMSTRUCTS_X86_HPP
@@ -45,7 +45,10 @@ int VM_Version::_model;
int VM_Version::_stepping;
bool VM_Version::_has_intel_jcc_erratum;
VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
const char* VM_Version::_features_names[] = { FEATURES_NAMES };

#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
#undef DECLARE_CPU_FEATURE_FLAG

// Address of instruction which causes SEGV
address VM_Version::_cpuinfo_segv_addr = 0;
@@ -782,7 +785,6 @@ void VM_Version::get_processor_features() {
cores_per_cpu(), threads_per_core(),
cpu_family(), _model, _stepping, os::cpu_microcode_revision());
assert(res > 0, "not enough temporary space allocated");
assert(log2i_exact((uint64_t)CPU_MAX_FEATURE) + 1 == sizeof(_features_names) / sizeof(char*), "wrong size features_names");
insert_features_names(buf + res, sizeof(buf) - res, _features_names);

_features_string = os::strdup(buf);
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -300,87 +300,74 @@ class VM_Version : public Abstract_VM_Version {
static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV

enum Feature_Flag : uint64_t {
CPU_CX8 = (1ULL << 0), // next bits are from cpuid 1 (EDX)
CPU_CMOV = (1ULL << 1),
CPU_FXSR = (1ULL << 2),
CPU_HT = (1ULL << 3),

CPU_MMX = (1ULL << 4),
CPU_3DNOW_PREFETCH = (1ULL << 5), // Processor supports 3dnow prefetch and prefetchw instructions
// may not necessarily support other 3dnow instructions
CPU_SSE = (1ULL << 6),
CPU_SSE2 = (1ULL << 7),

CPU_SSE3 = (1ULL << 8), // SSE3 comes from cpuid 1 (ECX)
CPU_SSSE3 = (1ULL << 9),
CPU_SSE4A = (1ULL << 10),
CPU_SSE4_1 = (1ULL << 11),

CPU_SSE4_2 = (1ULL << 12),
CPU_POPCNT = (1ULL << 13),
CPU_LZCNT = (1ULL << 14),
CPU_TSC = (1ULL << 15),

CPU_TSCINV_BIT = (1ULL << 16),
CPU_TSCINV = (1ULL << 17),
CPU_AVX = (1ULL << 18),
CPU_AVX2 = (1ULL << 19),

CPU_AES = (1ULL << 20),
CPU_ERMS = (1ULL << 21), // enhanced 'rep movsb/stosb' instructions
CPU_CLMUL = (1ULL << 22), // carryless multiply for CRC
CPU_BMI1 = (1ULL << 23),

CPU_BMI2 = (1ULL << 24),
CPU_RTM = (1ULL << 25), // Restricted Transactional Memory instructions
CPU_ADX = (1ULL << 26),
CPU_AVX512F = (1ULL << 27), // AVX 512bit foundation instructions

CPU_AVX512DQ = (1ULL << 28),
CPU_AVX512PF = (1ULL << 29),
CPU_AVX512ER = (1ULL << 30),
CPU_AVX512CD = (1ULL << 31),

CPU_AVX512BW = (1ULL << 32), // Byte and word vector instructions
CPU_AVX512VL = (1ULL << 33), // EVEX instructions with smaller vector length
CPU_SHA = (1ULL << 34), // SHA instructions
CPU_FMA = (1ULL << 35), // FMA instructions

CPU_VZEROUPPER = (1ULL << 36), // Vzeroupper instruction
CPU_AVX512_VPOPCNTDQ = (1ULL << 37), // Vector popcount
CPU_AVX512_VPCLMULQDQ = (1ULL << 38), // Vector carryless multiplication
CPU_AVX512_VAES = (1ULL << 39), // Vector AES instruction

CPU_AVX512_VNNI = (1ULL << 40), // Vector Neural Network Instructions
CPU_FLUSH = (1ULL << 41), // flush instruction
CPU_FLUSHOPT = (1ULL << 42), // flusopth instruction
CPU_CLWB = (1ULL << 43), // clwb instruction

CPU_AVX512_VBMI2 = (1ULL << 44), // VBMI2 shift left double instructions
CPU_AVX512_VBMI = (1ULL << 45), // Vector BMI instructions
CPU_HV = (1ULL << 46), // Hypervisor instructions

CPU_MAX_FEATURE = CPU_HV
#define CPU_FEATURE_FLAGS(decl) \
decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
decl(CMOV, "cmov", 1) \
decl(FXSR, "fxsr", 2) \
decl(HT, "ht", 3) \
\
decl(MMX, "mmx", 4) \
decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
/* may not necessarily support other 3dnow instructions */ \
decl(SSE, "sse", 6) \
decl(SSE2, "sse2", 7) \
\
decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
decl(SSSE3, "ssse3", 9 ) \
decl(SSE4A, "sse4a", 10) \
decl(SSE4_1, "sse4.1", 11) \
\
decl(SSE4_2, "sse4.2", 12) \
decl(POPCNT, "popcnt", 13) \
decl(LZCNT, "lzcnt", 14) \
decl(TSC, "tsc", 15) \
\
decl(TSCINV_BIT, "tscinvbit", 16) \
decl(TSCINV, "tscinv", 17) \
decl(AVX, "avx", 18) \
decl(AVX2, "avx2", 19) \
\
decl(AES, "aes", 20) \
decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
decl(BMI1, "bmi1", 23) \
\
decl(BMI2, "bmi2", 24) \
decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
decl(ADX, "adx", 26) \
decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
\
decl(AVX512DQ, "avx512dq", 28) \
decl(AVX512PF, "avx512pf", 29) \
decl(AVX512ER, "avx512er", 30) \
decl(AVX512CD, "avx512cd", 31) \
\
decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
decl(SHA, "sha", 34) /* SHA instructions */ \
decl(FMA, "fma", 35) /* FMA instructions */ \
\
decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
\
decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
decl(FLUSH, "clflush", 41) /* flush instruction */ \
decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
decl(CLWB, "clwb", 43) /* clwb instruction */ \
\
decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
decl(HV, "hv", 46) /* Hypervisor instructions */

#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
#undef DECLARE_CPU_FEATURE_FLAG
};

#define FEATURES_NAMES \
"cx8", "cmov", "fxsr", "ht", \
"mmx", "3dnowpref", "sse", "sse2", \
"sse3", "ssse3", "sse4a", "sse4.1", \
"sse4.2", "popcnt", "lzcnt", "tsc", \
"tscinvbit", "tscinv", "avx", "avx2", \
"aes", "erms", "clmul", "bmi1", \
"bmi2", "rtm", "adx", "avx512f", \
"avx512dq", "avx512pf", "avx512er", "avx512cd", \
"avx512bw", "avx512vl", "sha", "fma", \
"vzeroupper", "avx512_vpopcntdq", "avx512_vpclmulqdq", "avx512_vaes", \
"avx512_vnni", "clflush", "clflushopt", "clwb", \
"avx512_vmbi2", "avx512_vmbi", "hv"

static const char* _features_names[];

// NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().

enum Extended_Family {
// AMD
CPU_FAMILY_AMD_11H = 0x11,

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