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Doug Simon
committed
8265403: consolidate definition of CPU features
Reviewed-by: kvn, iklam
1 parent 20a373a commit 5aed446

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15 files changed

+258
-347
lines changed

15 files changed

+258
-347
lines changed

‎src/hotspot/cpu/aarch64/vmStructs_aarch64.hpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2015, 2019, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2015, 2021, Oracle and/or its affiliates. All rights reserved.
33
* Copyright (c) 2014, Red Hat Inc. All rights reserved. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
@@ -39,4 +39,7 @@
3939

4040
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)
4141

42+
#define DECLARE_INT_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_INT_CONSTANT_ENTRY(VM_Version::CPU_##id)
43+
#define VM_INT_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_INT_CPU_FEATURE_CONSTANT)
44+
4245
#endif // CPU_AARCH64_VMSTRUCTS_AARCH64_HPP

‎src/hotspot/cpu/aarch64/vm_version_aarch64.cpp‎

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -195,16 +195,9 @@ void VM_Version::initialize() {
195195
char buf[512];
196196
sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
197197
if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
198-
if (_features & CPU_ASIMD) strcat(buf, ", simd");
199-
if (_features & CPU_CRC32) strcat(buf, ", crc");
200-
if (_features & CPU_AES) strcat(buf, ", aes");
201-
if (_features & CPU_SHA1) strcat(buf, ", sha1");
202-
if (_features & CPU_SHA2) strcat(buf, ", sha256");
203-
if (_features & CPU_SHA3) strcat(buf, ", sha3");
204-
if (_features & CPU_SHA512) strcat(buf, ", sha512");
205-
if (_features & CPU_LSE) strcat(buf, ", lse");
206-
if (_features & CPU_SVE) strcat(buf, ", sve");
207-
if (_features & CPU_SVE2) strcat(buf, ", sve2");
198+
#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (_features & CPU_##id) strcat(buf, ", " name);
199+
CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
200+
#undef ADD_FEATURE_IF_SUPPORTED
208201

209202
_features_string = os::strdup(buf);
210203

‎src/hotspot/cpu/aarch64/vm_version_aarch64.hpp‎

Lines changed: 22 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -97,23 +97,28 @@ class VM_Version : public Abstract_VM_Version {
9797
};
9898

9999
enum Feature_Flag {
100-
CPU_FP = (1<<0),
101-
CPU_ASIMD = (1<<1),
102-
CPU_EVTSTRM = (1<<2),
103-
CPU_AES = (1<<3),
104-
CPU_PMULL = (1<<4),
105-
CPU_SHA1 = (1<<5),
106-
CPU_SHA2 = (1<<6),
107-
CPU_CRC32 = (1<<7),
108-
CPU_LSE = (1<<8),
109-
CPU_DCPOP = (1<<16),
110-
CPU_SHA3 = (1<<17),
111-
CPU_SHA512 = (1<<21),
112-
CPU_SVE = (1<<22),
113-
// flags above must follow Linux HWCAP
114-
CPU_SVE2 = (1<<28),
115-
CPU_STXR_PREFETCH= (1<<29),
116-
CPU_A53MAC = (1<<30),
100+
#define CPU_FEATURE_FLAGS(decl) \
101+
decl(FP, "fp", 0) \
102+
decl(ASIMD, "simd", 1) \
103+
decl(EVTSTRM, "evtstrm", 2) \
104+
decl(AES, "aes", 3) \
105+
decl(PMULL, "pmull", 4) \
106+
decl(SHA1, "sha1", 5) \
107+
decl(SHA2, "sha256", 6) \
108+
decl(CRC32, "crc", 7) \
109+
decl(LSE, "lse", 8) \
110+
decl(DCPOP, "dcpop", 16) \
111+
decl(SHA3, "sha3", 17) \
112+
decl(SHA512, "sha512", 21) \
113+
decl(SVE, "sve", 22) \
114+
/* flags above must follow Linux HWCAP */ \
115+
decl(SVE2, "sve2", 28) \
116+
decl(STXR_PREFETCH, "stxr_prefetch", 29) \
117+
decl(A53MAC, "a53mac", 30)
118+
119+
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1 << bit),
120+
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
121+
#undef DECLARE_CPU_FEATURE_FLAG
117122
};
118123

119124
static int cpu_family() { return _cpu; }

‎src/hotspot/cpu/x86/vmStructs_x86.hpp‎

Lines changed: 5 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2001, 2020, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2001, 2021, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -39,52 +39,9 @@
3939
declare_constant(frame::interpreter_frame_sender_sp_offset) \
4040
declare_constant(frame::interpreter_frame_last_sp_offset)
4141

42-
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) \
43-
declare_constant(VM_Version::CPU_CX8) \
44-
declare_constant(VM_Version::CPU_CMOV) \
45-
declare_constant(VM_Version::CPU_FXSR) \
46-
declare_constant(VM_Version::CPU_HT) \
47-
declare_constant(VM_Version::CPU_MMX) \
48-
declare_constant(VM_Version::CPU_3DNOW_PREFETCH) \
49-
declare_constant(VM_Version::CPU_SSE) \
50-
declare_constant(VM_Version::CPU_SSE2) \
51-
declare_constant(VM_Version::CPU_SSE3) \
52-
declare_constant(VM_Version::CPU_SSSE3) \
53-
declare_constant(VM_Version::CPU_SSE4A) \
54-
declare_constant(VM_Version::CPU_SSE4_1) \
55-
declare_constant(VM_Version::CPU_SSE4_2) \
56-
declare_constant(VM_Version::CPU_POPCNT) \
57-
declare_constant(VM_Version::CPU_LZCNT) \
58-
declare_constant(VM_Version::CPU_TSC) \
59-
declare_constant(VM_Version::CPU_TSCINV) \
60-
declare_constant(VM_Version::CPU_AVX) \
61-
declare_constant(VM_Version::CPU_AVX2) \
62-
declare_constant(VM_Version::CPU_AES) \
63-
declare_constant(VM_Version::CPU_ERMS) \
64-
declare_constant(VM_Version::CPU_CLMUL) \
65-
declare_constant(VM_Version::CPU_BMI1) \
66-
declare_constant(VM_Version::CPU_BMI2) \
67-
declare_constant(VM_Version::CPU_RTM) \
68-
declare_constant(VM_Version::CPU_ADX) \
69-
declare_constant(VM_Version::CPU_AVX512F) \
70-
declare_constant(VM_Version::CPU_AVX512DQ) \
71-
declare_constant(VM_Version::CPU_AVX512PF) \
72-
declare_constant(VM_Version::CPU_AVX512ER) \
73-
declare_constant(VM_Version::CPU_AVX512CD) \
74-
declare_constant(VM_Version::CPU_AVX512BW) \
75-
declare_constant(VM_Version::CPU_AVX512VL) \
76-
declare_constant(VM_Version::CPU_SHA) \
77-
declare_constant(VM_Version::CPU_FMA) \
78-
declare_constant(VM_Version::CPU_VZEROUPPER) \
79-
declare_constant(VM_Version::CPU_AVX512_VPOPCNTDQ) \
80-
declare_constant(VM_Version::CPU_AVX512_VPCLMULQDQ) \
81-
declare_constant(VM_Version::CPU_AVX512_VAES) \
82-
declare_constant(VM_Version::CPU_AVX512_VNNI) \
83-
declare_constant(VM_Version::CPU_FLUSH) \
84-
declare_constant(VM_Version::CPU_FLUSHOPT) \
85-
declare_constant(VM_Version::CPU_CLWB) \
86-
declare_constant(VM_Version::CPU_AVX512_VBMI2) \
87-
declare_constant(VM_Version::CPU_AVX512_VBMI) \
88-
declare_constant(VM_Version::CPU_HV)
42+
#define VM_LONG_CONSTANTS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant)
43+
44+
#define DECLARE_LONG_CPU_FEATURE_CONSTANT(id, name, bit) GENERATE_VM_LONG_CONSTANT_ENTRY(VM_Version::CPU_##id)
45+
#define VM_LONG_CPU_FEATURE_CONSTANTS CPU_FEATURE_FLAGS(DECLARE_LONG_CPU_FEATURE_CONSTANT)
8946

9047
#endif // CPU_X86_VMSTRUCTS_X86_HPP

‎src/hotspot/cpu/x86/vm_version_x86.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,10 @@ int VM_Version::_model;
4545
int VM_Version::_stepping;
4646
bool VM_Version::_has_intel_jcc_erratum;
4747
VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
48-
const char* VM_Version::_features_names[] = { FEATURES_NAMES };
48+
49+
#define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
50+
const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
51+
#undef DECLARE_CPU_FEATURE_FLAG
4952

5053
// Address of instruction which causes SEGV
5154
address VM_Version::_cpuinfo_segv_addr = 0;
@@ -782,7 +785,6 @@ void VM_Version::get_processor_features() {
782785
cores_per_cpu(), threads_per_core(),
783786
cpu_family(), _model, _stepping, os::cpu_microcode_revision());
784787
assert(res > 0, "not enough temporary space allocated");
785-
assert(log2i_exact((uint64_t)CPU_MAX_FEATURE) + 1 == sizeof(_features_names) / sizeof(char*), "wrong size features_names");
786788
insert_features_names(buf + res, sizeof(buf) - res, _features_names);
787789

788790
_features_string = os::strdup(buf);

‎src/hotspot/cpu/x86/vm_version_x86.hpp‎

Lines changed: 65 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -300,87 +300,74 @@ class VM_Version : public Abstract_VM_Version {
300300
static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
301301

302302
enum Feature_Flag : uint64_t {
303-
CPU_CX8 = (1ULL << 0), // next bits are from cpuid 1 (EDX)
304-
CPU_CMOV = (1ULL << 1),
305-
CPU_FXSR = (1ULL << 2),
306-
CPU_HT = (1ULL << 3),
307-
308-
CPU_MMX = (1ULL << 4),
309-
CPU_3DNOW_PREFETCH = (1ULL << 5), // Processor supports 3dnow prefetch and prefetchw instructions
310-
// may not necessarily support other 3dnow instructions
311-
CPU_SSE = (1ULL << 6),
312-
CPU_SSE2 = (1ULL << 7),
313-
314-
CPU_SSE3 = (1ULL << 8), // SSE3 comes from cpuid 1 (ECX)
315-
CPU_SSSE3 = (1ULL << 9),
316-
CPU_SSE4A = (1ULL << 10),
317-
CPU_SSE4_1 = (1ULL << 11),
318-
319-
CPU_SSE4_2 = (1ULL << 12),
320-
CPU_POPCNT = (1ULL << 13),
321-
CPU_LZCNT = (1ULL << 14),
322-
CPU_TSC = (1ULL << 15),
323-
324-
CPU_TSCINV_BIT = (1ULL << 16),
325-
CPU_TSCINV = (1ULL << 17),
326-
CPU_AVX = (1ULL << 18),
327-
CPU_AVX2 = (1ULL << 19),
328-
329-
CPU_AES = (1ULL << 20),
330-
CPU_ERMS = (1ULL << 21), // enhanced 'rep movsb/stosb' instructions
331-
CPU_CLMUL = (1ULL << 22), // carryless multiply for CRC
332-
CPU_BMI1 = (1ULL << 23),
333-
334-
CPU_BMI2 = (1ULL << 24),
335-
CPU_RTM = (1ULL << 25), // Restricted Transactional Memory instructions
336-
CPU_ADX = (1ULL << 26),
337-
CPU_AVX512F = (1ULL << 27), // AVX 512bit foundation instructions
338-
339-
CPU_AVX512DQ = (1ULL << 28),
340-
CPU_AVX512PF = (1ULL << 29),
341-
CPU_AVX512ER = (1ULL << 30),
342-
CPU_AVX512CD = (1ULL << 31),
343-
344-
CPU_AVX512BW = (1ULL << 32), // Byte and word vector instructions
345-
CPU_AVX512VL = (1ULL << 33), // EVEX instructions with smaller vector length
346-
CPU_SHA = (1ULL << 34), // SHA instructions
347-
CPU_FMA = (1ULL << 35), // FMA instructions
348-
349-
CPU_VZEROUPPER = (1ULL << 36), // Vzeroupper instruction
350-
CPU_AVX512_VPOPCNTDQ = (1ULL << 37), // Vector popcount
351-
CPU_AVX512_VPCLMULQDQ = (1ULL << 38), // Vector carryless multiplication
352-
CPU_AVX512_VAES = (1ULL << 39), // Vector AES instruction
353-
354-
CPU_AVX512_VNNI = (1ULL << 40), // Vector Neural Network Instructions
355-
CPU_FLUSH = (1ULL << 41), // flush instruction
356-
CPU_FLUSHOPT = (1ULL << 42), // flusopth instruction
357-
CPU_CLWB = (1ULL << 43), // clwb instruction
358-
359-
CPU_AVX512_VBMI2 = (1ULL << 44), // VBMI2 shift left double instructions
360-
CPU_AVX512_VBMI = (1ULL << 45), // Vector BMI instructions
361-
CPU_HV = (1ULL << 46), // Hypervisor instructions
362-
363-
CPU_MAX_FEATURE = CPU_HV
303+
#define CPU_FEATURE_FLAGS(decl) \
304+
decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
305+
decl(CMOV, "cmov", 1) \
306+
decl(FXSR, "fxsr", 2) \
307+
decl(HT, "ht", 3) \
308+
\
309+
decl(MMX, "mmx", 4) \
310+
decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
311+
/* may not necessarily support other 3dnow instructions */ \
312+
decl(SSE, "sse", 6) \
313+
decl(SSE2, "sse2", 7) \
314+
\
315+
decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
316+
decl(SSSE3, "ssse3", 9 ) \
317+
decl(SSE4A, "sse4a", 10) \
318+
decl(SSE4_1, "sse4.1", 11) \
319+
\
320+
decl(SSE4_2, "sse4.2", 12) \
321+
decl(POPCNT, "popcnt", 13) \
322+
decl(LZCNT, "lzcnt", 14) \
323+
decl(TSC, "tsc", 15) \
324+
\
325+
decl(TSCINV_BIT, "tscinvbit", 16) \
326+
decl(TSCINV, "tscinv", 17) \
327+
decl(AVX, "avx", 18) \
328+
decl(AVX2, "avx2", 19) \
329+
\
330+
decl(AES, "aes", 20) \
331+
decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
332+
decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
333+
decl(BMI1, "bmi1", 23) \
334+
\
335+
decl(BMI2, "bmi2", 24) \
336+
decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
337+
decl(ADX, "adx", 26) \
338+
decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
339+
\
340+
decl(AVX512DQ, "avx512dq", 28) \
341+
decl(AVX512PF, "avx512pf", 29) \
342+
decl(AVX512ER, "avx512er", 30) \
343+
decl(AVX512CD, "avx512cd", 31) \
344+
\
345+
decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
346+
decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
347+
decl(SHA, "sha", 34) /* SHA instructions */ \
348+
decl(FMA, "fma", 35) /* FMA instructions */ \
349+
\
350+
decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
351+
decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
352+
decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
353+
decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
354+
\
355+
decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
356+
decl(FLUSH, "clflush", 41) /* flush instruction */ \
357+
decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
358+
decl(CLWB, "clwb", 43) /* clwb instruction */ \
359+
\
360+
decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
361+
decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
362+
decl(HV, "hv", 46) /* Hypervisor instructions */
363+
364+
#define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
365+
CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
366+
#undef DECLARE_CPU_FEATURE_FLAG
364367
};
365368

366-
#define FEATURES_NAMES \
367-
"cx8", "cmov", "fxsr", "ht", \
368-
"mmx", "3dnowpref", "sse", "sse2", \
369-
"sse3", "ssse3", "sse4a", "sse4.1", \
370-
"sse4.2", "popcnt", "lzcnt", "tsc", \
371-
"tscinvbit", "tscinv", "avx", "avx2", \
372-
"aes", "erms", "clmul", "bmi1", \
373-
"bmi2", "rtm", "adx", "avx512f", \
374-
"avx512dq", "avx512pf", "avx512er", "avx512cd", \
375-
"avx512bw", "avx512vl", "sha", "fma", \
376-
"vzeroupper", "avx512_vpopcntdq", "avx512_vpclmulqdq", "avx512_vaes", \
377-
"avx512_vnni", "clflush", "clflushopt", "clwb", \
378-
"avx512_vmbi2", "avx512_vmbi", "hv"
379-
380369
static const char* _features_names[];
381370

382-
// NB! When adding new CPU feature detection consider updating vmStructs_x86.hpp, vmStructs_jvmci.hpp, and VM_Version::get_processor_features().
383-
384371
enum Extended_Family {
385372
// AMD
386373
CPU_FAMILY_AMD_11H = 0x11,

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