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Anjian-WenRealFYang
Anjian-Wen
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RealFYang
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8355074: RISC-V: C2: Support Vector-Scalar version of Zvbb Vector And-Not instruction
Reviewed-by: fjiang, fyang
1 parent a2f9c24 commit 5c06723

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‎src/hotspot/cpu/riscv/assembler_riscv.hpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2323,6 +2323,7 @@ enum Nf {
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}
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// Vector Bit-manipulation used in Cryptography (Zvbb) Extension
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INSN(vandn_vx, 0b1010111, 0b100, 0b000001);
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INSN(vrol_vx, 0b1010111, 0b100, 0b010101);
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INSN(vror_vx, 0b1010111, 0b100, 0b010100);
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‎src/hotspot/cpu/riscv/riscv_v.ad‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1187,6 +1187,70 @@ instruct vand_notL_masked(vReg dst_src1, vReg src2, immL_M1 m1, vRegMask_V0 v0)
11871187
ins_pipe(pipe_slow);
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%}
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1190+
instruct vand_notI_vx(vReg dst, vReg src1, iRegIorL2I src2, immI_M1 m1) %{
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predicate(UseZvbb);
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predicate(Matcher::vector_element_basic_type(n) == T_INT ||
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Matcher::vector_element_basic_type(n) == T_BYTE ||
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Matcher::vector_element_basic_type(n) == T_SHORT);
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match(Set dst (AndV src1 (Replicate (XorI src2 m1))));
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format %{ "vand_notI_vx $dst, $src1, $src2" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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__ vandn_vx(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg),
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as_Register($src2$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vand_notL_vx(vReg dst, vReg src1, iRegL src2, immL_M1 m1) %{
1208+
predicate(UseZvbb);
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predicate(Matcher::vector_element_basic_type(n) == T_LONG);
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match(Set dst (AndV src1 (Replicate (XorL src2 m1))));
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format %{ "vand_notL_vx $dst, $src1, $src2" %}
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ins_encode %{
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__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
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__ vandn_vx(as_VectorRegister($dst$$reg),
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as_VectorRegister($src1$$reg),
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as_Register($src2$$reg));
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vand_notI_vx_masked(vReg dst_src1, iRegIorL2I src2, immI_M1 m1, vRegMask_V0 v0) %{
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predicate(UseZvbb);
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predicate(Matcher::vector_element_basic_type(n) == T_INT ||
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Matcher::vector_element_basic_type(n) == T_BYTE ||
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Matcher::vector_element_basic_type(n) == T_SHORT);
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match(Set dst_src1 (AndV (Binary dst_src1 (Replicate (XorI src2 m1))) v0));
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format %{ "vand_notI_vx_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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BasicType bt = Matcher::vector_element_basic_type(this);
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__ vsetvli_helper(bt, Matcher::vector_length(this));
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__ vandn_vx(as_VectorRegister($dst_src1$$reg),
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as_VectorRegister($dst_src1$$reg),
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as_Register($src2$$reg),
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Assembler::v0_t);
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%}
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ins_pipe(pipe_slow);
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%}
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instruct vand_notL_vx_masked(vReg dst_src1, iRegL src2, immL_M1 m1, vRegMask_V0 v0) %{
1240+
predicate(UseZvbb);
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predicate(Matcher::vector_element_basic_type(n) == T_LONG);
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match(Set dst_src1 (AndV (Binary dst_src1 (Replicate (XorL src2 m1))) v0));
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format %{ "vand_notL_vx_masked $dst_src1, $dst_src1, $src2, $v0" %}
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ins_encode %{
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__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
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__ vandn_vx(as_VectorRegister($dst_src1$$reg),
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as_VectorRegister($dst_src1$$reg),
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as_Register($src2$$reg),
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Assembler::v0_t);
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%}
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ins_pipe(pipe_slow);
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%}
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// ------------------------------ Vector not -----------------------------------
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// vector not

‎test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2136,6 +2136,26 @@ public class IRNode {
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machOnlyNameRegex(VAND_NOT_L_MASKED, "vand_notL_masked");
21372137
}
21382138

2139+
public static final String RISCV_VAND_NOTI_VX = PREFIX + "RISCV_VAND_NOTI_VX" + POSTFIX;
2140+
static {
2141+
machOnlyNameRegex(RISCV_VAND_NOTI_VX, "vand_notI_vx");
2142+
}
2143+
2144+
public static final String RISCV_VAND_NOTL_VX = PREFIX + "RISCV_VAND_NOTL_VX" + POSTFIX;
2145+
static {
2146+
machOnlyNameRegex(RISCV_VAND_NOTL_VX, "vand_notL_vx");
2147+
}
2148+
2149+
public static final String RISCV_VAND_NOTI_VX_MASKED = PREFIX + "RISCV_VAND_NOTI_VX_MASKED" + POSTFIX;
2150+
static {
2151+
machOnlyNameRegex(RISCV_VAND_NOTI_VX_MASKED, "vand_notI_vx_masked");
2152+
}
2153+
2154+
public static final String RISCV_VAND_NOTL_VX_MASKED = PREFIX + "RISCV_VAND_NOTL_VX_MASKED" + POSTFIX;
2155+
static {
2156+
machOnlyNameRegex(RISCV_VAND_NOTL_VX_MASKED, "vand_notL_vx_masked");
2157+
}
2158+
21392159
public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX;
21402160
static {
21412161
vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE);

‎test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,68 @@ public static void testVectorVAndNotLMasked() {
154154
}
155155
}
156156

157+
@Test
158+
@Warmup(10000)
159+
@IR(counts = { IRNode.RISCV_VAND_NOTI_VX, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
160+
public static void testAllBitsSetVectorRegI() {
161+
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
162+
int bs = ib[0];
163+
av.not().lanewise(VectorOperators.AND_NOT, bs).intoArray(ir, 0);
164+
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// Verify results
166+
for (int i = 0; i < I_SPECIES.length(); i++) {
167+
Asserts.assertEquals((~ia[i]) & (~bs), ir[i]);
168+
}
169+
}
170+
171+
@Test
172+
@Warmup(10000)
173+
@IR(counts = { IRNode.RISCV_VAND_NOTL_VX, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
174+
public static void testAllBitsSetVectorRegL() {
175+
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
176+
long bs = lb[0];
177+
av.not().lanewise(VectorOperators.AND_NOT, bs).intoArray(lr, 0);
178+
179+
// Verify results
180+
for (int i = 0; i < L_SPECIES.length(); i++) {
181+
Asserts.assertEquals((~la[i]) & (~bs), lr[i]);
182+
}
183+
}
184+
185+
@Test
186+
@Warmup(10000)
187+
@IR(counts = { IRNode.RISCV_VAND_NOTI_VX_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
188+
public static void testAllBitsSetVectorRegIMask() {
189+
VectorMask<Integer> avm = VectorMask.fromArray(I_SPECIES, ma, 0);
190+
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
191+
int bs = ib[0];
192+
av.not().lanewise(VectorOperators.AND_NOT, bs, avm).intoArray(ir, 0);
193+
194+
// Verify results
195+
for (int i = 0; i < I_SPECIES.length(); i++) {
196+
if (ma[i] == true) {
197+
Asserts.assertEquals((~ia[i]) & (~bs), ir[i]);
198+
}
199+
}
200+
}
201+
202+
@Test
203+
@Warmup(10000)
204+
@IR(counts = { IRNode.RISCV_VAND_NOTL_VX_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
205+
public static void testAllBitsSetVectorRegLMask() {
206+
VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
207+
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
208+
long bs = lb[0];
209+
av.not().lanewise(VectorOperators.AND_NOT, bs, avm).intoArray(lr, 0);
210+
211+
// Verify results
212+
for (int i = 0; i < L_SPECIES.length(); i++) {
213+
if (ma[i] == true) {
214+
Asserts.assertEquals((~la[i]) & (~bs), lr[i]);
215+
}
216+
}
217+
}
218+
157219
@Test
158220
@Warmup(10000)
159221
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"})

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